source: rtems/c/src/lib/libcpu/arm/shared/include/cache.h @ 7b96f4b8

4.104.115
Last change on this file since 7b96f4b8 was 39c8fdb, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 01/12/10 at 15:03:22

add support for lpc32xx
  • Property mode set to 100644
File size: 2.8 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup arm
5 *
6 * @brief ARM cache defines and implementation.
7 */
8
9/*
10 * Copyright (c) 2009
11 * embedded brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * <rtems@embedded-brains.de>
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http://www.rtems.com/license/LICENSE.
20 */
21
22#ifndef LIBCPU_ARM_CACHE_H
23#define LIBCPU_ARM_CACHE_H
24
25#ifdef __ARM_ARCH_5TEJ__
26  #include <libcpu/arm-cp15.h>
27
28  #define CPU_DATA_CACHE_ALIGNMENT 32
29  #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
30
31  static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
32  {
33    arm_cp15_data_cache_clean_line(d_addr);
34  }
35
36  static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
37  {
38    arm_cp15_data_cache_invalidate_line(d_addr);
39  }
40
41  static inline void _CPU_cache_freeze_data(void)
42  {
43    /* TODO */
44  }
45
46  static inline void _CPU_cache_unfreeze_data(void)
47  {
48    /* TODO */
49  }
50
51  static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
52  {
53    arm_cp15_instruction_cache_invalidate_line(d_addr);
54  }
55
56  static inline void _CPU_cache_freeze_instruction(void)
57  {
58    /* TODO */
59  }
60
61  static inline void _CPU_cache_unfreeze_instruction(void)
62  {
63    /* TODO */
64  }
65
66  static inline void _CPU_cache_flush_entire_data(void)
67  {
68    arm_cp15_data_cache_test_and_clean();
69  }
70
71  static inline void _CPU_cache_invalidate_entire_data(void)
72  {
73    arm_cp15_data_cache_invalidate();
74  }
75
76  static inline void _CPU_cache_enable_data(void)
77  {
78    rtems_interrupt_level level;
79    uint32_t ctrl;
80
81    rtems_interrupt_disable(level);
82    ctrl = arm_cp15_get_control();
83    ctrl |= ARM_CP15_CTRL_C;
84    arm_cp15_set_control(ctrl);
85    rtems_interrupt_enable(level);
86  }
87
88  static inline void _CPU_cache_disable_data(void)
89  {
90    rtems_interrupt_level level;
91    uint32_t ctrl;
92
93    rtems_interrupt_disable(level);
94    ctrl = arm_cp15_get_control();
95    ctrl &= ~ARM_CP15_CTRL_C;
96    arm_cp15_set_control(ctrl);
97    rtems_interrupt_enable(level);
98
99    arm_cp15_data_cache_test_and_clean_and_invalidate();
100  }
101
102  static inline void _CPU_cache_invalidate_entire_instruction(void)
103  {
104    arm_cp15_instruction_cache_invalidate();
105  }
106
107  static inline void _CPU_cache_enable_instruction(void)
108  {
109    rtems_interrupt_level level;
110    uint32_t ctrl;
111
112    rtems_interrupt_disable(level);
113    ctrl = arm_cp15_get_control();
114    ctrl |= ARM_CP15_CTRL_I;
115    arm_cp15_set_control(ctrl);
116    rtems_interrupt_enable(level);
117  }
118
119  static inline void _CPU_cache_disable_instruction(void)
120  {
121    rtems_interrupt_level level;
122    uint32_t ctrl;
123
124    rtems_interrupt_disable(level);
125    ctrl = arm_cp15_get_control();
126    ctrl &= ~ARM_CP15_CTRL_I;
127    arm_cp15_set_control(ctrl);
128    rtems_interrupt_enable(level);
129  }
130#endif
131
132#endif /* LIBCPU_ARM_CACHE_H */
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