1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup ScoreCPUARMCP15 |
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5 | * |
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6 | * @brief ARM co-processor 15 (CP15) API. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009, 2010 |
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11 | * embedded brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * <rtems@embedded-brains.de> |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.com/license/LICENSE. |
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20 | */ |
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21 | |
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22 | #ifndef LIBCPU_SHARED_ARM_CP15_H |
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23 | #define LIBCPU_SHARED_ARM_CP15_H |
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24 | |
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25 | #include <rtems.h> |
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26 | |
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27 | #ifdef __cplusplus |
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28 | extern "C" { |
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29 | #endif /* __cplusplus */ |
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30 | |
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31 | #define ARM_CP15_CACHE_PREPARE_MVA(mva) \ |
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32 | ((const void *) (((uint32_t) (mva)) & ~0x1fU)) |
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33 | |
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34 | #define ARM_CP15_TLB_PREPARE_MVA(mva) \ |
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35 | ((const void *) (((uint32_t) (mva)) & ~0x3fU)) |
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36 | |
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37 | /** |
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38 | * @defgroup ScoreCPUARMCP15 ARM Co-Processor 15 Support |
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39 | * |
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40 | * @ingroup ScoreCPUARM |
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41 | * |
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42 | * @brief ARM co-processor 15 (CP15) support. |
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43 | * |
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44 | * @{ |
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45 | */ |
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46 | |
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47 | /** |
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48 | * @name MMU Defines |
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49 | * |
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50 | * @{ |
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51 | */ |
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52 | |
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53 | #define ARM_MMU_SECT_BASE_SHIFT 20 |
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54 | #define ARM_MMU_SECT_BASE_MASK (0xfffU << ARM_MMU_SECT_BASE_SHIFT) |
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55 | #define ARM_MMU_SECT_DOMAIN_SHIFT 5 |
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56 | #define ARM_MMU_SECT_DOMAIN_MASK (0xfU << ARM_MMU_SECT_DOMAIN_SHIFT) |
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57 | #define ARM_MMU_SECT_AP_1 (1U << 11) |
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58 | #define ARM_MMU_SECT_AP_0 (1U << 10) |
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59 | #define ARM_MMU_SECT_AP_SHIFT 10 |
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60 | #define ARM_MMU_SECT_AP_MASK (0x3U << ARM_MMU_SECT_AP_SHIFT) |
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61 | #define ARM_MMU_SECT_C (1U << 3) |
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62 | #define ARM_MMU_SECT_B (1U << 2) |
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63 | #define ARM_MMU_SECT_DEFAULT 0x12U |
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64 | #define ARM_MMU_SECT_GET_INDEX(mva) \ |
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65 | (((uint32_t) (mva)) >> ARM_MMU_SECT_BASE_SHIFT) |
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66 | #define ARM_MMU_SECT_MVA_ALIGN_UP(mva) \ |
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67 | ((1U << ARM_MMU_SECT_BASE_SHIFT) \ |
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68 | + ((((uint32_t) (mva) - 1U)) & ~((1U << ARM_MMU_SECT_BASE_SHIFT) - 1U))) |
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69 | |
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70 | #define ARM_MMU_TRANSLATION_TABLE_ENTRY_SIZE 4U |
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71 | #define ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT 4096U |
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72 | |
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73 | /** @} */ |
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74 | |
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75 | /** |
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76 | * @name Control Register Defines |
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77 | * |
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78 | * @{ |
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79 | */ |
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80 | |
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81 | #define ARM_CP15_CTRL_L4 (1U << 15) |
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82 | #define ARM_CP15_CTRL_RR (1U << 14) |
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83 | #define ARM_CP15_CTRL_V (1U << 13) |
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84 | #define ARM_CP15_CTRL_I (1U << 12) |
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85 | #define ARM_CP15_CTRL_R (1U << 9) |
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86 | #define ARM_CP15_CTRL_S (1U << 8) |
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87 | #define ARM_CP15_CTRL_B (1U << 7) |
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88 | #define ARM_CP15_CTRL_C (1U << 2) |
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89 | #define ARM_CP15_CTRL_A (1U << 1) |
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90 | #define ARM_CP15_CTRL_M (1U << 0) |
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91 | |
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92 | /** @} */ |
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93 | |
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94 | /** |
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95 | * @name Domain Access Control Defines |
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96 | * |
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97 | * @{ |
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98 | */ |
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99 | |
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100 | #define ARM_CP15_DAC_NO_ACCESS 0x0U |
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101 | #define ARM_CP15_DAC_CLIENT 0x1U |
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102 | #define ARM_CP15_DAC_MANAGER 0x3U |
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103 | #define ARM_CP15_DAC_DOMAIN(index, val) ((val) << (2 * index)) |
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104 | |
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105 | /** @} */ |
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106 | |
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107 | static inline uint32_t arm_cp15_get_id_code(void) |
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108 | { |
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109 | ARM_SWITCH_REGISTERS; |
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110 | uint32_t val; |
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111 | |
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112 | __asm__ volatile ( |
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113 | ARM_SWITCH_TO_ARM |
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114 | "mrc p15, 0, %[val], c0, c0, 0\n" |
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115 | ARM_SWITCH_BACK |
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116 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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117 | ); |
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118 | |
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119 | return val; |
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120 | } |
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121 | |
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122 | static inline uint32_t arm_cp15_get_tcm_status(void) |
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123 | { |
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124 | ARM_SWITCH_REGISTERS; |
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125 | uint32_t val; |
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126 | |
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127 | __asm__ volatile ( |
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128 | ARM_SWITCH_TO_ARM |
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129 | "mrc p15, 0, %[val], c0, c0, 2\n" |
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130 | ARM_SWITCH_BACK |
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131 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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132 | ); |
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133 | |
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134 | return val; |
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135 | } |
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136 | |
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137 | static inline uint32_t arm_cp15_get_control(void) |
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138 | { |
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139 | ARM_SWITCH_REGISTERS; |
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140 | uint32_t val; |
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141 | |
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142 | __asm__ volatile ( |
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143 | ARM_SWITCH_TO_ARM |
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144 | "mrc p15, 0, %[val], c1, c0, 0\n" |
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145 | ARM_SWITCH_BACK |
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146 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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147 | ); |
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148 | |
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149 | return val; |
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150 | } |
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151 | |
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152 | static inline void arm_cp15_set_control(uint32_t val) |
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153 | { |
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154 | ARM_SWITCH_REGISTERS; |
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155 | |
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156 | __asm__ volatile ( |
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157 | ARM_SWITCH_TO_ARM |
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158 | "mcr p15, 0, %[val], c1, c0, 0\n" |
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159 | "nop\n" |
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160 | "nop\n" |
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161 | ARM_SWITCH_BACK |
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162 | : ARM_SWITCH_OUTPUT |
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163 | : [val] "r" (val) |
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164 | : "memory" |
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165 | ); |
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166 | } |
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167 | |
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168 | /** |
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169 | * @name MMU Functions |
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170 | * |
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171 | * @{ |
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172 | */ |
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173 | |
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174 | static inline uint32_t *arm_cp15_get_translation_table_base(void) |
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175 | { |
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176 | ARM_SWITCH_REGISTERS; |
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177 | uint32_t *base; |
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178 | |
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179 | __asm__ volatile ( |
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180 | ARM_SWITCH_TO_ARM |
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181 | "mrc p15, 0, %[base], c2, c0, 0\n" |
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182 | ARM_SWITCH_BACK |
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183 | : [base] "=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT |
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184 | ); |
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185 | |
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186 | return base; |
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187 | } |
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188 | |
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189 | static inline void arm_cp15_set_translation_table_base(uint32_t *base) |
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190 | { |
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191 | ARM_SWITCH_REGISTERS; |
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192 | |
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193 | __asm__ volatile ( |
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194 | ARM_SWITCH_TO_ARM |
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195 | "mcr p15, 0, %[base], c2, c0, 0\n" |
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196 | ARM_SWITCH_BACK |
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197 | : ARM_SWITCH_OUTPUT |
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198 | : [base] "r" (base) |
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199 | ); |
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200 | } |
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201 | |
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202 | static inline uint32_t arm_cp15_get_domain_access_control(void) |
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203 | { |
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204 | ARM_SWITCH_REGISTERS; |
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205 | uint32_t val; |
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206 | |
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207 | __asm__ volatile ( |
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208 | ARM_SWITCH_TO_ARM |
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209 | "mrc p15, 0, %[val], c3, c0, 0\n" |
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210 | ARM_SWITCH_BACK |
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211 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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212 | ); |
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213 | |
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214 | return val; |
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215 | } |
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216 | |
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217 | static inline void arm_cp15_set_domain_access_control(uint32_t val) |
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218 | { |
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219 | ARM_SWITCH_REGISTERS; |
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220 | |
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221 | __asm__ volatile ( |
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222 | ARM_SWITCH_TO_ARM |
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223 | "mcr p15, 0, %[val], c3, c0, 0\n" |
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224 | ARM_SWITCH_BACK |
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225 | : ARM_SWITCH_OUTPUT |
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226 | : [val] "r" (val) |
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227 | ); |
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228 | } |
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229 | |
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230 | static inline uint32_t arm_cp15_get_data_fault_status(void) |
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231 | { |
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232 | ARM_SWITCH_REGISTERS; |
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233 | uint32_t val; |
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234 | |
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235 | __asm__ volatile ( |
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236 | ARM_SWITCH_TO_ARM |
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237 | "mrc p15, 0, %[val], c5, c0, 0\n" |
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238 | ARM_SWITCH_BACK |
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239 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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240 | ); |
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241 | |
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242 | return val; |
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243 | } |
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244 | |
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245 | static inline void arm_cp15_set_data_fault_status(uint32_t val) |
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246 | { |
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247 | ARM_SWITCH_REGISTERS; |
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248 | |
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249 | __asm__ volatile ( |
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250 | ARM_SWITCH_TO_ARM |
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251 | "mcr p15, 0, %[val], c5, c0, 0\n" |
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252 | ARM_SWITCH_BACK |
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253 | : ARM_SWITCH_OUTPUT |
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254 | : [val] "r" (val) |
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255 | ); |
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256 | } |
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257 | |
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258 | static inline uint32_t arm_cp15_get_instruction_fault_status(void) |
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259 | { |
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260 | ARM_SWITCH_REGISTERS; |
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261 | uint32_t val; |
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262 | |
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263 | __asm__ volatile ( |
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264 | ARM_SWITCH_TO_ARM |
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265 | "mrc p15, 0, %[val], c5, c0, 1\n" |
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266 | ARM_SWITCH_BACK |
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267 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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268 | ); |
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269 | |
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270 | return val; |
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271 | } |
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272 | |
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273 | static inline void arm_cp15_set_instruction_fault_status(uint32_t val) |
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274 | { |
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275 | ARM_SWITCH_REGISTERS; |
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276 | |
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277 | __asm__ volatile ( |
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278 | ARM_SWITCH_TO_ARM |
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279 | "mcr p15, 0, %[val], c5, c0, 1\n" |
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280 | ARM_SWITCH_BACK |
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281 | : ARM_SWITCH_OUTPUT |
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282 | : [val] "r" (val) |
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283 | ); |
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284 | } |
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285 | |
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286 | static inline void *arm_cp15_get_fault_address(void) |
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287 | { |
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288 | ARM_SWITCH_REGISTERS; |
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289 | void *mva; |
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290 | |
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291 | __asm__ volatile ( |
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292 | ARM_SWITCH_TO_ARM |
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293 | "mrc p15, 0, %[mva], c6, c0, 0\n" |
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294 | ARM_SWITCH_BACK |
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295 | : [mva] "=&r" (mva) ARM_SWITCH_ADDITIONAL_OUTPUT |
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296 | ); |
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297 | |
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298 | return mva; |
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299 | } |
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300 | |
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301 | static inline void arm_cp15_set_fault_address(const void *mva) |
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302 | { |
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303 | ARM_SWITCH_REGISTERS; |
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304 | |
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305 | __asm__ volatile ( |
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306 | ARM_SWITCH_TO_ARM |
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307 | "mcr p15, 0, %[mva], c6, c0, 0\n" |
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308 | ARM_SWITCH_BACK |
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309 | : ARM_SWITCH_OUTPUT |
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310 | : [mva] "r" (mva) |
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311 | ); |
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312 | } |
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313 | |
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314 | static inline void arm_cp15_tlb_invalidate(void) |
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315 | { |
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316 | ARM_SWITCH_REGISTERS; |
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317 | uint32_t sbz = 0; |
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318 | |
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319 | __asm__ volatile ( |
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320 | ARM_SWITCH_TO_ARM |
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321 | "mcr p15, 0, %[sbz], c8, c7, 0\n" |
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322 | ARM_SWITCH_BACK |
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323 | : ARM_SWITCH_OUTPUT |
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324 | : [sbz] "r" (sbz) |
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325 | ); |
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326 | } |
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327 | |
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328 | static inline void arm_cp15_tlb_invalidate_entry(const void *mva) |
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329 | { |
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330 | ARM_SWITCH_REGISTERS; |
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331 | |
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332 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
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333 | |
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334 | __asm__ volatile ( |
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335 | ARM_SWITCH_TO_ARM |
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336 | "mcr p15, 0, %[mva], c8, c7, 1\n" |
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337 | ARM_SWITCH_BACK |
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338 | : ARM_SWITCH_OUTPUT |
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339 | : [mva] "r" (mva) |
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340 | ); |
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341 | } |
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342 | |
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343 | static inline void arm_cp15_tlb_instruction_invalidate(void) |
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344 | { |
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345 | ARM_SWITCH_REGISTERS; |
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346 | uint32_t sbz = 0; |
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347 | |
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348 | __asm__ volatile ( |
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349 | ARM_SWITCH_TO_ARM |
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350 | "mcr p15, 0, %[sbz], c8, c5, 0\n" |
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351 | ARM_SWITCH_BACK |
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352 | : ARM_SWITCH_OUTPUT |
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353 | : [sbz] "r" (sbz) |
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354 | ); |
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355 | } |
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356 | |
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357 | static inline void arm_cp15_tlb_instruction_invalidate_entry(const void *mva) |
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358 | { |
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359 | ARM_SWITCH_REGISTERS; |
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360 | |
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361 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
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362 | |
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363 | __asm__ volatile ( |
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364 | ARM_SWITCH_TO_ARM |
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365 | "mcr p15, 0, %[mva], c8, c5, 1\n" |
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366 | ARM_SWITCH_BACK |
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367 | : ARM_SWITCH_OUTPUT |
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368 | : [mva] "r" (mva) |
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369 | ); |
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370 | } |
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371 | |
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372 | static inline void arm_cp15_tlb_data_invalidate(void) |
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373 | { |
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374 | ARM_SWITCH_REGISTERS; |
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375 | uint32_t sbz = 0; |
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376 | |
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377 | __asm__ volatile ( |
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378 | ARM_SWITCH_TO_ARM |
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379 | "mcr p15, 0, %[sbz], c8, c6, 0\n" |
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380 | ARM_SWITCH_BACK |
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381 | : ARM_SWITCH_OUTPUT |
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382 | : [sbz] "r" (sbz) |
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383 | ); |
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384 | } |
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385 | |
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386 | static inline void arm_cp15_tlb_data_invalidate_entry(const void *mva) |
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387 | { |
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388 | ARM_SWITCH_REGISTERS; |
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389 | |
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390 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
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391 | |
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392 | __asm__ volatile ( |
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393 | ARM_SWITCH_TO_ARM |
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394 | "mcr p15, 0, %[mva], c8, c6, 1\n" |
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395 | ARM_SWITCH_BACK |
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396 | : ARM_SWITCH_OUTPUT |
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397 | : [mva] "r" (mva) |
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398 | ); |
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399 | } |
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400 | |
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401 | static inline void arm_cp15_tlb_lockdown_entry(const void *mva) |
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402 | { |
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403 | uint32_t arm_switch_reg; |
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404 | |
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405 | __asm__ volatile ( |
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406 | ARM_SWITCH_TO_ARM |
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407 | "add %[arm_switch_reg], pc, #16\n" |
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408 | "mcr p15, 0, %[arm_switch_reg], c7, c13, 1\n" |
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409 | "mcr p15, 0, %[mva], c8, c7, 1\n" |
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410 | "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
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411 | "orr %[arm_switch_reg], #0x1\n" |
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412 | "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
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413 | "ldr %[mva], [%[mva]]\n" |
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414 | "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
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415 | "bic %[arm_switch_reg], #0x1\n" |
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416 | "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
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417 | ARM_SWITCH_BACK |
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418 | : [mva] "=r" (mva), [arm_switch_reg] "=&r" (arm_switch_reg) |
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419 | : "[mva]" (mva) |
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420 | ); |
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421 | } |
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422 | |
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423 | /** @} */ |
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424 | |
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425 | /** |
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426 | * @name Cache Functions |
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427 | * |
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428 | * @{ |
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429 | */ |
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430 | |
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431 | static inline uint32_t arm_cp15_get_cache_type(void) |
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432 | { |
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433 | ARM_SWITCH_REGISTERS; |
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434 | uint32_t val; |
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435 | |
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436 | __asm__ volatile ( |
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437 | ARM_SWITCH_TO_ARM |
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438 | "mrc p15, 0, %[val], c0, c0, 1\n" |
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439 | ARM_SWITCH_BACK |
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440 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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441 | ); |
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442 | |
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443 | return val; |
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444 | } |
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445 | |
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446 | static inline void arm_cp15_cache_invalidate(void) |
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447 | { |
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448 | ARM_SWITCH_REGISTERS; |
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449 | uint32_t sbz = 0; |
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450 | |
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451 | __asm__ volatile ( |
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452 | ARM_SWITCH_TO_ARM |
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453 | "mcr p15, 0, %[sbz], c7, c7, 0\n" |
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454 | ARM_SWITCH_BACK |
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455 | : ARM_SWITCH_OUTPUT |
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456 | : [sbz] "r" (sbz) |
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457 | : "memory" |
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458 | ); |
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459 | } |
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460 | |
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461 | static inline void arm_cp15_instruction_cache_invalidate(void) |
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462 | { |
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463 | ARM_SWITCH_REGISTERS; |
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464 | uint32_t sbz = 0; |
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465 | |
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466 | __asm__ volatile ( |
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467 | ARM_SWITCH_TO_ARM |
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468 | "mcr p15, 0, %[sbz], c7, c5, 0\n" |
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469 | ARM_SWITCH_BACK |
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470 | : ARM_SWITCH_OUTPUT |
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471 | : [sbz] "r" (sbz) |
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472 | : "memory" |
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473 | ); |
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474 | } |
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475 | |
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476 | static inline void arm_cp15_instruction_cache_invalidate_line(const void *mva) |
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477 | { |
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478 | ARM_SWITCH_REGISTERS; |
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479 | |
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480 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
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481 | |
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482 | __asm__ volatile ( |
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483 | ARM_SWITCH_TO_ARM |
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484 | "mcr p15, 0, %[mva], c7, c5, 1\n" |
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485 | ARM_SWITCH_BACK |
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486 | : ARM_SWITCH_OUTPUT |
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487 | : [mva] "r" (mva) |
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488 | : "memory" |
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489 | ); |
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490 | } |
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491 | |
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492 | static inline void arm_cp15_instruction_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) |
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493 | { |
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494 | ARM_SWITCH_REGISTERS; |
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495 | |
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496 | __asm__ volatile ( |
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497 | ARM_SWITCH_TO_ARM |
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498 | "mcr p15, 0, %[set_and_way], c7, c5, 2\n" |
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499 | ARM_SWITCH_BACK |
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500 | : ARM_SWITCH_OUTPUT |
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501 | : [set_and_way] "r" (set_and_way) |
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502 | : "memory" |
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503 | ); |
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504 | } |
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505 | |
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506 | static inline void arm_cp15_instruction_cache_prefetch_line(const void *mva) |
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507 | { |
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508 | ARM_SWITCH_REGISTERS; |
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509 | |
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510 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
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511 | |
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512 | __asm__ volatile ( |
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513 | ARM_SWITCH_TO_ARM |
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514 | "mcr p15, 0, %[mva], c7, c13, 1\n" |
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515 | ARM_SWITCH_BACK |
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516 | : ARM_SWITCH_OUTPUT |
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517 | : [mva] "r" (mva) |
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518 | ); |
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519 | } |
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520 | |
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521 | static inline void arm_cp15_data_cache_invalidate(void) |
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522 | { |
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523 | ARM_SWITCH_REGISTERS; |
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524 | uint32_t sbz = 0; |
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525 | |
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526 | __asm__ volatile ( |
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527 | ARM_SWITCH_TO_ARM |
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528 | "mcr p15, 0, %[sbz], c7, c6, 0\n" |
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529 | ARM_SWITCH_BACK |
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530 | : ARM_SWITCH_OUTPUT |
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531 | : [sbz] "r" (sbz) |
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532 | : "memory" |
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533 | ); |
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534 | } |
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535 | |
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536 | static inline void arm_cp15_data_cache_invalidate_line(const void *mva) |
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537 | { |
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538 | ARM_SWITCH_REGISTERS; |
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539 | |
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540 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
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541 | |
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542 | __asm__ volatile ( |
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543 | ARM_SWITCH_TO_ARM |
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544 | "mcr p15, 0, %[mva], c7, c6, 1\n" |
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545 | ARM_SWITCH_BACK |
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546 | : ARM_SWITCH_OUTPUT |
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547 | : [mva] "r" (mva) |
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548 | : "memory" |
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549 | ); |
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550 | } |
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551 | |
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552 | static inline void arm_cp15_data_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) |
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553 | { |
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554 | ARM_SWITCH_REGISTERS; |
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555 | |
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556 | __asm__ volatile ( |
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557 | ARM_SWITCH_TO_ARM |
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558 | "mcr p15, 0, %[set_and_way], c7, c6, 2\n" |
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559 | ARM_SWITCH_BACK |
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560 | : ARM_SWITCH_OUTPUT |
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561 | : [set_and_way] "r" (set_and_way) |
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562 | : "memory" |
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563 | ); |
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564 | } |
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565 | |
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566 | static inline void arm_cp15_data_cache_clean_line(const void *mva) |
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567 | { |
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568 | ARM_SWITCH_REGISTERS; |
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569 | |
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570 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
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571 | |
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572 | __asm__ volatile ( |
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573 | ARM_SWITCH_TO_ARM |
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574 | "mcr p15, 0, %[mva], c7, c10, 1\n" |
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575 | ARM_SWITCH_BACK |
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576 | : ARM_SWITCH_OUTPUT |
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577 | : [mva] "r" (mva) |
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578 | : "memory" |
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579 | ); |
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580 | } |
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581 | |
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582 | static inline void arm_cp15_data_cache_clean_line_by_set_and_way(uint32_t set_and_way) |
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583 | { |
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584 | ARM_SWITCH_REGISTERS; |
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585 | |
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586 | __asm__ volatile ( |
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587 | ARM_SWITCH_TO_ARM |
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588 | "mcr p15, 0, %[set_and_way], c7, c10, 2\n" |
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589 | ARM_SWITCH_BACK |
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590 | : ARM_SWITCH_OUTPUT |
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591 | : [set_and_way] "r" (set_and_way) |
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592 | : "memory" |
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593 | ); |
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594 | } |
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595 | |
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596 | static inline void arm_cp15_data_cache_test_and_clean(void) |
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597 | { |
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598 | ARM_SWITCH_REGISTERS; |
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599 | |
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600 | __asm__ volatile ( |
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601 | ARM_SWITCH_TO_ARM |
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602 | "1:\n" |
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603 | "mrc p15, 0, r15, c7, c10, 3\n" |
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604 | "bne 1b\n" |
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605 | ARM_SWITCH_BACK |
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606 | : ARM_SWITCH_OUTPUT |
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607 | : |
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608 | : "memory" |
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609 | ); |
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610 | } |
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611 | |
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612 | /* In DDI0301H_arm1176jzfs_r0p7_trm |
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613 | * 'MCR p15, 0, <Rd>, c7, c14, 0' means |
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614 | * Clean and Invalidate Entire Data Cache |
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615 | */ |
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616 | static inline void arm_cp15_data_cache_clean_and_invalidate(void) |
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617 | { |
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618 | ARM_SWITCH_REGISTERS; |
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619 | |
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620 | uint32_t sbz = 0; |
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621 | |
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622 | __asm__ volatile ( |
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623 | ARM_SWITCH_TO_ARM |
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624 | "mcr p15, 0, %[sbz], c7, c14, 0\n" |
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625 | ARM_SWITCH_BACK |
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626 | : ARM_SWITCH_OUTPUT |
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627 | : [sbz] "r" (sbz) |
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628 | : "memory" |
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629 | ); |
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630 | |
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631 | } |
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632 | |
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633 | static inline void arm_cp15_data_cache_clean_and_invalidate_line(const void *mva) |
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634 | { |
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635 | ARM_SWITCH_REGISTERS; |
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636 | |
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637 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
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638 | |
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639 | __asm__ volatile ( |
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640 | ARM_SWITCH_TO_ARM |
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641 | "mcr p15, 0, %[mva], c7, c14, 1\n" |
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642 | ARM_SWITCH_BACK |
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643 | : ARM_SWITCH_OUTPUT |
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644 | : [mva] "r" (mva) |
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645 | : "memory" |
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646 | ); |
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647 | } |
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648 | |
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649 | static inline void arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(uint32_t set_and_way) |
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650 | { |
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651 | ARM_SWITCH_REGISTERS; |
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652 | |
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653 | __asm__ volatile ( |
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654 | ARM_SWITCH_TO_ARM |
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655 | "mcr p15, 0, %[set_and_way], c7, c14, 2\n" |
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656 | ARM_SWITCH_BACK |
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657 | : ARM_SWITCH_OUTPUT |
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658 | : [set_and_way] "r" (set_and_way) |
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659 | : "memory" |
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660 | ); |
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661 | } |
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662 | |
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663 | static inline void arm_cp15_data_cache_test_and_clean_and_invalidate(void) |
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664 | { |
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665 | ARM_SWITCH_REGISTERS; |
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666 | |
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667 | __asm__ volatile ( |
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668 | ARM_SWITCH_TO_ARM |
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669 | "1:\n" |
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670 | "mrc p15, 0, r15, c7, c14, 3\n" |
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671 | "bne 1b\n" |
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672 | ARM_SWITCH_BACK |
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673 | : ARM_SWITCH_OUTPUT |
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674 | : |
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675 | : "memory" |
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676 | ); |
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677 | } |
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678 | |
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679 | /** @} */ |
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680 | |
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681 | static inline void arm_cp15_drain_write_buffer(void) |
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682 | { |
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683 | ARM_SWITCH_REGISTERS; |
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684 | uint32_t sbz = 0; |
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685 | |
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686 | __asm__ volatile ( |
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687 | ARM_SWITCH_TO_ARM |
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688 | "mcr p15, 0, %[sbz], c7, c10, 4\n" |
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689 | ARM_SWITCH_BACK |
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690 | : ARM_SWITCH_OUTPUT |
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691 | : [sbz] "r" (sbz) |
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692 | : "memory" |
---|
693 | ); |
---|
694 | } |
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695 | |
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696 | static inline void arm_cp15_wait_for_interrupt(void) |
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697 | { |
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698 | ARM_SWITCH_REGISTERS; |
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699 | uint32_t sbz = 0; |
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700 | |
---|
701 | __asm__ volatile ( |
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702 | ARM_SWITCH_TO_ARM |
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703 | "mcr p15, 0, %[sbz], c7, c0, 4\n" |
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704 | ARM_SWITCH_BACK |
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705 | : ARM_SWITCH_OUTPUT |
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706 | : [sbz] "r" (sbz) |
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707 | : "memory" |
---|
708 | ); |
---|
709 | } |
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710 | |
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711 | /** @} */ |
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712 | |
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713 | #ifdef __cplusplus |
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714 | } |
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715 | #endif /* __cplusplus */ |
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716 | |
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717 | #endif /* LIBCPU_SHARED_ARM_CP15_H */ |
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