1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm |
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5 | * |
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6 | * @brief ARM co-processor 15 (CP15) API. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009 |
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11 | * embedded brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * <rtems@embedded-brains.de> |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.com/license/LICENSE. |
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20 | */ |
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21 | |
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22 | #ifndef LIBCPU_SHARED_ARM_CP15_H |
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23 | #define LIBCPU_SHARED_ARM_CP15_H |
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24 | |
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25 | #include <rtems.h> |
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26 | |
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27 | #ifdef __cplusplus |
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28 | extern "C" { |
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29 | #endif /* __cplusplus */ |
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30 | |
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31 | #define ARM_MMU_SECT_BASE_SHIFT 20 |
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32 | #define ARM_MMU_SECT_BASE_MASK 0xfffU |
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33 | #define ARM_MMU_SECT_DOMAIN_SHIFT 5 |
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34 | #define ARM_MMU_SECT_DOMAIN_MASK 0xfU |
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35 | #define ARM_MMU_SECT_AP_1 (1U << 11) |
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36 | #define ARM_MMU_SECT_AP_0 (1U << 10) |
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37 | #define ARM_MMU_SECT_AP_SHIFT 10 |
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38 | #define ARM_MMU_SECT_AP_MASK 0x3U |
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39 | #define ARM_MMU_SECT_C (1U << 3) |
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40 | #define ARM_MMU_SECT_B (1U << 2) |
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41 | #define ARM_MMU_SECT_DEFAULT 0x12U |
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42 | #define ARM_MMU_SECT_GET_INDEX(mva) \ |
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43 | (((uint32_t) (mva)) >> ARM_MMU_SECT_BASE_SHIFT) |
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44 | #define ARM_MMU_SECT_MVA_ALIGN_UP(mva) \ |
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45 | ((1U << ARM_MMU_SECT_BASE_SHIFT) \ |
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46 | + ((((uint32_t) (mva) - 1U)) & ~((1U << ARM_MMU_SECT_BASE_SHIFT) - 1U))) |
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47 | |
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48 | #define ARM_MMU_TRANSLATION_TABLE_ENTRY_SIZE 4U |
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49 | #define ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT 4096U |
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50 | |
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51 | static inline uint32_t arm_cp15_get_id_code(void) |
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52 | { |
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53 | ARM_SWITCH_REGISTERS; |
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54 | uint32_t val; |
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55 | |
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56 | asm volatile ( |
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57 | ARM_SWITCH_TO_ARM |
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58 | "mrc p15, 0, %[val], c0, c0, 0\n" |
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59 | ARM_SWITCH_BACK |
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60 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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61 | ); |
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62 | |
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63 | return val; |
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64 | } |
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65 | |
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66 | static inline uint32_t arm_cp15_get_cache_type(void) |
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67 | { |
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68 | ARM_SWITCH_REGISTERS; |
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69 | uint32_t val; |
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70 | |
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71 | asm volatile ( |
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72 | ARM_SWITCH_TO_ARM |
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73 | "mrc p15, 0, %[val], c0, c0, 1\n" |
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74 | ARM_SWITCH_BACK |
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75 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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76 | ); |
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77 | |
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78 | return val; |
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79 | } |
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80 | |
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81 | static inline uint32_t arm_cp15_get_tcm_status(void) |
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82 | { |
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83 | ARM_SWITCH_REGISTERS; |
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84 | uint32_t val; |
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85 | |
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86 | asm volatile ( |
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87 | ARM_SWITCH_TO_ARM |
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88 | "mrc p15, 0, %[val], c0, c0, 2\n" |
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89 | ARM_SWITCH_BACK |
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90 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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91 | ); |
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92 | |
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93 | return val; |
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94 | } |
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95 | |
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96 | #define ARM_CP15_CTRL_L4 (1U << 15) |
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97 | #define ARM_CP15_CTRL_RR (1U << 14) |
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98 | #define ARM_CP15_CTRL_V (1U << 13) |
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99 | #define ARM_CP15_CTRL_I (1U << 12) |
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100 | #define ARM_CP15_CTRL_R (1U << 9) |
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101 | #define ARM_CP15_CTRL_S (1U << 8) |
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102 | #define ARM_CP15_CTRL_B (1U << 7) |
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103 | #define ARM_CP15_CTRL_C (1U << 2) |
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104 | #define ARM_CP15_CTRL_A (1U << 1) |
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105 | #define ARM_CP15_CTRL_M (1U << 0) |
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106 | |
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107 | static inline uint32_t arm_cp15_get_control(void) |
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108 | { |
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109 | ARM_SWITCH_REGISTERS; |
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110 | uint32_t val; |
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111 | |
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112 | asm volatile ( |
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113 | ARM_SWITCH_TO_ARM |
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114 | "mrc p15, 0, %[val], c1, c0, 0\n" |
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115 | ARM_SWITCH_BACK |
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116 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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117 | ); |
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118 | |
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119 | return val; |
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120 | } |
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121 | |
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122 | static inline void arm_cp15_set_control(uint32_t val) |
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123 | { |
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124 | ARM_SWITCH_REGISTERS; |
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125 | |
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126 | asm volatile ( |
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127 | ARM_SWITCH_TO_ARM |
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128 | "mcr p15, 0, %[val], c1, c0, 0\n" |
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129 | "nop\n" |
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130 | "nop\n" |
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131 | ARM_SWITCH_BACK |
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132 | : ARM_SWITCH_OUTPUT |
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133 | : [val] "r" (val) |
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134 | : "memory" |
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135 | ); |
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136 | } |
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137 | |
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138 | static inline uint32_t *arm_cp15_get_translation_table_base(void) |
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139 | { |
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140 | ARM_SWITCH_REGISTERS; |
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141 | uint32_t *base; |
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142 | |
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143 | asm volatile ( |
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144 | ARM_SWITCH_TO_ARM |
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145 | "mrc p15, 0, %[base], c2, c0, 0\n" |
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146 | ARM_SWITCH_BACK |
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147 | : [base] "=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT |
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148 | ); |
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149 | |
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150 | return base; |
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151 | } |
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152 | |
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153 | static inline void arm_cp15_set_translation_table_base(uint32_t *base) |
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154 | { |
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155 | ARM_SWITCH_REGISTERS; |
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156 | |
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157 | asm volatile ( |
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158 | ARM_SWITCH_TO_ARM |
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159 | "mcr p15, 0, %[base], c2, c0, 0\n" |
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160 | ARM_SWITCH_BACK |
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161 | : ARM_SWITCH_OUTPUT |
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162 | : [base] "r" (base) |
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163 | ); |
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164 | } |
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165 | |
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166 | #define ARM_CP15_DAC_NO_ACCESS 0x0U |
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167 | #define ARM_CP15_DAC_CLIENT 0x1U |
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168 | #define ARM_CP15_DAC_MANAGER 0x3U |
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169 | #define ARM_CP15_DAC_DOMAIN(index, val) ((val) << (2 * index)) |
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170 | |
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171 | static inline uint32_t arm_cp15_get_domain_access_control(void) |
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172 | { |
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173 | ARM_SWITCH_REGISTERS; |
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174 | uint32_t val; |
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175 | |
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176 | asm volatile ( |
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177 | ARM_SWITCH_TO_ARM |
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178 | "mrc p15, 0, %[val], c3, c0, 0\n" |
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179 | ARM_SWITCH_BACK |
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180 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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181 | ); |
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182 | |
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183 | return val; |
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184 | } |
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185 | |
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186 | static inline void arm_cp15_set_domain_access_control(uint32_t val) |
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187 | { |
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188 | ARM_SWITCH_REGISTERS; |
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189 | |
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190 | asm volatile ( |
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191 | ARM_SWITCH_TO_ARM |
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192 | "mcr p15, 0, %[val], c3, c0, 0\n" |
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193 | ARM_SWITCH_BACK |
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194 | : ARM_SWITCH_OUTPUT |
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195 | : [val] "r" (val) |
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196 | ); |
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197 | } |
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198 | |
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199 | static inline uint32_t arm_cp15_get_data_fault_status(void) |
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200 | { |
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201 | ARM_SWITCH_REGISTERS; |
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202 | uint32_t val; |
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203 | |
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204 | asm volatile ( |
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205 | ARM_SWITCH_TO_ARM |
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206 | "mrc p15, 0, %[val], c5, c0, 0\n" |
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207 | ARM_SWITCH_BACK |
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208 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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209 | ); |
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210 | |
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211 | return val; |
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212 | } |
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213 | |
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214 | static inline void arm_cp15_set_data_fault_status(uint32_t val) |
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215 | { |
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216 | ARM_SWITCH_REGISTERS; |
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217 | |
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218 | asm volatile ( |
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219 | ARM_SWITCH_TO_ARM |
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220 | "mcr p15, 0, %[val], c5, c0, 0\n" |
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221 | ARM_SWITCH_BACK |
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222 | : ARM_SWITCH_OUTPUT |
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223 | : [val] "r" (val) |
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224 | ); |
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225 | } |
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226 | |
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227 | static inline uint32_t arm_cp15_get_instruction_fault_status(void) |
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228 | { |
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229 | ARM_SWITCH_REGISTERS; |
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230 | uint32_t val; |
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231 | |
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232 | asm volatile ( |
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233 | ARM_SWITCH_TO_ARM |
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234 | "mrc p15, 0, %[val], c5, c0, 1\n" |
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235 | ARM_SWITCH_BACK |
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236 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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237 | ); |
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238 | |
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239 | return val; |
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240 | } |
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241 | |
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242 | static inline void arm_cp15_set_instruction_fault_status(uint32_t val) |
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243 | { |
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244 | ARM_SWITCH_REGISTERS; |
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245 | |
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246 | asm volatile ( |
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247 | ARM_SWITCH_TO_ARM |
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248 | "mcr p15, 0, %[val], c5, c0, 1\n" |
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249 | ARM_SWITCH_BACK |
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250 | : ARM_SWITCH_OUTPUT |
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251 | : [val] "r" (val) |
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252 | ); |
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253 | } |
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254 | |
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255 | static inline void *arm_cp15_get_fault_address(void) |
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256 | { |
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257 | ARM_SWITCH_REGISTERS; |
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258 | void *mva; |
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259 | |
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260 | asm volatile ( |
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261 | ARM_SWITCH_TO_ARM |
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262 | "mrc p15, 0, %[mva], c6, c0, 0\n" |
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263 | ARM_SWITCH_BACK |
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264 | : [mva] "=&r" (mva) ARM_SWITCH_ADDITIONAL_OUTPUT |
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265 | ); |
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266 | |
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267 | return mva; |
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268 | } |
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269 | |
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270 | static inline void arm_cp15_set_fault_address(const void *mva) |
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271 | { |
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272 | ARM_SWITCH_REGISTERS; |
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273 | |
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274 | asm volatile ( |
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275 | ARM_SWITCH_TO_ARM |
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276 | "mcr p15, 0, %[mva], c6, c0, 0\n" |
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277 | ARM_SWITCH_BACK |
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278 | : ARM_SWITCH_OUTPUT |
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279 | : [mva] "r" (mva) |
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280 | ); |
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281 | } |
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282 | |
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283 | #define ARM_CP15_CACHE_PREPARE_MVA(mva) \ |
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284 | ((const void *) (((uint32_t) (mva)) & ~0x1fU)) |
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285 | |
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286 | static inline void arm_cp15_cache_invalidate(void) |
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287 | { |
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288 | ARM_SWITCH_REGISTERS; |
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289 | uint32_t sbz = 0; |
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290 | |
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291 | asm volatile ( |
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292 | ARM_SWITCH_TO_ARM |
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293 | "mcr p15, 0, %[sbz], c7, c7, 0\n" |
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294 | ARM_SWITCH_BACK |
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295 | : ARM_SWITCH_OUTPUT |
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296 | : [sbz] "r" (sbz) |
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297 | : "memory" |
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298 | ); |
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299 | } |
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300 | |
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301 | static inline void arm_cp15_instruction_cache_invalidate(void) |
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302 | { |
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303 | ARM_SWITCH_REGISTERS; |
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304 | uint32_t sbz = 0; |
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305 | |
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306 | asm volatile ( |
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307 | ARM_SWITCH_TO_ARM |
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308 | "mcr p15, 0, %[sbz], c7, c5, 0\n" |
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309 | ARM_SWITCH_BACK |
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310 | : ARM_SWITCH_OUTPUT |
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311 | : [sbz] "r" (sbz) |
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312 | : "memory" |
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313 | ); |
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314 | } |
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315 | |
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316 | static inline void arm_cp15_instruction_cache_invalidate_line(const void *mva) |
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317 | { |
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318 | ARM_SWITCH_REGISTERS; |
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319 | |
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320 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
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321 | |
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322 | asm volatile ( |
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323 | ARM_SWITCH_TO_ARM |
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324 | "mcr p15, 0, %[mva], c7, c5, 1\n" |
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325 | ARM_SWITCH_BACK |
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326 | : ARM_SWITCH_OUTPUT |
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327 | : [mva] "r" (mva) |
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328 | : "memory" |
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329 | ); |
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330 | } |
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331 | |
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332 | static inline void arm_cp15_instruction_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) |
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333 | { |
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334 | ARM_SWITCH_REGISTERS; |
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335 | |
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336 | asm volatile ( |
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337 | ARM_SWITCH_TO_ARM |
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338 | "mcr p15, 0, %[set_and_way], c7, c5, 2\n" |
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339 | ARM_SWITCH_BACK |
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340 | : ARM_SWITCH_OUTPUT |
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341 | : [set_and_way] "r" (set_and_way) |
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342 | : "memory" |
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343 | ); |
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344 | } |
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345 | |
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346 | static inline void arm_cp15_instruction_cache_prefetch_line(const void *mva) |
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347 | { |
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348 | ARM_SWITCH_REGISTERS; |
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349 | |
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350 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
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351 | |
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352 | asm volatile ( |
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353 | ARM_SWITCH_TO_ARM |
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354 | "mcr p15, 0, %[mva], c7, c13, 1\n" |
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355 | ARM_SWITCH_BACK |
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356 | : ARM_SWITCH_OUTPUT |
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357 | : [mva] "r" (mva) |
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358 | ); |
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359 | } |
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360 | |
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361 | static inline void arm_cp15_data_cache_invalidate(void) |
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362 | { |
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363 | ARM_SWITCH_REGISTERS; |
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364 | uint32_t sbz = 0; |
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365 | |
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366 | asm volatile ( |
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367 | ARM_SWITCH_TO_ARM |
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368 | "mcr p15, 0, %[sbz], c7, c6, 0\n" |
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369 | ARM_SWITCH_BACK |
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370 | : ARM_SWITCH_OUTPUT |
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371 | : [sbz] "r" (sbz) |
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372 | : "memory" |
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373 | ); |
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374 | } |
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375 | |
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376 | static inline void arm_cp15_data_cache_invalidate_line(const void *mva) |
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377 | { |
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378 | ARM_SWITCH_REGISTERS; |
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379 | |
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380 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
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381 | |
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382 | asm volatile ( |
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383 | ARM_SWITCH_TO_ARM |
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384 | "mcr p15, 0, %[mva], c7, c6, 1\n" |
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385 | ARM_SWITCH_BACK |
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386 | : ARM_SWITCH_OUTPUT |
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387 | : [mva] "r" (mva) |
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388 | : "memory" |
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389 | ); |
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390 | } |
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391 | |
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392 | static inline void arm_cp15_data_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) |
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393 | { |
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394 | ARM_SWITCH_REGISTERS; |
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395 | |
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396 | asm volatile ( |
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397 | ARM_SWITCH_TO_ARM |
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398 | "mcr p15, 0, %[set_and_way], c7, c6, 2\n" |
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399 | ARM_SWITCH_BACK |
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400 | : ARM_SWITCH_OUTPUT |
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401 | : [set_and_way] "r" (set_and_way) |
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402 | : "memory" |
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403 | ); |
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404 | } |
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405 | |
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406 | static inline void arm_cp15_data_cache_clean_line(const void *mva) |
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407 | { |
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408 | ARM_SWITCH_REGISTERS; |
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409 | |
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410 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
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411 | |
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412 | asm volatile ( |
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413 | ARM_SWITCH_TO_ARM |
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414 | "mcr p15, 0, %[mva], c7, c10, 1\n" |
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415 | ARM_SWITCH_BACK |
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416 | : ARM_SWITCH_OUTPUT |
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417 | : [mva] "r" (mva) |
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418 | : "memory" |
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419 | ); |
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420 | } |
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421 | |
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422 | static inline void arm_cp15_data_cache_clean_line_by_set_and_way(uint32_t set_and_way) |
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423 | { |
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424 | ARM_SWITCH_REGISTERS; |
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425 | |
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426 | asm volatile ( |
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427 | ARM_SWITCH_TO_ARM |
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428 | "mcr p15, 0, %[set_and_way], c7, c10, 2\n" |
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429 | ARM_SWITCH_BACK |
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430 | : ARM_SWITCH_OUTPUT |
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431 | : [set_and_way] "r" (set_and_way) |
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432 | : "memory" |
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433 | ); |
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434 | } |
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435 | |
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436 | static inline void arm_cp15_data_cache_test_and_clean(void) |
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437 | { |
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438 | ARM_SWITCH_REGISTERS; |
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439 | |
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440 | asm volatile ( |
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441 | ARM_SWITCH_TO_ARM |
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442 | "1:\n" |
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443 | "mrc p15, 0, r15, c7, c10, 3\n" |
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444 | "bne 1b\n" |
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445 | ARM_SWITCH_BACK |
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446 | : ARM_SWITCH_OUTPUT |
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447 | : |
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448 | : "memory" |
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449 | ); |
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450 | } |
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451 | |
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452 | static inline void arm_cp15_data_cache_clean_and_invalidate_line(const void *mva) |
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453 | { |
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454 | ARM_SWITCH_REGISTERS; |
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455 | |
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456 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
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457 | |
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458 | asm volatile ( |
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459 | ARM_SWITCH_TO_ARM |
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460 | "mcr p15, 0, %[mva], c7, c14, 1\n" |
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461 | ARM_SWITCH_BACK |
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462 | : ARM_SWITCH_OUTPUT |
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463 | : [mva] "r" (mva) |
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464 | : "memory" |
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465 | ); |
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466 | } |
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467 | |
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468 | static inline void arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(uint32_t set_and_way) |
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469 | { |
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470 | ARM_SWITCH_REGISTERS; |
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471 | |
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472 | asm volatile ( |
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473 | ARM_SWITCH_TO_ARM |
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474 | "mcr p15, 0, %[set_and_way], c7, c14, 2\n" |
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475 | ARM_SWITCH_BACK |
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476 | : ARM_SWITCH_OUTPUT |
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477 | : [set_and_way] "r" (set_and_way) |
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478 | : "memory" |
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479 | ); |
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480 | } |
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481 | |
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482 | static inline void arm_cp15_data_cache_test_and_clean_and_invalidate(void) |
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483 | { |
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484 | ARM_SWITCH_REGISTERS; |
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485 | |
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486 | asm volatile ( |
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487 | ARM_SWITCH_TO_ARM |
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488 | "1:\n" |
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489 | "mrc p15, 0, r15, c7, c14, 3\n" |
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490 | "bne 1b\n" |
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491 | ARM_SWITCH_BACK |
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492 | : ARM_SWITCH_OUTPUT |
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493 | : |
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494 | : "memory" |
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495 | ); |
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496 | } |
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497 | |
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498 | static inline void arm_cp15_drain_write_buffer(void) |
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499 | { |
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500 | ARM_SWITCH_REGISTERS; |
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501 | uint32_t sbz = 0; |
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502 | |
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503 | asm volatile ( |
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504 | ARM_SWITCH_TO_ARM |
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505 | "mcr p15, 0, %[sbz], c7, c10, 4\n" |
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506 | ARM_SWITCH_BACK |
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507 | : ARM_SWITCH_OUTPUT |
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508 | : [sbz] "r" (sbz) |
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509 | : "memory" |
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510 | ); |
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511 | } |
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512 | |
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513 | static inline void arm_cp15_wait_for_interrupt(void) |
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514 | { |
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515 | ARM_SWITCH_REGISTERS; |
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516 | uint32_t sbz = 0; |
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517 | |
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518 | asm volatile ( |
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519 | ARM_SWITCH_TO_ARM |
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520 | "mcr p15, 0, %[sbz], c7, c0, 4\n" |
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521 | ARM_SWITCH_BACK |
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522 | : ARM_SWITCH_OUTPUT |
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523 | : [sbz] "r" (sbz) |
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524 | : "memory" |
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525 | ); |
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526 | } |
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527 | |
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528 | #define ARM_CP15_TLB_PREPARE_MVA(mva) \ |
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529 | ((const void *) (((uint32_t) (mva)) & ~0x3fU)) |
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530 | |
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531 | static inline void arm_cp15_tlb_invalidate(void) |
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532 | { |
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533 | ARM_SWITCH_REGISTERS; |
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534 | uint32_t sbz = 0; |
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535 | |
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536 | asm volatile ( |
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537 | ARM_SWITCH_TO_ARM |
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538 | "mcr p15, 0, %[sbz], c8, c7, 0\n" |
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539 | ARM_SWITCH_BACK |
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540 | : ARM_SWITCH_OUTPUT |
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541 | : [sbz] "r" (sbz) |
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542 | ); |
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543 | } |
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544 | |
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545 | static inline void arm_cp15_tlb_invalidate_entry(const void *mva) |
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546 | { |
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547 | ARM_SWITCH_REGISTERS; |
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548 | |
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549 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
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550 | |
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551 | asm volatile ( |
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552 | ARM_SWITCH_TO_ARM |
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553 | "mcr p15, 0, %[mva], c8, c7, 1\n" |
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554 | ARM_SWITCH_BACK |
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555 | : ARM_SWITCH_OUTPUT |
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556 | : [mva] "r" (mva) |
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557 | ); |
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558 | } |
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559 | |
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560 | static inline void arm_cp15_tlb_instruction_invalidate(void) |
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561 | { |
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562 | ARM_SWITCH_REGISTERS; |
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563 | uint32_t sbz = 0; |
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564 | |
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565 | asm volatile ( |
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566 | ARM_SWITCH_TO_ARM |
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567 | "mcr p15, 0, %[sbz], c8, c5, 0\n" |
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568 | ARM_SWITCH_BACK |
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569 | : ARM_SWITCH_OUTPUT |
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570 | : [sbz] "r" (sbz) |
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571 | ); |
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572 | } |
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573 | |
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574 | static inline void arm_cp15_tlb_instruction_invalidate_entry(const void *mva) |
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575 | { |
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576 | ARM_SWITCH_REGISTERS; |
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577 | |
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578 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
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579 | |
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580 | asm volatile ( |
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581 | ARM_SWITCH_TO_ARM |
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582 | "mcr p15, 0, %[mva], c8, c5, 1\n" |
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583 | ARM_SWITCH_BACK |
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584 | : ARM_SWITCH_OUTPUT |
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585 | : [mva] "r" (mva) |
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586 | ); |
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587 | } |
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588 | |
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589 | static inline void arm_cp15_tlb_data_invalidate(void) |
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590 | { |
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591 | ARM_SWITCH_REGISTERS; |
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592 | uint32_t sbz = 0; |
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593 | |
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594 | asm volatile ( |
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595 | ARM_SWITCH_TO_ARM |
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596 | "mcr p15, 0, %[sbz], c8, c6, 0\n" |
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597 | ARM_SWITCH_BACK |
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598 | : ARM_SWITCH_OUTPUT |
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599 | : [sbz] "r" (sbz) |
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600 | ); |
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601 | } |
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602 | |
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603 | static inline void arm_cp15_tlb_data_invalidate_entry(const void *mva) |
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604 | { |
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605 | ARM_SWITCH_REGISTERS; |
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606 | |
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607 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
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608 | |
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609 | asm volatile ( |
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610 | ARM_SWITCH_TO_ARM |
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611 | "mcr p15, 0, %[mva], c8, c6, 1\n" |
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612 | ARM_SWITCH_BACK |
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613 | : ARM_SWITCH_OUTPUT |
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614 | : [mva] "r" (mva) |
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615 | ); |
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616 | } |
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617 | |
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618 | static inline void arm_cp15_tlb_lockdown_entry(const void *mva) |
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619 | { |
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620 | uint32_t arm_switch_reg; |
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621 | |
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622 | asm volatile ( |
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623 | ARM_SWITCH_TO_ARM |
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624 | "add %[arm_switch_reg], pc, #16\n" |
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625 | "mcr p15, 0, %[arm_switch_reg], c7, c13, 1\n" |
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626 | "mcr p15, 0, %[mva], c8, c7, 1\n" |
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627 | "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
628 | "orr %[arm_switch_reg], #0x1\n" |
---|
629 | "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
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630 | "ldr %[mva], [%[mva]]\n" |
---|
631 | "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
632 | "bic %[arm_switch_reg], #0x1\n" |
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633 | "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
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634 | ARM_SWITCH_BACK |
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635 | : [mva] "=r" (mva), [arm_switch_reg] "=&r" (arm_switch_reg) |
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636 | : "[mva]" (mva) |
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637 | ); |
---|
638 | } |
---|
639 | |
---|
640 | #ifdef __cplusplus |
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641 | } |
---|
642 | #endif /* __cplusplus */ |
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643 | |
---|
644 | #endif /* LIBCPU_SHARED_ARM_CP15_H */ |
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