1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup ScoreCPUARMCP15 |
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5 | * |
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6 | * @brief ARM co-processor 15 (CP15) API. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2013 Hesham AL-Matary |
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11 | * Copyright (c) 2009-2013 embedded brains GmbH. All rights reserved. |
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12 | * |
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13 | * embedded brains GmbH |
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14 | * Dornierstr. 4 |
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15 | * 82178 Puchheim |
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16 | * Germany |
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17 | * <info@embedded-brains.de> |
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18 | * |
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19 | * The license and distribution terms for this file may be |
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20 | * found in the file LICENSE in this distribution or at |
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21 | * http://www.rtems.com/license/LICENSE. |
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22 | */ |
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23 | |
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24 | #ifndef LIBCPU_SHARED_ARM_CP15_H |
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25 | #define LIBCPU_SHARED_ARM_CP15_H |
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26 | |
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27 | #include <rtems.h> |
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28 | |
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29 | #ifdef __cplusplus |
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30 | extern "C" { |
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31 | #endif /* __cplusplus */ |
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32 | |
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33 | #define ARM_CP15_CACHE_PREPARE_MVA(mva) \ |
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34 | ((const void *) (((uint32_t) (mva)) & ~0x1fU)) |
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35 | |
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36 | #define ARM_CP15_TLB_PREPARE_MVA(mva) \ |
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37 | ((const void *) (((uint32_t) (mva)) & ~0x3fU)) |
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38 | |
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39 | /** |
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40 | * @defgroup ScoreCPUARMCP15 ARM Co-Processor 15 Support |
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41 | * |
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42 | * @ingroup ScoreCPUARM |
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43 | * |
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44 | * @brief ARM co-processor 15 (CP15) support. |
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45 | * |
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46 | * @{ |
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47 | */ |
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48 | |
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49 | /** |
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50 | * @name MMU Defines |
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51 | * |
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52 | * @{ |
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53 | */ |
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54 | |
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55 | #define ARM_MMU_SECT_BASE_SHIFT 20 |
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56 | #define ARM_MMU_SECT_BASE_MASK (0xfffU << ARM_MMU_SECT_BASE_SHIFT) |
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57 | #define ARM_MMU_SECT_NS (1U << 19) |
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58 | #define ARM_MMU_SECT_NG (1U << 17) |
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59 | #define ARM_MMU_SECT_S (1U << 16) |
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60 | #define ARM_MMU_SECT_AP_2 (1U << 15) |
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61 | #define ARM_MMU_SECT_TEX_2 (1U << 14) |
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62 | #define ARM_MMU_SECT_TEX_1 (1U << 13) |
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63 | #define ARM_MMU_SECT_TEX_0 (1U << 12) |
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64 | #define ARM_MMU_SECT_TEX_SHIFT 12 |
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65 | #define ARM_MMU_SECT_TEX_MASK (0x3U << ARM_MMU_SECT_TEX_SHIFT) |
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66 | #define ARM_MMU_SECT_AP_1 (1U << 11) |
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67 | #define ARM_MMU_SECT_AP_0 (1U << 10) |
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68 | #define ARM_MMU_SECT_AP_SHIFT 10 |
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69 | #define ARM_MMU_SECT_AP_MASK (0x23U << ARM_MMU_SECT_AP_SHIFT) |
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70 | #define ARM_MMU_SECT_DOMAIN_SHIFT 5 |
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71 | #define ARM_MMU_SECT_DOMAIN_MASK (0xfU << ARM_MMU_SECT_DOMAIN_SHIFT) |
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72 | #define ARM_MMU_SECT_XN (1U << 4) |
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73 | #define ARM_MMU_SECT_C (1U << 3) |
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74 | #define ARM_MMU_SECT_B (1U << 2) |
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75 | #define ARM_MMU_SECT_PXN (1U << 0) |
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76 | #define ARM_MMU_SECT_DEFAULT 0x2U |
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77 | #define ARM_MMU_SECT_GET_INDEX(mva) \ |
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78 | (((uint32_t) (mva)) >> ARM_MMU_SECT_BASE_SHIFT) |
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79 | #define ARM_MMU_SECT_MVA_ALIGN_UP(mva) \ |
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80 | ((1U << ARM_MMU_SECT_BASE_SHIFT) \ |
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81 | + ((((uint32_t) (mva) - 1U)) & ~((1U << ARM_MMU_SECT_BASE_SHIFT) - 1U))) |
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82 | |
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83 | #define ARM_MMU_TRANSLATION_TABLE_ENTRY_SIZE 4U |
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84 | #define ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT 4096U |
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85 | |
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86 | #define ARM_MMU_DEFAULT_CLIENT_DOMAIN 15U |
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87 | |
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88 | #define ARMV7_MMU_READ_ONLY \ |
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89 | ((ARM_MMU_DEFAULT_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ |
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90 | | ARM_MMU_SECT_AP_0 \ |
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91 | | ARM_MMU_SECT_AP_2 \ |
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92 | | ARM_MMU_SECT_DEFAULT) |
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93 | |
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94 | #define ARMV7_MMU_READ_ONLY_CACHED \ |
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95 | (ARMV7_MMU_READ_ONLY | ARM_MMU_SECT_TEX_0 | ARM_MMU_SECT_C | ARM_MMU_SECT_B) |
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96 | |
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97 | #define ARMV7_MMU_READ_WRITE \ |
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98 | ((ARM_MMU_DEFAULT_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ |
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99 | | ARM_MMU_SECT_AP_0 \ |
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100 | | ARM_MMU_SECT_DEFAULT) |
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101 | |
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102 | #define ARMV7_MMU_READ_WRITE_CACHED \ |
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103 | (ARMV7_MMU_READ_WRITE | ARM_MMU_SECT_TEX_0 | ARM_MMU_SECT_C | ARM_MMU_SECT_B) |
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104 | |
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105 | #define ARMV7_MMU_DATA_READ_ONLY \ |
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106 | ARMV7_MMU_READ_ONLY |
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107 | |
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108 | #define ARMV7_MMU_DATA_READ_ONLY_CACHED \ |
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109 | ARMV7_MMU_READ_ONLY_CACHED |
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110 | |
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111 | #define ARMV7_MMU_DATA_READ_WRITE \ |
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112 | ARMV7_MMU_READ_WRITE |
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113 | |
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114 | #define ARMV7_MMU_DATA_READ_WRITE_CACHED \ |
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115 | ARMV7_MMU_READ_WRITE_CACHED |
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116 | |
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117 | #define ARMV7_MMU_DATA_READ_WRITE_SHAREABLE \ |
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118 | (ARMV7_MMU_READ_WRITE_CACHED | ARM_MMU_SECT_S) |
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119 | |
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120 | #define ARMV7_MMU_CODE \ |
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121 | ARMV7_MMU_READ_ONLY |
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122 | |
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123 | #define ARMV7_MMU_CODE_CACHED \ |
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124 | ARMV7_MMU_READ_ONLY_CACHED |
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125 | |
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126 | #define ARMV7_MMU_DEVICE \ |
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127 | (ARMV7_MMU_READ_WRITE | ARM_MMU_SECT_B) |
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128 | |
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129 | /** @} */ |
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130 | |
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131 | /** |
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132 | * @name Control Register Defines |
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133 | * |
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134 | * @{ |
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135 | */ |
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136 | |
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137 | #define ARM_CP15_CTRL_TE (1U << 30) |
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138 | #define ARM_CP15_CTRL_AFE (1U << 29) |
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139 | #define ARM_CP15_CTRL_TRE (1U << 28) |
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140 | #define ARM_CP15_CTRL_NMFI (1U << 27) |
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141 | #define ARM_CP15_CTRL_EE (1U << 25) |
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142 | #define ARM_CP15_CTRL_VE (1U << 24) |
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143 | #define ARM_CP15_CTRL_XP (1U << 23) |
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144 | #define ARM_CP15_CTRL_U (1U << 22) |
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145 | #define ARM_CP15_CTRL_FI (1U << 21) |
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146 | #define ARM_CP15_CTRL_UWXN (1U << 20) |
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147 | #define ARM_CP15_CTRL_WXN (1U << 19) |
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148 | #define ARM_CP15_CTRL_HA (1U << 17) |
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149 | #define ARM_CP15_CTRL_L4 (1U << 15) |
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150 | #define ARM_CP15_CTRL_RR (1U << 14) |
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151 | #define ARM_CP15_CTRL_V (1U << 13) |
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152 | #define ARM_CP15_CTRL_I (1U << 12) |
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153 | #define ARM_CP15_CTRL_Z (1U << 11) |
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154 | #define ARM_CP15_CTRL_SW (1U << 10) |
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155 | #define ARM_CP15_CTRL_R (1U << 9) |
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156 | #define ARM_CP15_CTRL_S (1U << 8) |
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157 | #define ARM_CP15_CTRL_B (1U << 7) |
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158 | #define ARM_CP15_CTRL_CP15BEN (1U << 5) |
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159 | #define ARM_CP15_CTRL_C (1U << 2) |
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160 | #define ARM_CP15_CTRL_A (1U << 1) |
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161 | #define ARM_CP15_CTRL_M (1U << 0) |
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162 | |
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163 | /** @} */ |
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164 | |
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165 | /** |
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166 | * @name Domain Access Control Defines |
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167 | * |
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168 | * @{ |
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169 | */ |
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170 | |
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171 | #define ARM_CP15_DAC_NO_ACCESS 0x0U |
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172 | #define ARM_CP15_DAC_CLIENT 0x1U |
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173 | #define ARM_CP15_DAC_MANAGER 0x3U |
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174 | #define ARM_CP15_DAC_DOMAIN(index, val) ((val) << (2 * index)) |
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175 | |
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176 | /** @} */ |
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177 | |
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178 | /** |
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179 | * @name Fault Status Register Defines |
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180 | * |
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181 | * @{ |
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182 | */ |
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183 | |
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184 | #define ARM_CP15_FAULT_STATUS_MASK 0x040F |
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185 | |
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186 | #define ARM_CP15_FSR_ALIGNMENT_FAULT 0x00000001 |
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187 | #define ARM_CP15_FSR_BACKGROUND_FAULT 0x0000 |
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188 | #define ARM_CP15_FSR_ACCESS_PERMISSION_FAULT 0x000D |
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189 | #define ARM_CP15_FSR_PRECISE_EXTERNAL_ABORT_FAULT 0x0008 |
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190 | #define ARM_CP15_FSR_IMPRECISE_EXTERNAL_ABORT_FAULT 0x0406 |
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191 | #define ARM_CP15_FSR_PRECISE_PARITY_ERROR_EXCEPTION 0x0006 |
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192 | #define ARM_CP15_FSR_IMPRECISE_PARITY_ERROR_EXCEPTION 0x0408 |
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193 | #define ARM_CP15_FSR_DEBUG_EVENT 0x0002 |
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194 | |
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195 | /** @} */ |
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196 | |
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197 | static inline uint32_t arm_cp15_get_id_code(void) |
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198 | { |
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199 | ARM_SWITCH_REGISTERS; |
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200 | uint32_t val; |
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201 | |
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202 | __asm__ volatile ( |
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203 | ARM_SWITCH_TO_ARM |
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204 | "mrc p15, 0, %[val], c0, c0, 0\n" |
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205 | ARM_SWITCH_BACK |
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206 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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207 | ); |
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208 | |
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209 | return val; |
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210 | } |
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211 | |
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212 | static inline uint32_t arm_cp15_get_tcm_status(void) |
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213 | { |
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214 | ARM_SWITCH_REGISTERS; |
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215 | uint32_t val; |
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216 | |
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217 | __asm__ volatile ( |
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218 | ARM_SWITCH_TO_ARM |
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219 | "mrc p15, 0, %[val], c0, c0, 2\n" |
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220 | ARM_SWITCH_BACK |
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221 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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222 | ); |
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223 | |
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224 | return val; |
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225 | } |
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226 | |
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227 | static inline uint32_t arm_cp15_get_control(void) |
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228 | { |
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229 | ARM_SWITCH_REGISTERS; |
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230 | uint32_t val; |
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231 | |
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232 | __asm__ volatile ( |
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233 | ARM_SWITCH_TO_ARM |
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234 | "mrc p15, 0, %[val], c1, c0, 0\n" |
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235 | ARM_SWITCH_BACK |
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236 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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237 | ); |
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238 | |
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239 | return val; |
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240 | } |
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241 | |
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242 | static inline void arm_cp15_set_control(uint32_t val) |
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243 | { |
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244 | ARM_SWITCH_REGISTERS; |
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245 | |
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246 | __asm__ volatile ( |
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247 | ARM_SWITCH_TO_ARM |
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248 | "mcr p15, 0, %[val], c1, c0, 0\n" |
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249 | "nop\n" |
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250 | "nop\n" |
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251 | ARM_SWITCH_BACK |
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252 | : ARM_SWITCH_OUTPUT |
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253 | : [val] "r" (val) |
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254 | : "memory" |
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255 | ); |
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256 | } |
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257 | |
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258 | /** |
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259 | * @name MMU Functions |
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260 | * |
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261 | * @{ |
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262 | */ |
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263 | |
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264 | /** |
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265 | * @brief Disable the MMU. |
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266 | * |
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267 | * This function will clean and invalidate eight cache lines before and after |
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268 | * the current stack pointer. |
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269 | * |
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270 | * @param[in] cls The data cache line size. |
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271 | * |
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272 | * @return The current control register value. |
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273 | */ |
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274 | static inline uint32_t arm_cp15_mmu_disable(uint32_t cls) |
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275 | { |
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276 | ARM_SWITCH_REGISTERS; |
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277 | uint32_t ctrl; |
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278 | uint32_t tmp_0; |
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279 | uint32_t tmp_1; |
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280 | |
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281 | __asm__ volatile ( |
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282 | ARM_SWITCH_TO_ARM |
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283 | "mrc p15, 0, %[ctrl], c1, c0, 0\n" |
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284 | "bic %[tmp_0], %[ctrl], #1\n" |
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285 | "mcr p15, 0, %[tmp_0], c1, c0, 0\n" |
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286 | "nop\n" |
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287 | "nop\n" |
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288 | "mov %[tmp_1], sp\n" |
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289 | "rsb %[tmp_0], %[cls], #0\n" |
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290 | "and %[tmp_0], %[tmp_0], %[tmp_1]\n" |
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291 | "sub %[tmp_0], %[tmp_0], %[cls], asl #3\n" |
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292 | "add %[tmp_1], %[tmp_0], %[cls], asl #4\n" |
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293 | "1:\n" |
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294 | "mcr p15, 0, %[tmp_0], c7, c14, 1\n" |
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295 | "add %[tmp_0], %[tmp_0], %[cls]\n" |
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296 | "cmp %[tmp_1], %[tmp_0]\n" |
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297 | "bne 1b\n" |
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298 | ARM_SWITCH_BACK |
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299 | : [ctrl] "=&r" (ctrl), |
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300 | [tmp_0] "=&r" (tmp_0), |
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301 | [tmp_1] "=&r" (tmp_1) |
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302 | ARM_SWITCH_ADDITIONAL_OUTPUT |
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303 | : [cls] "r" (cls) |
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304 | : "memory", "cc" |
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305 | ); |
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306 | |
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307 | return ctrl; |
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308 | } |
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309 | |
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310 | static inline uint32_t *arm_cp15_get_translation_table_base(void) |
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311 | { |
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312 | ARM_SWITCH_REGISTERS; |
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313 | uint32_t *base; |
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314 | |
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315 | __asm__ volatile ( |
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316 | ARM_SWITCH_TO_ARM |
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317 | "mrc p15, 0, %[base], c2, c0, 0\n" |
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318 | ARM_SWITCH_BACK |
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319 | : [base] "=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT |
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320 | ); |
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321 | |
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322 | return base; |
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323 | } |
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324 | |
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325 | static inline void arm_cp15_set_translation_table_base(uint32_t *base) |
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326 | { |
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327 | ARM_SWITCH_REGISTERS; |
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328 | |
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329 | __asm__ volatile ( |
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330 | ARM_SWITCH_TO_ARM |
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331 | "mcr p15, 0, %[base], c2, c0, 0\n" |
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332 | ARM_SWITCH_BACK |
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333 | : ARM_SWITCH_OUTPUT |
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334 | : [base] "r" (base) |
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335 | ); |
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336 | } |
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337 | |
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338 | static inline uint32_t arm_cp15_get_domain_access_control(void) |
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339 | { |
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340 | ARM_SWITCH_REGISTERS; |
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341 | uint32_t val; |
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342 | |
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343 | __asm__ volatile ( |
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344 | ARM_SWITCH_TO_ARM |
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345 | "mrc p15, 0, %[val], c3, c0, 0\n" |
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346 | ARM_SWITCH_BACK |
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347 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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348 | ); |
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349 | |
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350 | return val; |
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351 | } |
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352 | |
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353 | static inline void arm_cp15_set_domain_access_control(uint32_t val) |
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354 | { |
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355 | ARM_SWITCH_REGISTERS; |
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356 | |
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357 | __asm__ volatile ( |
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358 | ARM_SWITCH_TO_ARM |
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359 | "mcr p15, 0, %[val], c3, c0, 0\n" |
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360 | ARM_SWITCH_BACK |
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361 | : ARM_SWITCH_OUTPUT |
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362 | : [val] "r" (val) |
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363 | ); |
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364 | } |
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365 | |
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366 | static inline uint32_t arm_cp15_get_data_fault_status(void) |
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367 | { |
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368 | ARM_SWITCH_REGISTERS; |
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369 | uint32_t val; |
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370 | |
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371 | __asm__ volatile ( |
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372 | ARM_SWITCH_TO_ARM |
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373 | "mrc p15, 0, %[val], c5, c0, 0\n" |
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374 | ARM_SWITCH_BACK |
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375 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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376 | ); |
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377 | |
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378 | return val; |
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379 | } |
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380 | |
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381 | static inline void arm_cp15_set_data_fault_status(uint32_t val) |
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382 | { |
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383 | ARM_SWITCH_REGISTERS; |
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384 | |
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385 | __asm__ volatile ( |
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386 | ARM_SWITCH_TO_ARM |
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387 | "mcr p15, 0, %[val], c5, c0, 0\n" |
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388 | ARM_SWITCH_BACK |
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389 | : ARM_SWITCH_OUTPUT |
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390 | : [val] "r" (val) |
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391 | ); |
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392 | } |
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393 | |
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394 | static inline uint32_t arm_cp15_get_instruction_fault_status(void) |
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395 | { |
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396 | ARM_SWITCH_REGISTERS; |
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397 | uint32_t val; |
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398 | |
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399 | __asm__ volatile ( |
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400 | ARM_SWITCH_TO_ARM |
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401 | "mrc p15, 0, %[val], c5, c0, 1\n" |
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402 | ARM_SWITCH_BACK |
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403 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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404 | ); |
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405 | |
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406 | return val; |
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407 | } |
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408 | |
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409 | static inline void arm_cp15_set_instruction_fault_status(uint32_t val) |
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410 | { |
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411 | ARM_SWITCH_REGISTERS; |
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412 | |
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413 | __asm__ volatile ( |
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414 | ARM_SWITCH_TO_ARM |
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415 | "mcr p15, 0, %[val], c5, c0, 1\n" |
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416 | ARM_SWITCH_BACK |
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417 | : ARM_SWITCH_OUTPUT |
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418 | : [val] "r" (val) |
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419 | ); |
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420 | } |
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421 | |
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422 | static inline void *arm_cp15_get_fault_address(void) |
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423 | { |
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424 | ARM_SWITCH_REGISTERS; |
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425 | void *mva; |
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426 | |
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427 | __asm__ volatile ( |
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428 | ARM_SWITCH_TO_ARM |
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429 | "mrc p15, 0, %[mva], c6, c0, 0\n" |
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430 | ARM_SWITCH_BACK |
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431 | : [mva] "=&r" (mva) ARM_SWITCH_ADDITIONAL_OUTPUT |
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432 | ); |
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433 | |
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434 | return mva; |
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435 | } |
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436 | |
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437 | static inline void arm_cp15_set_fault_address(const void *mva) |
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438 | { |
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439 | ARM_SWITCH_REGISTERS; |
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440 | |
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441 | __asm__ volatile ( |
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442 | ARM_SWITCH_TO_ARM |
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443 | "mcr p15, 0, %[mva], c6, c0, 0\n" |
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444 | ARM_SWITCH_BACK |
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445 | : ARM_SWITCH_OUTPUT |
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446 | : [mva] "r" (mva) |
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447 | ); |
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448 | } |
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449 | |
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450 | static inline void arm_cp15_tlb_invalidate(void) |
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451 | { |
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452 | ARM_SWITCH_REGISTERS; |
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453 | uint32_t sbz = 0; |
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454 | |
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455 | __asm__ volatile ( |
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456 | ARM_SWITCH_TO_ARM |
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457 | "mcr p15, 0, %[sbz], c8, c7, 0\n" |
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458 | ARM_SWITCH_BACK |
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459 | : ARM_SWITCH_OUTPUT |
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460 | : [sbz] "r" (sbz) |
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461 | ); |
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462 | } |
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463 | |
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464 | static inline void arm_cp15_tlb_invalidate_entry(const void *mva) |
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465 | { |
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466 | ARM_SWITCH_REGISTERS; |
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467 | |
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468 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
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469 | |
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470 | __asm__ volatile ( |
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471 | ARM_SWITCH_TO_ARM |
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472 | "mcr p15, 0, %[mva], c8, c7, 1\n" |
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473 | ARM_SWITCH_BACK |
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474 | : ARM_SWITCH_OUTPUT |
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475 | : [mva] "r" (mva) |
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476 | ); |
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477 | } |
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478 | |
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479 | static inline void arm_cp15_tlb_instruction_invalidate(void) |
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480 | { |
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481 | ARM_SWITCH_REGISTERS; |
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482 | uint32_t sbz = 0; |
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483 | |
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484 | __asm__ volatile ( |
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485 | ARM_SWITCH_TO_ARM |
---|
486 | "mcr p15, 0, %[sbz], c8, c5, 0\n" |
---|
487 | ARM_SWITCH_BACK |
---|
488 | : ARM_SWITCH_OUTPUT |
---|
489 | : [sbz] "r" (sbz) |
---|
490 | ); |
---|
491 | } |
---|
492 | |
---|
493 | static inline void arm_cp15_tlb_instruction_invalidate_entry(const void *mva) |
---|
494 | { |
---|
495 | ARM_SWITCH_REGISTERS; |
---|
496 | |
---|
497 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
---|
498 | |
---|
499 | __asm__ volatile ( |
---|
500 | ARM_SWITCH_TO_ARM |
---|
501 | "mcr p15, 0, %[mva], c8, c5, 1\n" |
---|
502 | ARM_SWITCH_BACK |
---|
503 | : ARM_SWITCH_OUTPUT |
---|
504 | : [mva] "r" (mva) |
---|
505 | ); |
---|
506 | } |
---|
507 | |
---|
508 | static inline void arm_cp15_tlb_data_invalidate(void) |
---|
509 | { |
---|
510 | ARM_SWITCH_REGISTERS; |
---|
511 | uint32_t sbz = 0; |
---|
512 | |
---|
513 | __asm__ volatile ( |
---|
514 | ARM_SWITCH_TO_ARM |
---|
515 | "mcr p15, 0, %[sbz], c8, c6, 0\n" |
---|
516 | ARM_SWITCH_BACK |
---|
517 | : ARM_SWITCH_OUTPUT |
---|
518 | : [sbz] "r" (sbz) |
---|
519 | ); |
---|
520 | } |
---|
521 | |
---|
522 | static inline void arm_cp15_tlb_data_invalidate_entry(const void *mva) |
---|
523 | { |
---|
524 | ARM_SWITCH_REGISTERS; |
---|
525 | |
---|
526 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
---|
527 | |
---|
528 | __asm__ volatile ( |
---|
529 | ARM_SWITCH_TO_ARM |
---|
530 | "mcr p15, 0, %[mva], c8, c6, 1\n" |
---|
531 | ARM_SWITCH_BACK |
---|
532 | : ARM_SWITCH_OUTPUT |
---|
533 | : [mva] "r" (mva) |
---|
534 | ); |
---|
535 | } |
---|
536 | |
---|
537 | static inline void arm_cp15_tlb_lockdown_entry(const void *mva) |
---|
538 | { |
---|
539 | uint32_t arm_switch_reg; |
---|
540 | |
---|
541 | __asm__ volatile ( |
---|
542 | ARM_SWITCH_TO_ARM |
---|
543 | "add %[arm_switch_reg], pc, #16\n" |
---|
544 | "mcr p15, 0, %[arm_switch_reg], c7, c13, 1\n" |
---|
545 | "mcr p15, 0, %[mva], c8, c7, 1\n" |
---|
546 | "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
547 | "orr %[arm_switch_reg], #0x1\n" |
---|
548 | "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
549 | "ldr %[mva], [%[mva]]\n" |
---|
550 | "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
551 | "bic %[arm_switch_reg], #0x1\n" |
---|
552 | "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
553 | ARM_SWITCH_BACK |
---|
554 | : [mva] "=r" (mva), [arm_switch_reg] "=&r" (arm_switch_reg) |
---|
555 | : "[mva]" (mva) |
---|
556 | ); |
---|
557 | } |
---|
558 | |
---|
559 | /** @} */ |
---|
560 | |
---|
561 | /** |
---|
562 | * @name Cache Functions |
---|
563 | * |
---|
564 | * @{ |
---|
565 | */ |
---|
566 | |
---|
567 | static inline uint32_t arm_cp15_get_cache_type(void) |
---|
568 | { |
---|
569 | ARM_SWITCH_REGISTERS; |
---|
570 | uint32_t val; |
---|
571 | |
---|
572 | __asm__ volatile ( |
---|
573 | ARM_SWITCH_TO_ARM |
---|
574 | "mrc p15, 0, %[val], c0, c0, 1\n" |
---|
575 | ARM_SWITCH_BACK |
---|
576 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
577 | ); |
---|
578 | |
---|
579 | return val; |
---|
580 | } |
---|
581 | |
---|
582 | static inline uint32_t arm_cp15_get_min_cache_line_size(void) |
---|
583 | { |
---|
584 | uint32_t mcls = 0; |
---|
585 | uint32_t ct = arm_cp15_get_cache_type(); |
---|
586 | uint32_t format = (ct >> 29) & 0x7U; |
---|
587 | |
---|
588 | if (format == 0x4) { |
---|
589 | mcls = (1U << (ct & 0xf)) * 4; |
---|
590 | } else if (format == 0x0) { |
---|
591 | uint32_t mask = (1U << 12) - 1; |
---|
592 | uint32_t dcls = (ct >> 12) & mask; |
---|
593 | uint32_t icls = ct & mask; |
---|
594 | |
---|
595 | mcls = dcls <= icls ? dcls : icls; |
---|
596 | } |
---|
597 | |
---|
598 | return mcls; |
---|
599 | } |
---|
600 | |
---|
601 | /* CCSIDR, Cache Size ID Register */ |
---|
602 | |
---|
603 | static inline uint32_t arm_cp15_get_cache_size_id(void) |
---|
604 | { |
---|
605 | ARM_SWITCH_REGISTERS; |
---|
606 | uint32_t val; |
---|
607 | |
---|
608 | __asm__ volatile ( |
---|
609 | ARM_SWITCH_TO_ARM |
---|
610 | "mrc p15, 1, %[val], c0, c0, 0\n" |
---|
611 | ARM_SWITCH_BACK |
---|
612 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
613 | ); |
---|
614 | |
---|
615 | return val; |
---|
616 | } |
---|
617 | |
---|
618 | /* CLIDR, Cache Level ID Register */ |
---|
619 | |
---|
620 | static inline uint32_t arm_cp15_get_cache_level_id(void) |
---|
621 | { |
---|
622 | ARM_SWITCH_REGISTERS; |
---|
623 | uint32_t val; |
---|
624 | |
---|
625 | __asm__ volatile ( |
---|
626 | ARM_SWITCH_TO_ARM |
---|
627 | "mrc p15, 1, %[val], c0, c0, 1\n" |
---|
628 | ARM_SWITCH_BACK |
---|
629 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
630 | ); |
---|
631 | |
---|
632 | return val; |
---|
633 | } |
---|
634 | |
---|
635 | /* CSSELR, Cache Size Selection Register */ |
---|
636 | |
---|
637 | static inline uint32_t arm_cp15_get_cache_size_selection(void) |
---|
638 | { |
---|
639 | ARM_SWITCH_REGISTERS; |
---|
640 | uint32_t val; |
---|
641 | |
---|
642 | __asm__ volatile ( |
---|
643 | ARM_SWITCH_TO_ARM |
---|
644 | "mrc p15, 2, %[val], c0, c0, 0\n" |
---|
645 | ARM_SWITCH_BACK |
---|
646 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
647 | ); |
---|
648 | |
---|
649 | return val; |
---|
650 | } |
---|
651 | |
---|
652 | static inline void arm_cp15_set_cache_size_selection(uint32_t val) |
---|
653 | { |
---|
654 | ARM_SWITCH_REGISTERS; |
---|
655 | |
---|
656 | __asm__ volatile ( |
---|
657 | ARM_SWITCH_TO_ARM |
---|
658 | "mcr p15, 2, %[val], c0, c0, 0\n" |
---|
659 | ARM_SWITCH_BACK |
---|
660 | : ARM_SWITCH_OUTPUT |
---|
661 | : [val] "r" (val) |
---|
662 | : "memory" |
---|
663 | ); |
---|
664 | } |
---|
665 | |
---|
666 | static inline void arm_cp15_cache_invalidate(void) |
---|
667 | { |
---|
668 | ARM_SWITCH_REGISTERS; |
---|
669 | uint32_t sbz = 0; |
---|
670 | |
---|
671 | __asm__ volatile ( |
---|
672 | ARM_SWITCH_TO_ARM |
---|
673 | "mcr p15, 0, %[sbz], c7, c7, 0\n" |
---|
674 | ARM_SWITCH_BACK |
---|
675 | : ARM_SWITCH_OUTPUT |
---|
676 | : [sbz] "r" (sbz) |
---|
677 | : "memory" |
---|
678 | ); |
---|
679 | } |
---|
680 | |
---|
681 | static inline void arm_cp15_instruction_cache_invalidate(void) |
---|
682 | { |
---|
683 | ARM_SWITCH_REGISTERS; |
---|
684 | uint32_t sbz = 0; |
---|
685 | |
---|
686 | __asm__ volatile ( |
---|
687 | ARM_SWITCH_TO_ARM |
---|
688 | "mcr p15, 0, %[sbz], c7, c5, 0\n" |
---|
689 | ARM_SWITCH_BACK |
---|
690 | : ARM_SWITCH_OUTPUT |
---|
691 | : [sbz] "r" (sbz) |
---|
692 | : "memory" |
---|
693 | ); |
---|
694 | } |
---|
695 | |
---|
696 | static inline void arm_cp15_instruction_cache_invalidate_line(const void *mva) |
---|
697 | { |
---|
698 | ARM_SWITCH_REGISTERS; |
---|
699 | |
---|
700 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
701 | |
---|
702 | __asm__ volatile ( |
---|
703 | ARM_SWITCH_TO_ARM |
---|
704 | "mcr p15, 0, %[mva], c7, c5, 1\n" |
---|
705 | ARM_SWITCH_BACK |
---|
706 | : ARM_SWITCH_OUTPUT |
---|
707 | : [mva] "r" (mva) |
---|
708 | : "memory" |
---|
709 | ); |
---|
710 | } |
---|
711 | |
---|
712 | static inline void arm_cp15_instruction_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) |
---|
713 | { |
---|
714 | ARM_SWITCH_REGISTERS; |
---|
715 | |
---|
716 | __asm__ volatile ( |
---|
717 | ARM_SWITCH_TO_ARM |
---|
718 | "mcr p15, 0, %[set_and_way], c7, c5, 2\n" |
---|
719 | ARM_SWITCH_BACK |
---|
720 | : ARM_SWITCH_OUTPUT |
---|
721 | : [set_and_way] "r" (set_and_way) |
---|
722 | : "memory" |
---|
723 | ); |
---|
724 | } |
---|
725 | |
---|
726 | static inline void arm_cp15_instruction_cache_prefetch_line(const void *mva) |
---|
727 | { |
---|
728 | ARM_SWITCH_REGISTERS; |
---|
729 | |
---|
730 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
731 | |
---|
732 | __asm__ volatile ( |
---|
733 | ARM_SWITCH_TO_ARM |
---|
734 | "mcr p15, 0, %[mva], c7, c13, 1\n" |
---|
735 | ARM_SWITCH_BACK |
---|
736 | : ARM_SWITCH_OUTPUT |
---|
737 | : [mva] "r" (mva) |
---|
738 | ); |
---|
739 | } |
---|
740 | |
---|
741 | static inline void arm_cp15_data_cache_invalidate(void) |
---|
742 | { |
---|
743 | ARM_SWITCH_REGISTERS; |
---|
744 | uint32_t sbz = 0; |
---|
745 | |
---|
746 | __asm__ volatile ( |
---|
747 | ARM_SWITCH_TO_ARM |
---|
748 | "mcr p15, 0, %[sbz], c7, c6, 0\n" |
---|
749 | ARM_SWITCH_BACK |
---|
750 | : ARM_SWITCH_OUTPUT |
---|
751 | : [sbz] "r" (sbz) |
---|
752 | : "memory" |
---|
753 | ); |
---|
754 | } |
---|
755 | |
---|
756 | static inline void arm_cp15_data_cache_invalidate_line(const void *mva) |
---|
757 | { |
---|
758 | ARM_SWITCH_REGISTERS; |
---|
759 | |
---|
760 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
761 | |
---|
762 | __asm__ volatile ( |
---|
763 | ARM_SWITCH_TO_ARM |
---|
764 | "mcr p15, 0, %[mva], c7, c6, 1\n" |
---|
765 | ARM_SWITCH_BACK |
---|
766 | : ARM_SWITCH_OUTPUT |
---|
767 | : [mva] "r" (mva) |
---|
768 | : "memory" |
---|
769 | ); |
---|
770 | } |
---|
771 | |
---|
772 | static inline void arm_cp15_data_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) |
---|
773 | { |
---|
774 | ARM_SWITCH_REGISTERS; |
---|
775 | |
---|
776 | __asm__ volatile ( |
---|
777 | ARM_SWITCH_TO_ARM |
---|
778 | "mcr p15, 0, %[set_and_way], c7, c6, 2\n" |
---|
779 | ARM_SWITCH_BACK |
---|
780 | : ARM_SWITCH_OUTPUT |
---|
781 | : [set_and_way] "r" (set_and_way) |
---|
782 | : "memory" |
---|
783 | ); |
---|
784 | } |
---|
785 | |
---|
786 | static inline void arm_cp15_data_cache_clean_line(const void *mva) |
---|
787 | { |
---|
788 | ARM_SWITCH_REGISTERS; |
---|
789 | |
---|
790 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
791 | |
---|
792 | __asm__ volatile ( |
---|
793 | ARM_SWITCH_TO_ARM |
---|
794 | "mcr p15, 0, %[mva], c7, c10, 1\n" |
---|
795 | ARM_SWITCH_BACK |
---|
796 | : ARM_SWITCH_OUTPUT |
---|
797 | : [mva] "r" (mva) |
---|
798 | : "memory" |
---|
799 | ); |
---|
800 | } |
---|
801 | |
---|
802 | static inline void arm_cp15_data_cache_clean_line_by_set_and_way(uint32_t set_and_way) |
---|
803 | { |
---|
804 | ARM_SWITCH_REGISTERS; |
---|
805 | |
---|
806 | __asm__ volatile ( |
---|
807 | ARM_SWITCH_TO_ARM |
---|
808 | "mcr p15, 0, %[set_and_way], c7, c10, 2\n" |
---|
809 | ARM_SWITCH_BACK |
---|
810 | : ARM_SWITCH_OUTPUT |
---|
811 | : [set_and_way] "r" (set_and_way) |
---|
812 | : "memory" |
---|
813 | ); |
---|
814 | } |
---|
815 | |
---|
816 | static inline void arm_cp15_data_cache_test_and_clean(void) |
---|
817 | { |
---|
818 | ARM_SWITCH_REGISTERS; |
---|
819 | |
---|
820 | __asm__ volatile ( |
---|
821 | ARM_SWITCH_TO_ARM |
---|
822 | "1:\n" |
---|
823 | "mrc p15, 0, r15, c7, c10, 3\n" |
---|
824 | "bne 1b\n" |
---|
825 | ARM_SWITCH_BACK |
---|
826 | : ARM_SWITCH_OUTPUT |
---|
827 | : |
---|
828 | : "memory" |
---|
829 | ); |
---|
830 | } |
---|
831 | |
---|
832 | /* In DDI0301H_arm1176jzfs_r0p7_trm |
---|
833 | * 'MCR p15, 0, <Rd>, c7, c14, 0' means |
---|
834 | * Clean and Invalidate Entire Data Cache |
---|
835 | */ |
---|
836 | static inline void arm_cp15_data_cache_clean_and_invalidate(void) |
---|
837 | { |
---|
838 | ARM_SWITCH_REGISTERS; |
---|
839 | |
---|
840 | uint32_t sbz = 0; |
---|
841 | |
---|
842 | __asm__ volatile ( |
---|
843 | ARM_SWITCH_TO_ARM |
---|
844 | "mcr p15, 0, %[sbz], c7, c14, 0\n" |
---|
845 | ARM_SWITCH_BACK |
---|
846 | : ARM_SWITCH_OUTPUT |
---|
847 | : [sbz] "r" (sbz) |
---|
848 | : "memory" |
---|
849 | ); |
---|
850 | |
---|
851 | } |
---|
852 | |
---|
853 | static inline void arm_cp15_data_cache_clean_and_invalidate_line(const void *mva) |
---|
854 | { |
---|
855 | ARM_SWITCH_REGISTERS; |
---|
856 | |
---|
857 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
858 | |
---|
859 | __asm__ volatile ( |
---|
860 | ARM_SWITCH_TO_ARM |
---|
861 | "mcr p15, 0, %[mva], c7, c14, 1\n" |
---|
862 | ARM_SWITCH_BACK |
---|
863 | : ARM_SWITCH_OUTPUT |
---|
864 | : [mva] "r" (mva) |
---|
865 | : "memory" |
---|
866 | ); |
---|
867 | } |
---|
868 | |
---|
869 | static inline void arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(uint32_t set_and_way) |
---|
870 | { |
---|
871 | ARM_SWITCH_REGISTERS; |
---|
872 | |
---|
873 | __asm__ volatile ( |
---|
874 | ARM_SWITCH_TO_ARM |
---|
875 | "mcr p15, 0, %[set_and_way], c7, c14, 2\n" |
---|
876 | ARM_SWITCH_BACK |
---|
877 | : ARM_SWITCH_OUTPUT |
---|
878 | : [set_and_way] "r" (set_and_way) |
---|
879 | : "memory" |
---|
880 | ); |
---|
881 | } |
---|
882 | |
---|
883 | static inline void arm_cp15_data_cache_test_and_clean_and_invalidate(void) |
---|
884 | { |
---|
885 | ARM_SWITCH_REGISTERS; |
---|
886 | |
---|
887 | __asm__ volatile ( |
---|
888 | ARM_SWITCH_TO_ARM |
---|
889 | "1:\n" |
---|
890 | "mrc p15, 0, r15, c7, c14, 3\n" |
---|
891 | "bne 1b\n" |
---|
892 | ARM_SWITCH_BACK |
---|
893 | : ARM_SWITCH_OUTPUT |
---|
894 | : |
---|
895 | : "memory" |
---|
896 | ); |
---|
897 | } |
---|
898 | |
---|
899 | /** @} */ |
---|
900 | |
---|
901 | static inline void arm_cp15_drain_write_buffer(void) |
---|
902 | { |
---|
903 | ARM_SWITCH_REGISTERS; |
---|
904 | uint32_t sbz = 0; |
---|
905 | |
---|
906 | __asm__ volatile ( |
---|
907 | ARM_SWITCH_TO_ARM |
---|
908 | "mcr p15, 0, %[sbz], c7, c10, 4\n" |
---|
909 | ARM_SWITCH_BACK |
---|
910 | : ARM_SWITCH_OUTPUT |
---|
911 | : [sbz] "r" (sbz) |
---|
912 | : "memory" |
---|
913 | ); |
---|
914 | } |
---|
915 | |
---|
916 | static inline void arm_cp15_wait_for_interrupt(void) |
---|
917 | { |
---|
918 | ARM_SWITCH_REGISTERS; |
---|
919 | uint32_t sbz = 0; |
---|
920 | |
---|
921 | __asm__ volatile ( |
---|
922 | ARM_SWITCH_TO_ARM |
---|
923 | "mcr p15, 0, %[sbz], c7, c0, 4\n" |
---|
924 | ARM_SWITCH_BACK |
---|
925 | : ARM_SWITCH_OUTPUT |
---|
926 | : [sbz] "r" (sbz) |
---|
927 | : "memory" |
---|
928 | ); |
---|
929 | } |
---|
930 | |
---|
931 | static inline uint32_t arm_cp15_get_multiprocessor_affinity(void) |
---|
932 | { |
---|
933 | ARM_SWITCH_REGISTERS; |
---|
934 | uint32_t mpidr; |
---|
935 | |
---|
936 | __asm__ volatile ( |
---|
937 | ARM_SWITCH_TO_ARM |
---|
938 | "mrc p15, 0, %[mpidr], c0, c0, 5\n" |
---|
939 | ARM_SWITCH_BACK |
---|
940 | : [mpidr] "=&r" (mpidr) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
941 | ); |
---|
942 | |
---|
943 | return mpidr & 0xff; |
---|
944 | } |
---|
945 | |
---|
946 | static inline uint32_t arm_cortex_a9_get_multiprocessor_cpu_id(void) |
---|
947 | { |
---|
948 | return arm_cp15_get_multiprocessor_affinity() & 0xff; |
---|
949 | } |
---|
950 | |
---|
951 | #define ARM_CORTEX_A9_ACTL_FW (1U << 0) |
---|
952 | #define ARM_CORTEX_A9_ACTL_L2_PREFETCH_HINT_ENABLE (1U << 1) |
---|
953 | #define ARM_CORTEX_A9_ACTL_L1_PREFETCH_ENABLE (1U << 2) |
---|
954 | #define ARM_CORTEX_A9_ACTL_WRITE_FULL_LINE_OF_ZEROS_MODE (1U << 3) |
---|
955 | #define ARM_CORTEX_A9_ACTL_SMP (1U << 6) |
---|
956 | #define ARM_CORTEX_A9_ACTL_EXCL (1U << 7) |
---|
957 | #define ARM_CORTEX_A9_ACTL_ALLOC_IN_ONE_WAY (1U << 8) |
---|
958 | #define ARM_CORTEX_A9_ACTL_PARITY_ON (1U << 9) |
---|
959 | |
---|
960 | static inline uint32_t arm_cp15_get_auxiliary_control(void) |
---|
961 | { |
---|
962 | ARM_SWITCH_REGISTERS; |
---|
963 | uint32_t val; |
---|
964 | |
---|
965 | __asm__ volatile ( |
---|
966 | ARM_SWITCH_TO_ARM |
---|
967 | "mrc p15, 0, %[val], c1, c0, 1\n" |
---|
968 | ARM_SWITCH_BACK |
---|
969 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
970 | ); |
---|
971 | |
---|
972 | return val; |
---|
973 | } |
---|
974 | |
---|
975 | static inline void arm_cp15_set_auxiliary_control(uint32_t val) |
---|
976 | { |
---|
977 | ARM_SWITCH_REGISTERS; |
---|
978 | |
---|
979 | __asm__ volatile ( |
---|
980 | ARM_SWITCH_TO_ARM |
---|
981 | "mcr p15, 0, %[val], c1, c0, 1\n" |
---|
982 | ARM_SWITCH_BACK |
---|
983 | : ARM_SWITCH_OUTPUT |
---|
984 | : [val] "r" (val) |
---|
985 | ); |
---|
986 | } |
---|
987 | |
---|
988 | /* ID_PFR1, Processor Feature Register 1 */ |
---|
989 | |
---|
990 | static inline uint32_t arm_cp15_get_processor_feature_1(void) |
---|
991 | { |
---|
992 | ARM_SWITCH_REGISTERS; |
---|
993 | uint32_t val; |
---|
994 | |
---|
995 | __asm__ volatile ( |
---|
996 | ARM_SWITCH_TO_ARM |
---|
997 | "mrc p15, 0, %[val], c0, c1, 1\n" |
---|
998 | ARM_SWITCH_BACK |
---|
999 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
1000 | ); |
---|
1001 | |
---|
1002 | return val; |
---|
1003 | } |
---|
1004 | |
---|
1005 | /* VBAR, Vector Base Address Register, Security Extensions */ |
---|
1006 | |
---|
1007 | static inline void *arm_cp15_get_vector_base_address(void) |
---|
1008 | { |
---|
1009 | ARM_SWITCH_REGISTERS; |
---|
1010 | void *base; |
---|
1011 | |
---|
1012 | __asm__ volatile ( |
---|
1013 | ARM_SWITCH_TO_ARM |
---|
1014 | "mrc p15, 0, %[base], c12, c0, 0\n" |
---|
1015 | ARM_SWITCH_BACK |
---|
1016 | : [base] "=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
1017 | ); |
---|
1018 | |
---|
1019 | return base; |
---|
1020 | } |
---|
1021 | |
---|
1022 | static inline void arm_cp15_set_vector_base_address(void *base) |
---|
1023 | { |
---|
1024 | ARM_SWITCH_REGISTERS; |
---|
1025 | |
---|
1026 | __asm__ volatile ( |
---|
1027 | ARM_SWITCH_TO_ARM |
---|
1028 | "mcr p15, 0, %[base], c12, c0, 0\n" |
---|
1029 | ARM_SWITCH_BACK |
---|
1030 | : ARM_SWITCH_OUTPUT |
---|
1031 | : [base] "r" (base) |
---|
1032 | ); |
---|
1033 | } |
---|
1034 | |
---|
1035 | /** |
---|
1036 | * @brief Sets the @a section_flags for the address range [@a begin, @a end). |
---|
1037 | * |
---|
1038 | * @return Previous section flags of the first modified entry. |
---|
1039 | */ |
---|
1040 | uint32_t arm_cp15_set_translation_table_entries( |
---|
1041 | const void *begin, |
---|
1042 | const void *end, |
---|
1043 | uint32_t section_flags |
---|
1044 | ); |
---|
1045 | |
---|
1046 | void arm_cp15_set_exception_handler( |
---|
1047 | Arm_symbolic_exception_name exception, |
---|
1048 | void (*handler)(void) |
---|
1049 | ); |
---|
1050 | |
---|
1051 | /** @} */ |
---|
1052 | |
---|
1053 | #ifdef __cplusplus |
---|
1054 | } |
---|
1055 | #endif /* __cplusplus */ |
---|
1056 | |
---|
1057 | #endif /* LIBCPU_SHARED_ARM_CP15_H */ |
---|