[39c8fdb] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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[5e657e2] | 4 | * @ingroup ScoreCPUARMCP15 |
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[39c8fdb] | 5 | * |
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| 6 | * @brief ARM co-processor 15 (CP15) API. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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[d2d02961] | 10 | * Copyright (c) 2009-2013 embedded brains GmbH. All rights reserved. |
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| 11 | * |
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| 12 | * embedded brains GmbH |
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| 13 | * Dornierstr. 4 |
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| 14 | * 82178 Puchheim |
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| 15 | * Germany |
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| 16 | * <info@embedded-brains.de> |
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[39c8fdb] | 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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| 20 | * http://www.rtems.com/license/LICENSE. |
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| 21 | */ |
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| 22 | |
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| 23 | #ifndef LIBCPU_SHARED_ARM_CP15_H |
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| 24 | #define LIBCPU_SHARED_ARM_CP15_H |
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| 25 | |
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| 26 | #include <rtems.h> |
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| 27 | |
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| 28 | #ifdef __cplusplus |
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| 29 | extern "C" { |
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| 30 | #endif /* __cplusplus */ |
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| 31 | |
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[5e657e2] | 32 | #define ARM_CP15_CACHE_PREPARE_MVA(mva) \ |
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| 33 | ((const void *) (((uint32_t) (mva)) & ~0x1fU)) |
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| 34 | |
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| 35 | #define ARM_CP15_TLB_PREPARE_MVA(mva) \ |
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| 36 | ((const void *) (((uint32_t) (mva)) & ~0x3fU)) |
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| 37 | |
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| 38 | /** |
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| 39 | * @defgroup ScoreCPUARMCP15 ARM Co-Processor 15 Support |
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| 40 | * |
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| 41 | * @ingroup ScoreCPUARM |
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| 42 | * |
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| 43 | * @brief ARM co-processor 15 (CP15) support. |
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| 44 | * |
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| 45 | * @{ |
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| 46 | */ |
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| 47 | |
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| 48 | /** |
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| 49 | * @name MMU Defines |
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| 50 | * |
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| 51 | * @{ |
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| 52 | */ |
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| 53 | |
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[39c8fdb] | 54 | #define ARM_MMU_SECT_BASE_SHIFT 20 |
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[5e657e2] | 55 | #define ARM_MMU_SECT_BASE_MASK (0xfffU << ARM_MMU_SECT_BASE_SHIFT) |
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[fd51f7e] | 56 | #define ARM_MMU_SECT_NS (1U << 19) |
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| 57 | #define ARM_MMU_SECT_NG (1U << 17) |
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| 58 | #define ARM_MMU_SECT_S (1U << 16) |
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| 59 | #define ARM_MMU_SECT_AP_2 (1U << 15) |
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| 60 | #define ARM_MMU_SECT_TEX_2 (1U << 14) |
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| 61 | #define ARM_MMU_SECT_TEX_1 (1U << 13) |
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| 62 | #define ARM_MMU_SECT_TEX_0 (1U << 12) |
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| 63 | #define ARM_MMU_SECT_TEX_SHIFT 12 |
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| 64 | #define ARM_MMU_SECT_TEX_MASK (0x3U << ARM_MMU_SECT_TEX_SHIFT) |
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[39c8fdb] | 65 | #define ARM_MMU_SECT_AP_1 (1U << 11) |
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| 66 | #define ARM_MMU_SECT_AP_0 (1U << 10) |
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| 67 | #define ARM_MMU_SECT_AP_SHIFT 10 |
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[fd51f7e] | 68 | #define ARM_MMU_SECT_AP_MASK (0x23U << ARM_MMU_SECT_AP_SHIFT) |
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| 69 | #define ARM_MMU_SECT_DOMAIN_SHIFT 5 |
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| 70 | #define ARM_MMU_SECT_DOMAIN_MASK (0xfU << ARM_MMU_SECT_DOMAIN_SHIFT) |
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| 71 | #define ARM_MMU_SECT_XN (1U << 4) |
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[39c8fdb] | 72 | #define ARM_MMU_SECT_C (1U << 3) |
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| 73 | #define ARM_MMU_SECT_B (1U << 2) |
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[fd51f7e] | 74 | #define ARM_MMU_SECT_PXN (1U << 0) |
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| 75 | #define ARM_MMU_SECT_DEFAULT 0x2U |
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[39c8fdb] | 76 | #define ARM_MMU_SECT_GET_INDEX(mva) \ |
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| 77 | (((uint32_t) (mva)) >> ARM_MMU_SECT_BASE_SHIFT) |
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| 78 | #define ARM_MMU_SECT_MVA_ALIGN_UP(mva) \ |
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| 79 | ((1U << ARM_MMU_SECT_BASE_SHIFT) \ |
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| 80 | + ((((uint32_t) (mva) - 1U)) & ~((1U << ARM_MMU_SECT_BASE_SHIFT) - 1U))) |
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| 81 | |
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| 82 | #define ARM_MMU_TRANSLATION_TABLE_ENTRY_SIZE 4U |
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| 83 | #define ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT 4096U |
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| 84 | |
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[1dcf5fe] | 85 | #define ARM_MMU_DEFAULT_CLIENT_DOMAIN 15U |
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| 86 | |
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| 87 | #define ARMV7_MMU_READ_ONLY \ |
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| 88 | ((ARM_MMU_DEFAULT_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ |
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| 89 | | ARM_MMU_SECT_AP_0 \ |
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| 90 | | ARM_MMU_SECT_AP_2 \ |
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| 91 | | ARM_MMU_SECT_DEFAULT) |
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| 92 | |
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| 93 | #define ARMV7_MMU_READ_ONLY_CACHED \ |
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[5b391f85] | 94 | (ARMV7_MMU_READ_ONLY | ARM_MMU_SECT_TEX_0 | ARM_MMU_SECT_C | ARM_MMU_SECT_B) |
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[1dcf5fe] | 95 | |
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| 96 | #define ARMV7_MMU_READ_WRITE \ |
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| 97 | ((ARM_MMU_DEFAULT_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \ |
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| 98 | | ARM_MMU_SECT_AP_0 \ |
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| 99 | | ARM_MMU_SECT_DEFAULT) |
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| 100 | |
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| 101 | #define ARMV7_MMU_READ_WRITE_CACHED \ |
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[5b391f85] | 102 | (ARMV7_MMU_READ_WRITE | ARM_MMU_SECT_TEX_0 | ARM_MMU_SECT_C | ARM_MMU_SECT_B) |
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[1dcf5fe] | 103 | |
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| 104 | #define ARMV7_MMU_DATA_READ_ONLY \ |
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| 105 | ARMV7_MMU_READ_ONLY |
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| 106 | |
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| 107 | #define ARMV7_MMU_DATA_READ_ONLY_CACHED \ |
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| 108 | ARMV7_MMU_READ_ONLY_CACHED |
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| 109 | |
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| 110 | #define ARMV7_MMU_DATA_READ_WRITE \ |
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| 111 | ARMV7_MMU_READ_WRITE |
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| 112 | |
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| 113 | #define ARMV7_MMU_DATA_READ_WRITE_CACHED \ |
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| 114 | ARMV7_MMU_READ_WRITE_CACHED |
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| 115 | |
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| 116 | #define ARMV7_MMU_DATA_READ_WRITE_SHAREABLE \ |
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| 117 | (ARMV7_MMU_READ_WRITE_CACHED | ARM_MMU_SECT_S) |
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| 118 | |
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| 119 | #define ARMV7_MMU_CODE \ |
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| 120 | ARMV7_MMU_READ_ONLY |
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| 121 | |
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| 122 | #define ARMV7_MMU_CODE_CACHED \ |
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| 123 | ARMV7_MMU_READ_ONLY_CACHED |
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| 124 | |
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| 125 | #define ARMV7_MMU_DEVICE \ |
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| 126 | (ARMV7_MMU_READ_WRITE | ARM_MMU_SECT_B) |
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| 127 | |
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[5e657e2] | 128 | /** @} */ |
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[39c8fdb] | 129 | |
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[5e657e2] | 130 | /** |
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| 131 | * @name Control Register Defines |
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| 132 | * |
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| 133 | * @{ |
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| 134 | */ |
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[39c8fdb] | 135 | |
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[fd51f7e] | 136 | #define ARM_CP15_CTRL_TE (1U << 30) |
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| 137 | #define ARM_CP15_CTRL_AFE (1U << 29) |
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| 138 | #define ARM_CP15_CTRL_TRE (1U << 28) |
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| 139 | #define ARM_CP15_CTRL_NMFI (1U << 27) |
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| 140 | #define ARM_CP15_CTRL_EE (1U << 25) |
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| 141 | #define ARM_CP15_CTRL_VE (1U << 24) |
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| 142 | #define ARM_CP15_CTRL_U (1U << 22) |
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| 143 | #define ARM_CP15_CTRL_FI (1U << 21) |
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| 144 | #define ARM_CP15_CTRL_UWXN (1U << 20) |
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| 145 | #define ARM_CP15_CTRL_WXN (1U << 19) |
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| 146 | #define ARM_CP15_CTRL_HA (1U << 17) |
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[5e657e2] | 147 | #define ARM_CP15_CTRL_L4 (1U << 15) |
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| 148 | #define ARM_CP15_CTRL_RR (1U << 14) |
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| 149 | #define ARM_CP15_CTRL_V (1U << 13) |
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| 150 | #define ARM_CP15_CTRL_I (1U << 12) |
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[fd51f7e] | 151 | #define ARM_CP15_CTRL_Z (1U << 11) |
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| 152 | #define ARM_CP15_CTRL_SW (1U << 10) |
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[5e657e2] | 153 | #define ARM_CP15_CTRL_R (1U << 9) |
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| 154 | #define ARM_CP15_CTRL_S (1U << 8) |
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| 155 | #define ARM_CP15_CTRL_B (1U << 7) |
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[fd51f7e] | 156 | #define ARM_CP15_CTRL_CP15BEN (1U << 5) |
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[5e657e2] | 157 | #define ARM_CP15_CTRL_C (1U << 2) |
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| 158 | #define ARM_CP15_CTRL_A (1U << 1) |
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| 159 | #define ARM_CP15_CTRL_M (1U << 0) |
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[39c8fdb] | 160 | |
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[5e657e2] | 161 | /** @} */ |
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| 162 | |
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| 163 | /** |
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| 164 | * @name Domain Access Control Defines |
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| 165 | * |
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| 166 | * @{ |
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| 167 | */ |
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| 168 | |
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| 169 | #define ARM_CP15_DAC_NO_ACCESS 0x0U |
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| 170 | #define ARM_CP15_DAC_CLIENT 0x1U |
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| 171 | #define ARM_CP15_DAC_MANAGER 0x3U |
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| 172 | #define ARM_CP15_DAC_DOMAIN(index, val) ((val) << (2 * index)) |
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| 173 | |
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| 174 | /** @} */ |
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| 175 | |
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| 176 | static inline uint32_t arm_cp15_get_id_code(void) |
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[39c8fdb] | 177 | { |
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| 178 | ARM_SWITCH_REGISTERS; |
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| 179 | uint32_t val; |
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| 180 | |
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[139ec149] | 181 | __asm__ volatile ( |
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[39c8fdb] | 182 | ARM_SWITCH_TO_ARM |
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[5e657e2] | 183 | "mrc p15, 0, %[val], c0, c0, 0\n" |
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[39c8fdb] | 184 | ARM_SWITCH_BACK |
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| 185 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 186 | ); |
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| 187 | |
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| 188 | return val; |
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| 189 | } |
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| 190 | |
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| 191 | static inline uint32_t arm_cp15_get_tcm_status(void) |
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| 192 | { |
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| 193 | ARM_SWITCH_REGISTERS; |
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| 194 | uint32_t val; |
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| 195 | |
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[139ec149] | 196 | __asm__ volatile ( |
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[39c8fdb] | 197 | ARM_SWITCH_TO_ARM |
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| 198 | "mrc p15, 0, %[val], c0, c0, 2\n" |
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| 199 | ARM_SWITCH_BACK |
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| 200 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 201 | ); |
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| 202 | |
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| 203 | return val; |
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| 204 | } |
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| 205 | |
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| 206 | static inline uint32_t arm_cp15_get_control(void) |
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| 207 | { |
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| 208 | ARM_SWITCH_REGISTERS; |
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| 209 | uint32_t val; |
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| 210 | |
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[139ec149] | 211 | __asm__ volatile ( |
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[39c8fdb] | 212 | ARM_SWITCH_TO_ARM |
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| 213 | "mrc p15, 0, %[val], c1, c0, 0\n" |
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| 214 | ARM_SWITCH_BACK |
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| 215 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 216 | ); |
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| 217 | |
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| 218 | return val; |
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| 219 | } |
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| 220 | |
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| 221 | static inline void arm_cp15_set_control(uint32_t val) |
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| 222 | { |
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| 223 | ARM_SWITCH_REGISTERS; |
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| 224 | |
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[139ec149] | 225 | __asm__ volatile ( |
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[39c8fdb] | 226 | ARM_SWITCH_TO_ARM |
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| 227 | "mcr p15, 0, %[val], c1, c0, 0\n" |
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| 228 | "nop\n" |
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| 229 | "nop\n" |
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| 230 | ARM_SWITCH_BACK |
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| 231 | : ARM_SWITCH_OUTPUT |
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| 232 | : [val] "r" (val) |
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| 233 | : "memory" |
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| 234 | ); |
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| 235 | } |
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| 236 | |
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[5e657e2] | 237 | /** |
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| 238 | * @name MMU Functions |
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| 239 | * |
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| 240 | * @{ |
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| 241 | */ |
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| 242 | |
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[544615d] | 243 | /** |
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| 244 | * @brief Disable the MMU. |
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| 245 | * |
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| 246 | * This function will clean and invalidate eight cache lines before and after |
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| 247 | * the current stack pointer. |
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| 248 | * |
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| 249 | * @param[in] cls The data cache line size. |
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| 250 | * |
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| 251 | * @return The current control register value. |
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| 252 | */ |
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| 253 | static inline uint32_t arm_cp15_mmu_disable(uint32_t cls) |
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| 254 | { |
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| 255 | ARM_SWITCH_REGISTERS; |
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| 256 | uint32_t ctrl; |
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| 257 | uint32_t tmp_0; |
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| 258 | uint32_t tmp_1; |
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| 259 | |
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| 260 | __asm__ volatile ( |
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| 261 | ARM_SWITCH_TO_ARM |
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| 262 | "mrc p15, 0, %[ctrl], c1, c0, 0\n" |
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| 263 | "bic %[tmp_0], %[ctrl], #1\n" |
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| 264 | "mcr p15, 0, %[tmp_0], c1, c0, 0\n" |
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| 265 | "nop\n" |
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| 266 | "nop\n" |
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| 267 | "mov %[tmp_1], sp\n" |
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| 268 | "rsb %[tmp_0], %[cls], #0\n" |
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| 269 | "and %[tmp_0], %[tmp_0], %[tmp_1]\n" |
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| 270 | "sub %[tmp_0], %[tmp_0], %[cls], asl #3\n" |
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| 271 | "add %[tmp_1], %[tmp_0], %[cls], asl #4\n" |
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| 272 | "1:\n" |
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| 273 | "mcr p15, 0, %[tmp_0], c7, c14, 1\n" |
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| 274 | "add %[tmp_0], %[tmp_0], %[cls]\n" |
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| 275 | "cmp %[tmp_1], %[tmp_0]\n" |
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| 276 | "bne 1b\n" |
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| 277 | ARM_SWITCH_BACK |
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| 278 | : [ctrl] "=&r" (ctrl), |
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| 279 | [tmp_0] "=&r" (tmp_0), |
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| 280 | [tmp_1] "=&r" (tmp_1) |
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| 281 | ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 282 | : [cls] "r" (cls) |
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| 283 | : "memory", "cc" |
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| 284 | ); |
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| 285 | |
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| 286 | return ctrl; |
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| 287 | } |
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| 288 | |
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[39c8fdb] | 289 | static inline uint32_t *arm_cp15_get_translation_table_base(void) |
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| 290 | { |
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| 291 | ARM_SWITCH_REGISTERS; |
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| 292 | uint32_t *base; |
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| 293 | |
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[139ec149] | 294 | __asm__ volatile ( |
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[39c8fdb] | 295 | ARM_SWITCH_TO_ARM |
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| 296 | "mrc p15, 0, %[base], c2, c0, 0\n" |
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| 297 | ARM_SWITCH_BACK |
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| 298 | : [base] "=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 299 | ); |
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| 300 | |
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| 301 | return base; |
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| 302 | } |
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| 303 | |
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| 304 | static inline void arm_cp15_set_translation_table_base(uint32_t *base) |
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| 305 | { |
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| 306 | ARM_SWITCH_REGISTERS; |
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| 307 | |
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[139ec149] | 308 | __asm__ volatile ( |
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[39c8fdb] | 309 | ARM_SWITCH_TO_ARM |
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| 310 | "mcr p15, 0, %[base], c2, c0, 0\n" |
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| 311 | ARM_SWITCH_BACK |
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| 312 | : ARM_SWITCH_OUTPUT |
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| 313 | : [base] "r" (base) |
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| 314 | ); |
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| 315 | } |
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| 316 | |
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| 317 | static inline uint32_t arm_cp15_get_domain_access_control(void) |
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| 318 | { |
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| 319 | ARM_SWITCH_REGISTERS; |
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| 320 | uint32_t val; |
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| 321 | |
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[139ec149] | 322 | __asm__ volatile ( |
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[39c8fdb] | 323 | ARM_SWITCH_TO_ARM |
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| 324 | "mrc p15, 0, %[val], c3, c0, 0\n" |
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| 325 | ARM_SWITCH_BACK |
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| 326 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 327 | ); |
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| 328 | |
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| 329 | return val; |
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| 330 | } |
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| 331 | |
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| 332 | static inline void arm_cp15_set_domain_access_control(uint32_t val) |
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| 333 | { |
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| 334 | ARM_SWITCH_REGISTERS; |
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| 335 | |
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[139ec149] | 336 | __asm__ volatile ( |
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[39c8fdb] | 337 | ARM_SWITCH_TO_ARM |
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| 338 | "mcr p15, 0, %[val], c3, c0, 0\n" |
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| 339 | ARM_SWITCH_BACK |
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| 340 | : ARM_SWITCH_OUTPUT |
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| 341 | : [val] "r" (val) |
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| 342 | ); |
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| 343 | } |
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| 344 | |
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| 345 | static inline uint32_t arm_cp15_get_data_fault_status(void) |
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| 346 | { |
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| 347 | ARM_SWITCH_REGISTERS; |
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| 348 | uint32_t val; |
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| 349 | |
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[139ec149] | 350 | __asm__ volatile ( |
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[39c8fdb] | 351 | ARM_SWITCH_TO_ARM |
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| 352 | "mrc p15, 0, %[val], c5, c0, 0\n" |
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| 353 | ARM_SWITCH_BACK |
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| 354 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 355 | ); |
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| 356 | |
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| 357 | return val; |
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| 358 | } |
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| 359 | |
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| 360 | static inline void arm_cp15_set_data_fault_status(uint32_t val) |
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| 361 | { |
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| 362 | ARM_SWITCH_REGISTERS; |
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| 363 | |
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[139ec149] | 364 | __asm__ volatile ( |
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[39c8fdb] | 365 | ARM_SWITCH_TO_ARM |
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| 366 | "mcr p15, 0, %[val], c5, c0, 0\n" |
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| 367 | ARM_SWITCH_BACK |
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| 368 | : ARM_SWITCH_OUTPUT |
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| 369 | : [val] "r" (val) |
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| 370 | ); |
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| 371 | } |
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| 372 | |
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| 373 | static inline uint32_t arm_cp15_get_instruction_fault_status(void) |
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| 374 | { |
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| 375 | ARM_SWITCH_REGISTERS; |
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| 376 | uint32_t val; |
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| 377 | |
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[139ec149] | 378 | __asm__ volatile ( |
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[39c8fdb] | 379 | ARM_SWITCH_TO_ARM |
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| 380 | "mrc p15, 0, %[val], c5, c0, 1\n" |
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| 381 | ARM_SWITCH_BACK |
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| 382 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 383 | ); |
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| 384 | |
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| 385 | return val; |
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| 386 | } |
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| 387 | |
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| 388 | static inline void arm_cp15_set_instruction_fault_status(uint32_t val) |
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| 389 | { |
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| 390 | ARM_SWITCH_REGISTERS; |
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| 391 | |
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[139ec149] | 392 | __asm__ volatile ( |
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[39c8fdb] | 393 | ARM_SWITCH_TO_ARM |
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| 394 | "mcr p15, 0, %[val], c5, c0, 1\n" |
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| 395 | ARM_SWITCH_BACK |
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| 396 | : ARM_SWITCH_OUTPUT |
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| 397 | : [val] "r" (val) |
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| 398 | ); |
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| 399 | } |
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| 400 | |
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| 401 | static inline void *arm_cp15_get_fault_address(void) |
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| 402 | { |
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| 403 | ARM_SWITCH_REGISTERS; |
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| 404 | void *mva; |
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| 405 | |
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[139ec149] | 406 | __asm__ volatile ( |
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[39c8fdb] | 407 | ARM_SWITCH_TO_ARM |
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| 408 | "mrc p15, 0, %[mva], c6, c0, 0\n" |
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| 409 | ARM_SWITCH_BACK |
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| 410 | : [mva] "=&r" (mva) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 411 | ); |
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| 412 | |
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| 413 | return mva; |
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| 414 | } |
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| 415 | |
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| 416 | static inline void arm_cp15_set_fault_address(const void *mva) |
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| 417 | { |
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| 418 | ARM_SWITCH_REGISTERS; |
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| 419 | |
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[139ec149] | 420 | __asm__ volatile ( |
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[39c8fdb] | 421 | ARM_SWITCH_TO_ARM |
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| 422 | "mcr p15, 0, %[mva], c6, c0, 0\n" |
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| 423 | ARM_SWITCH_BACK |
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| 424 | : ARM_SWITCH_OUTPUT |
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| 425 | : [mva] "r" (mva) |
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| 426 | ); |
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| 427 | } |
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| 428 | |
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[5e657e2] | 429 | static inline void arm_cp15_tlb_invalidate(void) |
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[39c8fdb] | 430 | { |
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| 431 | ARM_SWITCH_REGISTERS; |
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| 432 | uint32_t sbz = 0; |
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| 433 | |
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[139ec149] | 434 | __asm__ volatile ( |
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[39c8fdb] | 435 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 436 | "mcr p15, 0, %[sbz], c8, c7, 0\n" |
---|
[39c8fdb] | 437 | ARM_SWITCH_BACK |
---|
| 438 | : ARM_SWITCH_OUTPUT |
---|
| 439 | : [sbz] "r" (sbz) |
---|
| 440 | ); |
---|
| 441 | } |
---|
| 442 | |
---|
[5e657e2] | 443 | static inline void arm_cp15_tlb_invalidate_entry(const void *mva) |
---|
| 444 | { |
---|
| 445 | ARM_SWITCH_REGISTERS; |
---|
| 446 | |
---|
| 447 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
---|
| 448 | |
---|
[139ec149] | 449 | __asm__ volatile ( |
---|
[5e657e2] | 450 | ARM_SWITCH_TO_ARM |
---|
| 451 | "mcr p15, 0, %[mva], c8, c7, 1\n" |
---|
| 452 | ARM_SWITCH_BACK |
---|
| 453 | : ARM_SWITCH_OUTPUT |
---|
| 454 | : [mva] "r" (mva) |
---|
| 455 | ); |
---|
| 456 | } |
---|
| 457 | |
---|
| 458 | static inline void arm_cp15_tlb_instruction_invalidate(void) |
---|
[39c8fdb] | 459 | { |
---|
| 460 | ARM_SWITCH_REGISTERS; |
---|
| 461 | uint32_t sbz = 0; |
---|
| 462 | |
---|
[139ec149] | 463 | __asm__ volatile ( |
---|
[39c8fdb] | 464 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 465 | "mcr p15, 0, %[sbz], c8, c5, 0\n" |
---|
[39c8fdb] | 466 | ARM_SWITCH_BACK |
---|
| 467 | : ARM_SWITCH_OUTPUT |
---|
| 468 | : [sbz] "r" (sbz) |
---|
| 469 | ); |
---|
| 470 | } |
---|
| 471 | |
---|
[5e657e2] | 472 | static inline void arm_cp15_tlb_instruction_invalidate_entry(const void *mva) |
---|
[39c8fdb] | 473 | { |
---|
| 474 | ARM_SWITCH_REGISTERS; |
---|
| 475 | |
---|
[5e657e2] | 476 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
---|
[39c8fdb] | 477 | |
---|
[139ec149] | 478 | __asm__ volatile ( |
---|
[39c8fdb] | 479 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 480 | "mcr p15, 0, %[mva], c8, c5, 1\n" |
---|
[39c8fdb] | 481 | ARM_SWITCH_BACK |
---|
| 482 | : ARM_SWITCH_OUTPUT |
---|
| 483 | : [mva] "r" (mva) |
---|
| 484 | ); |
---|
| 485 | } |
---|
| 486 | |
---|
[5e657e2] | 487 | static inline void arm_cp15_tlb_data_invalidate(void) |
---|
[39c8fdb] | 488 | { |
---|
| 489 | ARM_SWITCH_REGISTERS; |
---|
[5e657e2] | 490 | uint32_t sbz = 0; |
---|
[39c8fdb] | 491 | |
---|
[139ec149] | 492 | __asm__ volatile ( |
---|
[39c8fdb] | 493 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 494 | "mcr p15, 0, %[sbz], c8, c6, 0\n" |
---|
[39c8fdb] | 495 | ARM_SWITCH_BACK |
---|
| 496 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 497 | : [sbz] "r" (sbz) |
---|
[39c8fdb] | 498 | ); |
---|
| 499 | } |
---|
| 500 | |
---|
[5e657e2] | 501 | static inline void arm_cp15_tlb_data_invalidate_entry(const void *mva) |
---|
[39c8fdb] | 502 | { |
---|
| 503 | ARM_SWITCH_REGISTERS; |
---|
| 504 | |
---|
[5e657e2] | 505 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
---|
[39c8fdb] | 506 | |
---|
[139ec149] | 507 | __asm__ volatile ( |
---|
[39c8fdb] | 508 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 509 | "mcr p15, 0, %[mva], c8, c6, 1\n" |
---|
[39c8fdb] | 510 | ARM_SWITCH_BACK |
---|
| 511 | : ARM_SWITCH_OUTPUT |
---|
| 512 | : [mva] "r" (mva) |
---|
| 513 | ); |
---|
| 514 | } |
---|
| 515 | |
---|
[5e657e2] | 516 | static inline void arm_cp15_tlb_lockdown_entry(const void *mva) |
---|
[39c8fdb] | 517 | { |
---|
[5e657e2] | 518 | uint32_t arm_switch_reg; |
---|
[39c8fdb] | 519 | |
---|
[139ec149] | 520 | __asm__ volatile ( |
---|
[39c8fdb] | 521 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 522 | "add %[arm_switch_reg], pc, #16\n" |
---|
| 523 | "mcr p15, 0, %[arm_switch_reg], c7, c13, 1\n" |
---|
| 524 | "mcr p15, 0, %[mva], c8, c7, 1\n" |
---|
| 525 | "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
| 526 | "orr %[arm_switch_reg], #0x1\n" |
---|
| 527 | "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
| 528 | "ldr %[mva], [%[mva]]\n" |
---|
| 529 | "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
| 530 | "bic %[arm_switch_reg], #0x1\n" |
---|
| 531 | "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
[39c8fdb] | 532 | ARM_SWITCH_BACK |
---|
[5e657e2] | 533 | : [mva] "=r" (mva), [arm_switch_reg] "=&r" (arm_switch_reg) |
---|
| 534 | : "[mva]" (mva) |
---|
[39c8fdb] | 535 | ); |
---|
| 536 | } |
---|
| 537 | |
---|
[5e657e2] | 538 | /** @} */ |
---|
| 539 | |
---|
| 540 | /** |
---|
| 541 | * @name Cache Functions |
---|
| 542 | * |
---|
| 543 | * @{ |
---|
| 544 | */ |
---|
| 545 | |
---|
| 546 | static inline uint32_t arm_cp15_get_cache_type(void) |
---|
[39c8fdb] | 547 | { |
---|
| 548 | ARM_SWITCH_REGISTERS; |
---|
[5e657e2] | 549 | uint32_t val; |
---|
[39c8fdb] | 550 | |
---|
[139ec149] | 551 | __asm__ volatile ( |
---|
[5e657e2] | 552 | ARM_SWITCH_TO_ARM |
---|
| 553 | "mrc p15, 0, %[val], c0, c0, 1\n" |
---|
| 554 | ARM_SWITCH_BACK |
---|
| 555 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
| 556 | ); |
---|
| 557 | |
---|
| 558 | return val; |
---|
| 559 | } |
---|
| 560 | |
---|
[d2d02961] | 561 | static inline uint32_t arm_cp15_get_min_cache_line_size(void) |
---|
| 562 | { |
---|
| 563 | uint32_t mcls = 0; |
---|
| 564 | uint32_t ct = arm_cp15_get_cache_type(); |
---|
| 565 | uint32_t format = (ct >> 29) & 0x7U; |
---|
| 566 | |
---|
| 567 | if (format == 0x4) { |
---|
| 568 | mcls = (1U << (ct & 0xf)) * 4; |
---|
| 569 | } else if (format == 0x0) { |
---|
| 570 | uint32_t mask = (1U << 12) - 1; |
---|
| 571 | uint32_t dcls = (ct >> 12) & mask; |
---|
| 572 | uint32_t icls = ct & mask; |
---|
| 573 | |
---|
| 574 | mcls = dcls <= icls ? dcls : icls; |
---|
| 575 | } |
---|
| 576 | |
---|
| 577 | return mcls; |
---|
| 578 | } |
---|
| 579 | |
---|
[c9b66f5] | 580 | /* CCSIDR, Cache Size ID Register */ |
---|
| 581 | |
---|
| 582 | static inline uint32_t arm_cp15_get_cache_size_id(void) |
---|
| 583 | { |
---|
| 584 | ARM_SWITCH_REGISTERS; |
---|
| 585 | uint32_t val; |
---|
| 586 | |
---|
| 587 | __asm__ volatile ( |
---|
| 588 | ARM_SWITCH_TO_ARM |
---|
[d157a4fd] | 589 | "mrc p15, 1, %[val], c0, c0, 0\n" |
---|
[c9b66f5] | 590 | ARM_SWITCH_BACK |
---|
| 591 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
| 592 | ); |
---|
| 593 | |
---|
| 594 | return val; |
---|
| 595 | } |
---|
| 596 | |
---|
| 597 | /* CLIDR, Cache Level ID Register */ |
---|
| 598 | |
---|
| 599 | static inline uint32_t arm_cp15_get_cache_level_id(void) |
---|
| 600 | { |
---|
| 601 | ARM_SWITCH_REGISTERS; |
---|
| 602 | uint32_t val; |
---|
| 603 | |
---|
| 604 | __asm__ volatile ( |
---|
| 605 | ARM_SWITCH_TO_ARM |
---|
[d157a4fd] | 606 | "mrc p15, 1, %[val], c0, c0, 1\n" |
---|
[c9b66f5] | 607 | ARM_SWITCH_BACK |
---|
| 608 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
| 609 | ); |
---|
| 610 | |
---|
| 611 | return val; |
---|
| 612 | } |
---|
| 613 | |
---|
| 614 | /* CSSELR, Cache Size Selection Register */ |
---|
| 615 | |
---|
| 616 | static inline uint32_t arm_cp15_get_cache_size_selection(void) |
---|
| 617 | { |
---|
| 618 | ARM_SWITCH_REGISTERS; |
---|
| 619 | uint32_t val; |
---|
| 620 | |
---|
| 621 | __asm__ volatile ( |
---|
| 622 | ARM_SWITCH_TO_ARM |
---|
[d157a4fd] | 623 | "mrc p15, 2, %[val], c0, c0, 0\n" |
---|
[c9b66f5] | 624 | ARM_SWITCH_BACK |
---|
| 625 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
| 626 | ); |
---|
| 627 | |
---|
| 628 | return val; |
---|
| 629 | } |
---|
| 630 | |
---|
| 631 | static inline void arm_cp15_set_cache_size_selection(uint32_t val) |
---|
| 632 | { |
---|
| 633 | ARM_SWITCH_REGISTERS; |
---|
| 634 | |
---|
| 635 | __asm__ volatile ( |
---|
| 636 | ARM_SWITCH_TO_ARM |
---|
| 637 | "mcr p15, 2, %[val], c0, c0, 0\n" |
---|
| 638 | ARM_SWITCH_BACK |
---|
| 639 | : ARM_SWITCH_OUTPUT |
---|
| 640 | : [val] "r" (val) |
---|
| 641 | : "memory" |
---|
| 642 | ); |
---|
| 643 | } |
---|
| 644 | |
---|
[5e657e2] | 645 | static inline void arm_cp15_cache_invalidate(void) |
---|
| 646 | { |
---|
| 647 | ARM_SWITCH_REGISTERS; |
---|
| 648 | uint32_t sbz = 0; |
---|
[39c8fdb] | 649 | |
---|
[139ec149] | 650 | __asm__ volatile ( |
---|
[39c8fdb] | 651 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 652 | "mcr p15, 0, %[sbz], c7, c7, 0\n" |
---|
[39c8fdb] | 653 | ARM_SWITCH_BACK |
---|
| 654 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 655 | : [sbz] "r" (sbz) |
---|
[39c8fdb] | 656 | : "memory" |
---|
| 657 | ); |
---|
| 658 | } |
---|
| 659 | |
---|
[5e657e2] | 660 | static inline void arm_cp15_instruction_cache_invalidate(void) |
---|
[39c8fdb] | 661 | { |
---|
| 662 | ARM_SWITCH_REGISTERS; |
---|
[5e657e2] | 663 | uint32_t sbz = 0; |
---|
[39c8fdb] | 664 | |
---|
[139ec149] | 665 | __asm__ volatile ( |
---|
[39c8fdb] | 666 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 667 | "mcr p15, 0, %[sbz], c7, c5, 0\n" |
---|
[39c8fdb] | 668 | ARM_SWITCH_BACK |
---|
| 669 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 670 | : [sbz] "r" (sbz) |
---|
[39c8fdb] | 671 | : "memory" |
---|
| 672 | ); |
---|
| 673 | } |
---|
| 674 | |
---|
[5e657e2] | 675 | static inline void arm_cp15_instruction_cache_invalidate_line(const void *mva) |
---|
[39c8fdb] | 676 | { |
---|
| 677 | ARM_SWITCH_REGISTERS; |
---|
| 678 | |
---|
| 679 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
| 680 | |
---|
[139ec149] | 681 | __asm__ volatile ( |
---|
[39c8fdb] | 682 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 683 | "mcr p15, 0, %[mva], c7, c5, 1\n" |
---|
[39c8fdb] | 684 | ARM_SWITCH_BACK |
---|
| 685 | : ARM_SWITCH_OUTPUT |
---|
| 686 | : [mva] "r" (mva) |
---|
| 687 | : "memory" |
---|
| 688 | ); |
---|
| 689 | } |
---|
| 690 | |
---|
[5e657e2] | 691 | static inline void arm_cp15_instruction_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) |
---|
[39c8fdb] | 692 | { |
---|
| 693 | ARM_SWITCH_REGISTERS; |
---|
| 694 | |
---|
[139ec149] | 695 | __asm__ volatile ( |
---|
[39c8fdb] | 696 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 697 | "mcr p15, 0, %[set_and_way], c7, c5, 2\n" |
---|
[39c8fdb] | 698 | ARM_SWITCH_BACK |
---|
| 699 | : ARM_SWITCH_OUTPUT |
---|
| 700 | : [set_and_way] "r" (set_and_way) |
---|
| 701 | : "memory" |
---|
| 702 | ); |
---|
| 703 | } |
---|
| 704 | |
---|
[5e657e2] | 705 | static inline void arm_cp15_instruction_cache_prefetch_line(const void *mva) |
---|
[39c8fdb] | 706 | { |
---|
| 707 | ARM_SWITCH_REGISTERS; |
---|
| 708 | |
---|
[5e657e2] | 709 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
| 710 | |
---|
[139ec149] | 711 | __asm__ volatile ( |
---|
[39c8fdb] | 712 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 713 | "mcr p15, 0, %[mva], c7, c13, 1\n" |
---|
[39c8fdb] | 714 | ARM_SWITCH_BACK |
---|
| 715 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 716 | : [mva] "r" (mva) |
---|
[39c8fdb] | 717 | ); |
---|
| 718 | } |
---|
| 719 | |
---|
[5e657e2] | 720 | static inline void arm_cp15_data_cache_invalidate(void) |
---|
[39c8fdb] | 721 | { |
---|
| 722 | ARM_SWITCH_REGISTERS; |
---|
[5e657e2] | 723 | uint32_t sbz = 0; |
---|
[39c8fdb] | 724 | |
---|
[139ec149] | 725 | __asm__ volatile ( |
---|
[39c8fdb] | 726 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 727 | "mcr p15, 0, %[sbz], c7, c6, 0\n" |
---|
[39c8fdb] | 728 | ARM_SWITCH_BACK |
---|
| 729 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 730 | : [sbz] "r" (sbz) |
---|
[39c8fdb] | 731 | : "memory" |
---|
| 732 | ); |
---|
| 733 | } |
---|
| 734 | |
---|
[5e657e2] | 735 | static inline void arm_cp15_data_cache_invalidate_line(const void *mva) |
---|
[39c8fdb] | 736 | { |
---|
| 737 | ARM_SWITCH_REGISTERS; |
---|
| 738 | |
---|
[5e657e2] | 739 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
| 740 | |
---|
[139ec149] | 741 | __asm__ volatile ( |
---|
[39c8fdb] | 742 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 743 | "mcr p15, 0, %[mva], c7, c6, 1\n" |
---|
[39c8fdb] | 744 | ARM_SWITCH_BACK |
---|
| 745 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 746 | : [mva] "r" (mva) |
---|
[39c8fdb] | 747 | : "memory" |
---|
| 748 | ); |
---|
| 749 | } |
---|
| 750 | |
---|
[5e657e2] | 751 | static inline void arm_cp15_data_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) |
---|
[39c8fdb] | 752 | { |
---|
| 753 | ARM_SWITCH_REGISTERS; |
---|
| 754 | |
---|
[139ec149] | 755 | __asm__ volatile ( |
---|
[39c8fdb] | 756 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 757 | "mcr p15, 0, %[set_and_way], c7, c6, 2\n" |
---|
[39c8fdb] | 758 | ARM_SWITCH_BACK |
---|
| 759 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 760 | : [set_and_way] "r" (set_and_way) |
---|
[39c8fdb] | 761 | : "memory" |
---|
| 762 | ); |
---|
| 763 | } |
---|
| 764 | |
---|
[5e657e2] | 765 | static inline void arm_cp15_data_cache_clean_line(const void *mva) |
---|
[39c8fdb] | 766 | { |
---|
| 767 | ARM_SWITCH_REGISTERS; |
---|
[5e657e2] | 768 | |
---|
| 769 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
[39c8fdb] | 770 | |
---|
[139ec149] | 771 | __asm__ volatile ( |
---|
[39c8fdb] | 772 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 773 | "mcr p15, 0, %[mva], c7, c10, 1\n" |
---|
[39c8fdb] | 774 | ARM_SWITCH_BACK |
---|
| 775 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 776 | : [mva] "r" (mva) |
---|
[39c8fdb] | 777 | : "memory" |
---|
| 778 | ); |
---|
| 779 | } |
---|
| 780 | |
---|
[5e657e2] | 781 | static inline void arm_cp15_data_cache_clean_line_by_set_and_way(uint32_t set_and_way) |
---|
[39c8fdb] | 782 | { |
---|
| 783 | ARM_SWITCH_REGISTERS; |
---|
| 784 | |
---|
[139ec149] | 785 | __asm__ volatile ( |
---|
[39c8fdb] | 786 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 787 | "mcr p15, 0, %[set_and_way], c7, c10, 2\n" |
---|
[39c8fdb] | 788 | ARM_SWITCH_BACK |
---|
| 789 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 790 | : [set_and_way] "r" (set_and_way) |
---|
[39c8fdb] | 791 | : "memory" |
---|
| 792 | ); |
---|
| 793 | } |
---|
| 794 | |
---|
[5e657e2] | 795 | static inline void arm_cp15_data_cache_test_and_clean(void) |
---|
[39c8fdb] | 796 | { |
---|
| 797 | ARM_SWITCH_REGISTERS; |
---|
| 798 | |
---|
[139ec149] | 799 | __asm__ volatile ( |
---|
[39c8fdb] | 800 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 801 | "1:\n" |
---|
| 802 | "mrc p15, 0, r15, c7, c10, 3\n" |
---|
| 803 | "bne 1b\n" |
---|
[39c8fdb] | 804 | ARM_SWITCH_BACK |
---|
| 805 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 806 | : |
---|
| 807 | : "memory" |
---|
[39c8fdb] | 808 | ); |
---|
| 809 | } |
---|
| 810 | |
---|
[76de8a8e] | 811 | /* In DDI0301H_arm1176jzfs_r0p7_trm |
---|
| 812 | * 'MCR p15, 0, <Rd>, c7, c14, 0' means |
---|
| 813 | * Clean and Invalidate Entire Data Cache |
---|
| 814 | */ |
---|
| 815 | static inline void arm_cp15_data_cache_clean_and_invalidate(void) |
---|
| 816 | { |
---|
| 817 | ARM_SWITCH_REGISTERS; |
---|
| 818 | |
---|
| 819 | uint32_t sbz = 0; |
---|
| 820 | |
---|
| 821 | __asm__ volatile ( |
---|
| 822 | ARM_SWITCH_TO_ARM |
---|
| 823 | "mcr p15, 0, %[sbz], c7, c14, 0\n" |
---|
| 824 | ARM_SWITCH_BACK |
---|
| 825 | : ARM_SWITCH_OUTPUT |
---|
| 826 | : [sbz] "r" (sbz) |
---|
| 827 | : "memory" |
---|
| 828 | ); |
---|
| 829 | |
---|
| 830 | } |
---|
| 831 | |
---|
[5e657e2] | 832 | static inline void arm_cp15_data_cache_clean_and_invalidate_line(const void *mva) |
---|
[39c8fdb] | 833 | { |
---|
| 834 | ARM_SWITCH_REGISTERS; |
---|
| 835 | |
---|
[5e657e2] | 836 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
[39c8fdb] | 837 | |
---|
[139ec149] | 838 | __asm__ volatile ( |
---|
[39c8fdb] | 839 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 840 | "mcr p15, 0, %[mva], c7, c14, 1\n" |
---|
[39c8fdb] | 841 | ARM_SWITCH_BACK |
---|
| 842 | : ARM_SWITCH_OUTPUT |
---|
| 843 | : [mva] "r" (mva) |
---|
[5e657e2] | 844 | : "memory" |
---|
[39c8fdb] | 845 | ); |
---|
| 846 | } |
---|
| 847 | |
---|
[5e657e2] | 848 | static inline void arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(uint32_t set_and_way) |
---|
[39c8fdb] | 849 | { |
---|
| 850 | ARM_SWITCH_REGISTERS; |
---|
| 851 | |
---|
[139ec149] | 852 | __asm__ volatile ( |
---|
[39c8fdb] | 853 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 854 | "mcr p15, 0, %[set_and_way], c7, c14, 2\n" |
---|
[39c8fdb] | 855 | ARM_SWITCH_BACK |
---|
| 856 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 857 | : [set_and_way] "r" (set_and_way) |
---|
| 858 | : "memory" |
---|
[39c8fdb] | 859 | ); |
---|
| 860 | } |
---|
| 861 | |
---|
[5e657e2] | 862 | static inline void arm_cp15_data_cache_test_and_clean_and_invalidate(void) |
---|
[39c8fdb] | 863 | { |
---|
| 864 | ARM_SWITCH_REGISTERS; |
---|
| 865 | |
---|
[139ec149] | 866 | __asm__ volatile ( |
---|
[39c8fdb] | 867 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 868 | "1:\n" |
---|
| 869 | "mrc p15, 0, r15, c7, c14, 3\n" |
---|
| 870 | "bne 1b\n" |
---|
[39c8fdb] | 871 | ARM_SWITCH_BACK |
---|
| 872 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 873 | : |
---|
| 874 | : "memory" |
---|
[39c8fdb] | 875 | ); |
---|
| 876 | } |
---|
| 877 | |
---|
[5e657e2] | 878 | /** @} */ |
---|
| 879 | |
---|
| 880 | static inline void arm_cp15_drain_write_buffer(void) |
---|
[39c8fdb] | 881 | { |
---|
| 882 | ARM_SWITCH_REGISTERS; |
---|
| 883 | uint32_t sbz = 0; |
---|
| 884 | |
---|
[139ec149] | 885 | __asm__ volatile ( |
---|
[39c8fdb] | 886 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 887 | "mcr p15, 0, %[sbz], c7, c10, 4\n" |
---|
[39c8fdb] | 888 | ARM_SWITCH_BACK |
---|
| 889 | : ARM_SWITCH_OUTPUT |
---|
| 890 | : [sbz] "r" (sbz) |
---|
[5e657e2] | 891 | : "memory" |
---|
[39c8fdb] | 892 | ); |
---|
| 893 | } |
---|
| 894 | |
---|
[5e657e2] | 895 | static inline void arm_cp15_wait_for_interrupt(void) |
---|
[39c8fdb] | 896 | { |
---|
| 897 | ARM_SWITCH_REGISTERS; |
---|
[5e657e2] | 898 | uint32_t sbz = 0; |
---|
[39c8fdb] | 899 | |
---|
[139ec149] | 900 | __asm__ volatile ( |
---|
[39c8fdb] | 901 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 902 | "mcr p15, 0, %[sbz], c7, c0, 4\n" |
---|
[39c8fdb] | 903 | ARM_SWITCH_BACK |
---|
| 904 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 905 | : [sbz] "r" (sbz) |
---|
| 906 | : "memory" |
---|
[39c8fdb] | 907 | ); |
---|
| 908 | } |
---|
| 909 | |
---|
[db42c079] | 910 | static inline uint32_t arm_cp15_get_multiprocessor_affinity(void) |
---|
| 911 | { |
---|
| 912 | ARM_SWITCH_REGISTERS; |
---|
| 913 | uint32_t mpidr; |
---|
| 914 | |
---|
| 915 | __asm__ volatile ( |
---|
| 916 | ARM_SWITCH_TO_ARM |
---|
| 917 | "mrc p15, 0, %[mpidr], c0, c0, 5\n" |
---|
| 918 | ARM_SWITCH_BACK |
---|
| 919 | : [mpidr] "=&r" (mpidr) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
| 920 | ); |
---|
| 921 | |
---|
| 922 | return mpidr & 0xff; |
---|
| 923 | } |
---|
| 924 | |
---|
| 925 | static inline uint32_t arm_cortex_a9_get_multiprocessor_cpu_id(void) |
---|
| 926 | { |
---|
| 927 | return arm_cp15_get_multiprocessor_affinity() & 0xff; |
---|
| 928 | } |
---|
| 929 | |
---|
| 930 | #define ARM_CORTEX_A9_ACTL_FW (1U << 0) |
---|
| 931 | #define ARM_CORTEX_A9_ACTL_L2_PREFETCH_HINT_ENABLE (1U << 1) |
---|
| 932 | #define ARM_CORTEX_A9_ACTL_L1_PREFETCH_ENABLE (1U << 2) |
---|
| 933 | #define ARM_CORTEX_A9_ACTL_WRITE_FULL_LINE_OF_ZEROS_MODE (1U << 3) |
---|
| 934 | #define ARM_CORTEX_A9_ACTL_SMP (1U << 6) |
---|
| 935 | #define ARM_CORTEX_A9_ACTL_EXCL (1U << 7) |
---|
| 936 | #define ARM_CORTEX_A9_ACTL_ALLOC_IN_ONE_WAY (1U << 8) |
---|
| 937 | #define ARM_CORTEX_A9_ACTL_PARITY_ON (1U << 9) |
---|
| 938 | |
---|
| 939 | static inline uint32_t arm_cp15_get_auxiliary_control(void) |
---|
| 940 | { |
---|
| 941 | ARM_SWITCH_REGISTERS; |
---|
| 942 | uint32_t val; |
---|
| 943 | |
---|
| 944 | __asm__ volatile ( |
---|
| 945 | ARM_SWITCH_TO_ARM |
---|
| 946 | "mrc p15, 0, %[val], c1, c0, 1\n" |
---|
| 947 | ARM_SWITCH_BACK |
---|
| 948 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
| 949 | ); |
---|
| 950 | |
---|
| 951 | return val; |
---|
| 952 | } |
---|
| 953 | |
---|
| 954 | static inline void arm_cp15_set_auxiliary_control(uint32_t val) |
---|
| 955 | { |
---|
| 956 | ARM_SWITCH_REGISTERS; |
---|
| 957 | |
---|
| 958 | __asm__ volatile ( |
---|
| 959 | ARM_SWITCH_TO_ARM |
---|
| 960 | "mcr p15, 0, %[val], c1, c0, 1\n" |
---|
| 961 | ARM_SWITCH_BACK |
---|
| 962 | : ARM_SWITCH_OUTPUT |
---|
| 963 | : [val] "r" (val) |
---|
| 964 | ); |
---|
| 965 | } |
---|
| 966 | |
---|
[9a037da9] | 967 | /* ID_PFR1, Processor Feature Register 1 */ |
---|
| 968 | |
---|
| 969 | static inline uint32_t arm_cp15_get_processor_feature_1(void) |
---|
| 970 | { |
---|
| 971 | ARM_SWITCH_REGISTERS; |
---|
| 972 | uint32_t val; |
---|
| 973 | |
---|
| 974 | __asm__ volatile ( |
---|
| 975 | ARM_SWITCH_TO_ARM |
---|
| 976 | "mrc p15, 0, %[val], c0, c1, 1\n" |
---|
| 977 | ARM_SWITCH_BACK |
---|
| 978 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
| 979 | ); |
---|
| 980 | |
---|
| 981 | return val; |
---|
| 982 | } |
---|
| 983 | |
---|
| 984 | /* VBAR, Vector Base Address Register, Security Extensions */ |
---|
| 985 | |
---|
| 986 | static inline void *arm_cp15_get_vector_base_address(void) |
---|
| 987 | { |
---|
| 988 | ARM_SWITCH_REGISTERS; |
---|
| 989 | void *base; |
---|
| 990 | |
---|
| 991 | __asm__ volatile ( |
---|
| 992 | ARM_SWITCH_TO_ARM |
---|
| 993 | "mrc p15, 0, %[base], c12, c0, 0\n" |
---|
| 994 | ARM_SWITCH_BACK |
---|
| 995 | : [base] "=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
| 996 | ); |
---|
| 997 | |
---|
| 998 | return base; |
---|
| 999 | } |
---|
| 1000 | |
---|
| 1001 | static inline void arm_cp15_set_vector_base_address(void *base) |
---|
| 1002 | { |
---|
| 1003 | ARM_SWITCH_REGISTERS; |
---|
| 1004 | |
---|
| 1005 | __asm__ volatile ( |
---|
| 1006 | ARM_SWITCH_TO_ARM |
---|
| 1007 | "mcr p15, 0, %[base], c12, c0, 0\n" |
---|
| 1008 | ARM_SWITCH_BACK |
---|
| 1009 | : ARM_SWITCH_OUTPUT |
---|
| 1010 | : [base] "r" (base) |
---|
| 1011 | ); |
---|
| 1012 | } |
---|
| 1013 | |
---|
[037e8ae5] | 1014 | /** |
---|
| 1015 | * @brief Sets the @a section_flags for the address range [@a begin, @a end). |
---|
| 1016 | * |
---|
| 1017 | * @return Previous section flags of the first modified entry. |
---|
| 1018 | */ |
---|
| 1019 | uint32_t arm_cp15_set_translation_table_entries( |
---|
| 1020 | const void *begin, |
---|
| 1021 | const void *end, |
---|
| 1022 | uint32_t section_flags |
---|
| 1023 | ); |
---|
| 1024 | |
---|
[88cf23f8] | 1025 | void arm_cp15_set_exception_handler( |
---|
| 1026 | Arm_symbolic_exception_name exception, |
---|
[33c98fd] | 1027 | void (*handler)(void) |
---|
[88cf23f8] | 1028 | ); |
---|
| 1029 | |
---|
[5e657e2] | 1030 | /** @} */ |
---|
[39c8fdb] | 1031 | |
---|
| 1032 | #ifdef __cplusplus |
---|
| 1033 | } |
---|
| 1034 | #endif /* __cplusplus */ |
---|
| 1035 | |
---|
| 1036 | #endif /* LIBCPU_SHARED_ARM_CP15_H */ |
---|