[39c8fdb] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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[5e657e2] | 4 | * @ingroup ScoreCPUARMCP15 |
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[39c8fdb] | 5 | * |
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| 6 | * @brief ARM co-processor 15 (CP15) API. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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[d2d02961] | 10 | * Copyright (c) 2009-2013 embedded brains GmbH. All rights reserved. |
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| 11 | * |
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| 12 | * embedded brains GmbH |
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| 13 | * Dornierstr. 4 |
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| 14 | * 82178 Puchheim |
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| 15 | * Germany |
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| 16 | * <info@embedded-brains.de> |
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[39c8fdb] | 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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| 20 | * http://www.rtems.com/license/LICENSE. |
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| 21 | */ |
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| 22 | |
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| 23 | #ifndef LIBCPU_SHARED_ARM_CP15_H |
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| 24 | #define LIBCPU_SHARED_ARM_CP15_H |
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| 25 | |
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| 26 | #include <rtems.h> |
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| 27 | |
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| 28 | #ifdef __cplusplus |
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| 29 | extern "C" { |
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| 30 | #endif /* __cplusplus */ |
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| 31 | |
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[5e657e2] | 32 | #define ARM_CP15_CACHE_PREPARE_MVA(mva) \ |
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| 33 | ((const void *) (((uint32_t) (mva)) & ~0x1fU)) |
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| 34 | |
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| 35 | #define ARM_CP15_TLB_PREPARE_MVA(mva) \ |
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| 36 | ((const void *) (((uint32_t) (mva)) & ~0x3fU)) |
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| 37 | |
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| 38 | /** |
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| 39 | * @defgroup ScoreCPUARMCP15 ARM Co-Processor 15 Support |
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| 40 | * |
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| 41 | * @ingroup ScoreCPUARM |
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| 42 | * |
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| 43 | * @brief ARM co-processor 15 (CP15) support. |
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| 44 | * |
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| 45 | * @{ |
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| 46 | */ |
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| 47 | |
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| 48 | /** |
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| 49 | * @name MMU Defines |
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| 50 | * |
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| 51 | * @{ |
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| 52 | */ |
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| 53 | |
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[39c8fdb] | 54 | #define ARM_MMU_SECT_BASE_SHIFT 20 |
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[5e657e2] | 55 | #define ARM_MMU_SECT_BASE_MASK (0xfffU << ARM_MMU_SECT_BASE_SHIFT) |
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[39c8fdb] | 56 | #define ARM_MMU_SECT_DOMAIN_SHIFT 5 |
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[5e657e2] | 57 | #define ARM_MMU_SECT_DOMAIN_MASK (0xfU << ARM_MMU_SECT_DOMAIN_SHIFT) |
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[39c8fdb] | 58 | #define ARM_MMU_SECT_AP_1 (1U << 11) |
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| 59 | #define ARM_MMU_SECT_AP_0 (1U << 10) |
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| 60 | #define ARM_MMU_SECT_AP_SHIFT 10 |
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[5e657e2] | 61 | #define ARM_MMU_SECT_AP_MASK (0x3U << ARM_MMU_SECT_AP_SHIFT) |
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[39c8fdb] | 62 | #define ARM_MMU_SECT_C (1U << 3) |
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| 63 | #define ARM_MMU_SECT_B (1U << 2) |
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| 64 | #define ARM_MMU_SECT_DEFAULT 0x12U |
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| 65 | #define ARM_MMU_SECT_GET_INDEX(mva) \ |
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| 66 | (((uint32_t) (mva)) >> ARM_MMU_SECT_BASE_SHIFT) |
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| 67 | #define ARM_MMU_SECT_MVA_ALIGN_UP(mva) \ |
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| 68 | ((1U << ARM_MMU_SECT_BASE_SHIFT) \ |
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| 69 | + ((((uint32_t) (mva) - 1U)) & ~((1U << ARM_MMU_SECT_BASE_SHIFT) - 1U))) |
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| 70 | |
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| 71 | #define ARM_MMU_TRANSLATION_TABLE_ENTRY_SIZE 4U |
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| 72 | #define ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT 4096U |
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| 73 | |
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[5e657e2] | 74 | /** @} */ |
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[39c8fdb] | 75 | |
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[5e657e2] | 76 | /** |
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| 77 | * @name Control Register Defines |
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| 78 | * |
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| 79 | * @{ |
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| 80 | */ |
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[39c8fdb] | 81 | |
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[5e657e2] | 82 | #define ARM_CP15_CTRL_L4 (1U << 15) |
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| 83 | #define ARM_CP15_CTRL_RR (1U << 14) |
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| 84 | #define ARM_CP15_CTRL_V (1U << 13) |
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| 85 | #define ARM_CP15_CTRL_I (1U << 12) |
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| 86 | #define ARM_CP15_CTRL_R (1U << 9) |
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| 87 | #define ARM_CP15_CTRL_S (1U << 8) |
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| 88 | #define ARM_CP15_CTRL_B (1U << 7) |
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| 89 | #define ARM_CP15_CTRL_C (1U << 2) |
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| 90 | #define ARM_CP15_CTRL_A (1U << 1) |
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| 91 | #define ARM_CP15_CTRL_M (1U << 0) |
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[39c8fdb] | 92 | |
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[5e657e2] | 93 | /** @} */ |
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| 94 | |
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| 95 | /** |
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| 96 | * @name Domain Access Control Defines |
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| 97 | * |
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| 98 | * @{ |
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| 99 | */ |
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| 100 | |
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| 101 | #define ARM_CP15_DAC_NO_ACCESS 0x0U |
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| 102 | #define ARM_CP15_DAC_CLIENT 0x1U |
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| 103 | #define ARM_CP15_DAC_MANAGER 0x3U |
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| 104 | #define ARM_CP15_DAC_DOMAIN(index, val) ((val) << (2 * index)) |
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| 105 | |
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| 106 | /** @} */ |
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| 107 | |
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| 108 | static inline uint32_t arm_cp15_get_id_code(void) |
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[39c8fdb] | 109 | { |
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| 110 | ARM_SWITCH_REGISTERS; |
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| 111 | uint32_t val; |
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| 112 | |
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[139ec149] | 113 | __asm__ volatile ( |
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[39c8fdb] | 114 | ARM_SWITCH_TO_ARM |
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[5e657e2] | 115 | "mrc p15, 0, %[val], c0, c0, 0\n" |
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[39c8fdb] | 116 | ARM_SWITCH_BACK |
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| 117 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 118 | ); |
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| 119 | |
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| 120 | return val; |
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| 121 | } |
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| 122 | |
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| 123 | static inline uint32_t arm_cp15_get_tcm_status(void) |
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| 124 | { |
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| 125 | ARM_SWITCH_REGISTERS; |
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| 126 | uint32_t val; |
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| 127 | |
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[139ec149] | 128 | __asm__ volatile ( |
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[39c8fdb] | 129 | ARM_SWITCH_TO_ARM |
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| 130 | "mrc p15, 0, %[val], c0, c0, 2\n" |
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| 131 | ARM_SWITCH_BACK |
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| 132 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 133 | ); |
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| 134 | |
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| 135 | return val; |
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| 136 | } |
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| 137 | |
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| 138 | static inline uint32_t arm_cp15_get_control(void) |
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| 139 | { |
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| 140 | ARM_SWITCH_REGISTERS; |
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| 141 | uint32_t val; |
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| 142 | |
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[139ec149] | 143 | __asm__ volatile ( |
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[39c8fdb] | 144 | ARM_SWITCH_TO_ARM |
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| 145 | "mrc p15, 0, %[val], c1, c0, 0\n" |
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| 146 | ARM_SWITCH_BACK |
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| 147 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 148 | ); |
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| 149 | |
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| 150 | return val; |
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| 151 | } |
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| 152 | |
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| 153 | static inline void arm_cp15_set_control(uint32_t val) |
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| 154 | { |
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| 155 | ARM_SWITCH_REGISTERS; |
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| 156 | |
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[139ec149] | 157 | __asm__ volatile ( |
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[39c8fdb] | 158 | ARM_SWITCH_TO_ARM |
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| 159 | "mcr p15, 0, %[val], c1, c0, 0\n" |
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| 160 | "nop\n" |
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| 161 | "nop\n" |
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| 162 | ARM_SWITCH_BACK |
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| 163 | : ARM_SWITCH_OUTPUT |
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| 164 | : [val] "r" (val) |
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| 165 | : "memory" |
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| 166 | ); |
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| 167 | } |
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| 168 | |
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[5e657e2] | 169 | /** |
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| 170 | * @name MMU Functions |
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| 171 | * |
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| 172 | * @{ |
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| 173 | */ |
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| 174 | |
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[544615d] | 175 | /** |
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| 176 | * @brief Disable the MMU. |
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| 177 | * |
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| 178 | * This function will clean and invalidate eight cache lines before and after |
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| 179 | * the current stack pointer. |
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| 180 | * |
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| 181 | * @param[in] cls The data cache line size. |
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| 182 | * |
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| 183 | * @return The current control register value. |
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| 184 | */ |
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| 185 | static inline uint32_t arm_cp15_mmu_disable(uint32_t cls) |
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| 186 | { |
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| 187 | ARM_SWITCH_REGISTERS; |
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| 188 | uint32_t ctrl; |
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| 189 | uint32_t tmp_0; |
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| 190 | uint32_t tmp_1; |
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| 191 | |
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| 192 | __asm__ volatile ( |
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| 193 | ARM_SWITCH_TO_ARM |
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| 194 | "mrc p15, 0, %[ctrl], c1, c0, 0\n" |
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| 195 | "bic %[tmp_0], %[ctrl], #1\n" |
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| 196 | "mcr p15, 0, %[tmp_0], c1, c0, 0\n" |
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| 197 | "nop\n" |
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| 198 | "nop\n" |
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| 199 | "mov %[tmp_1], sp\n" |
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| 200 | "rsb %[tmp_0], %[cls], #0\n" |
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| 201 | "and %[tmp_0], %[tmp_0], %[tmp_1]\n" |
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| 202 | "sub %[tmp_0], %[tmp_0], %[cls], asl #3\n" |
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| 203 | "add %[tmp_1], %[tmp_0], %[cls], asl #4\n" |
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| 204 | "1:\n" |
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| 205 | "mcr p15, 0, %[tmp_0], c7, c14, 1\n" |
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| 206 | "add %[tmp_0], %[tmp_0], %[cls]\n" |
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| 207 | "cmp %[tmp_1], %[tmp_0]\n" |
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| 208 | "bne 1b\n" |
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| 209 | ARM_SWITCH_BACK |
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| 210 | : [ctrl] "=&r" (ctrl), |
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| 211 | [tmp_0] "=&r" (tmp_0), |
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| 212 | [tmp_1] "=&r" (tmp_1) |
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| 213 | ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 214 | : [cls] "r" (cls) |
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| 215 | : "memory", "cc" |
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| 216 | ); |
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| 217 | |
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| 218 | return ctrl; |
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| 219 | } |
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| 220 | |
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[39c8fdb] | 221 | static inline uint32_t *arm_cp15_get_translation_table_base(void) |
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| 222 | { |
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| 223 | ARM_SWITCH_REGISTERS; |
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| 224 | uint32_t *base; |
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| 225 | |
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[139ec149] | 226 | __asm__ volatile ( |
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[39c8fdb] | 227 | ARM_SWITCH_TO_ARM |
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| 228 | "mrc p15, 0, %[base], c2, c0, 0\n" |
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| 229 | ARM_SWITCH_BACK |
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| 230 | : [base] "=&r" (base) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 231 | ); |
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| 232 | |
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| 233 | return base; |
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| 234 | } |
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| 235 | |
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| 236 | static inline void arm_cp15_set_translation_table_base(uint32_t *base) |
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| 237 | { |
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| 238 | ARM_SWITCH_REGISTERS; |
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| 239 | |
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[139ec149] | 240 | __asm__ volatile ( |
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[39c8fdb] | 241 | ARM_SWITCH_TO_ARM |
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| 242 | "mcr p15, 0, %[base], c2, c0, 0\n" |
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| 243 | ARM_SWITCH_BACK |
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| 244 | : ARM_SWITCH_OUTPUT |
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| 245 | : [base] "r" (base) |
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| 246 | ); |
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| 247 | } |
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| 248 | |
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| 249 | static inline uint32_t arm_cp15_get_domain_access_control(void) |
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| 250 | { |
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| 251 | ARM_SWITCH_REGISTERS; |
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| 252 | uint32_t val; |
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| 253 | |
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[139ec149] | 254 | __asm__ volatile ( |
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[39c8fdb] | 255 | ARM_SWITCH_TO_ARM |
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| 256 | "mrc p15, 0, %[val], c3, c0, 0\n" |
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| 257 | ARM_SWITCH_BACK |
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| 258 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 259 | ); |
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| 260 | |
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| 261 | return val; |
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| 262 | } |
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| 263 | |
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| 264 | static inline void arm_cp15_set_domain_access_control(uint32_t val) |
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| 265 | { |
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| 266 | ARM_SWITCH_REGISTERS; |
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| 267 | |
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[139ec149] | 268 | __asm__ volatile ( |
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[39c8fdb] | 269 | ARM_SWITCH_TO_ARM |
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| 270 | "mcr p15, 0, %[val], c3, c0, 0\n" |
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| 271 | ARM_SWITCH_BACK |
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| 272 | : ARM_SWITCH_OUTPUT |
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| 273 | : [val] "r" (val) |
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| 274 | ); |
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| 275 | } |
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| 276 | |
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| 277 | static inline uint32_t arm_cp15_get_data_fault_status(void) |
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| 278 | { |
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| 279 | ARM_SWITCH_REGISTERS; |
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| 280 | uint32_t val; |
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| 281 | |
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[139ec149] | 282 | __asm__ volatile ( |
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[39c8fdb] | 283 | ARM_SWITCH_TO_ARM |
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| 284 | "mrc p15, 0, %[val], c5, c0, 0\n" |
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| 285 | ARM_SWITCH_BACK |
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| 286 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 287 | ); |
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| 288 | |
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| 289 | return val; |
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| 290 | } |
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| 291 | |
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| 292 | static inline void arm_cp15_set_data_fault_status(uint32_t val) |
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| 293 | { |
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| 294 | ARM_SWITCH_REGISTERS; |
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| 295 | |
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[139ec149] | 296 | __asm__ volatile ( |
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[39c8fdb] | 297 | ARM_SWITCH_TO_ARM |
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| 298 | "mcr p15, 0, %[val], c5, c0, 0\n" |
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| 299 | ARM_SWITCH_BACK |
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| 300 | : ARM_SWITCH_OUTPUT |
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| 301 | : [val] "r" (val) |
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| 302 | ); |
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| 303 | } |
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| 304 | |
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| 305 | static inline uint32_t arm_cp15_get_instruction_fault_status(void) |
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| 306 | { |
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| 307 | ARM_SWITCH_REGISTERS; |
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| 308 | uint32_t val; |
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| 309 | |
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[139ec149] | 310 | __asm__ volatile ( |
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[39c8fdb] | 311 | ARM_SWITCH_TO_ARM |
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| 312 | "mrc p15, 0, %[val], c5, c0, 1\n" |
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| 313 | ARM_SWITCH_BACK |
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| 314 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 315 | ); |
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| 316 | |
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| 317 | return val; |
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| 318 | } |
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| 319 | |
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| 320 | static inline void arm_cp15_set_instruction_fault_status(uint32_t val) |
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| 321 | { |
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| 322 | ARM_SWITCH_REGISTERS; |
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| 323 | |
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[139ec149] | 324 | __asm__ volatile ( |
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[39c8fdb] | 325 | ARM_SWITCH_TO_ARM |
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| 326 | "mcr p15, 0, %[val], c5, c0, 1\n" |
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| 327 | ARM_SWITCH_BACK |
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| 328 | : ARM_SWITCH_OUTPUT |
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| 329 | : [val] "r" (val) |
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| 330 | ); |
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| 331 | } |
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| 332 | |
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| 333 | static inline void *arm_cp15_get_fault_address(void) |
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| 334 | { |
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| 335 | ARM_SWITCH_REGISTERS; |
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| 336 | void *mva; |
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| 337 | |
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[139ec149] | 338 | __asm__ volatile ( |
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[39c8fdb] | 339 | ARM_SWITCH_TO_ARM |
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| 340 | "mrc p15, 0, %[mva], c6, c0, 0\n" |
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| 341 | ARM_SWITCH_BACK |
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| 342 | : [mva] "=&r" (mva) ARM_SWITCH_ADDITIONAL_OUTPUT |
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| 343 | ); |
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| 344 | |
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| 345 | return mva; |
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| 346 | } |
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| 347 | |
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| 348 | static inline void arm_cp15_set_fault_address(const void *mva) |
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| 349 | { |
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| 350 | ARM_SWITCH_REGISTERS; |
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| 351 | |
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[139ec149] | 352 | __asm__ volatile ( |
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[39c8fdb] | 353 | ARM_SWITCH_TO_ARM |
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| 354 | "mcr p15, 0, %[mva], c6, c0, 0\n" |
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| 355 | ARM_SWITCH_BACK |
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| 356 | : ARM_SWITCH_OUTPUT |
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| 357 | : [mva] "r" (mva) |
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| 358 | ); |
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| 359 | } |
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| 360 | |
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[5e657e2] | 361 | static inline void arm_cp15_tlb_invalidate(void) |
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[39c8fdb] | 362 | { |
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| 363 | ARM_SWITCH_REGISTERS; |
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| 364 | uint32_t sbz = 0; |
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| 365 | |
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[139ec149] | 366 | __asm__ volatile ( |
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[39c8fdb] | 367 | ARM_SWITCH_TO_ARM |
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[5e657e2] | 368 | "mcr p15, 0, %[sbz], c8, c7, 0\n" |
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[39c8fdb] | 369 | ARM_SWITCH_BACK |
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| 370 | : ARM_SWITCH_OUTPUT |
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| 371 | : [sbz] "r" (sbz) |
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| 372 | ); |
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| 373 | } |
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| 374 | |
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[5e657e2] | 375 | static inline void arm_cp15_tlb_invalidate_entry(const void *mva) |
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| 376 | { |
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| 377 | ARM_SWITCH_REGISTERS; |
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| 378 | |
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| 379 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
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| 380 | |
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[139ec149] | 381 | __asm__ volatile ( |
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[5e657e2] | 382 | ARM_SWITCH_TO_ARM |
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| 383 | "mcr p15, 0, %[mva], c8, c7, 1\n" |
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| 384 | ARM_SWITCH_BACK |
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| 385 | : ARM_SWITCH_OUTPUT |
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| 386 | : [mva] "r" (mva) |
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| 387 | ); |
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| 388 | } |
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| 389 | |
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| 390 | static inline void arm_cp15_tlb_instruction_invalidate(void) |
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[39c8fdb] | 391 | { |
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| 392 | ARM_SWITCH_REGISTERS; |
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| 393 | uint32_t sbz = 0; |
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| 394 | |
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[139ec149] | 395 | __asm__ volatile ( |
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[39c8fdb] | 396 | ARM_SWITCH_TO_ARM |
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[5e657e2] | 397 | "mcr p15, 0, %[sbz], c8, c5, 0\n" |
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[39c8fdb] | 398 | ARM_SWITCH_BACK |
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| 399 | : ARM_SWITCH_OUTPUT |
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| 400 | : [sbz] "r" (sbz) |
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| 401 | ); |
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| 402 | } |
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| 403 | |
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[5e657e2] | 404 | static inline void arm_cp15_tlb_instruction_invalidate_entry(const void *mva) |
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[39c8fdb] | 405 | { |
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| 406 | ARM_SWITCH_REGISTERS; |
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| 407 | |
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[5e657e2] | 408 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
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[39c8fdb] | 409 | |
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[139ec149] | 410 | __asm__ volatile ( |
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[39c8fdb] | 411 | ARM_SWITCH_TO_ARM |
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[5e657e2] | 412 | "mcr p15, 0, %[mva], c8, c5, 1\n" |
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[39c8fdb] | 413 | ARM_SWITCH_BACK |
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| 414 | : ARM_SWITCH_OUTPUT |
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| 415 | : [mva] "r" (mva) |
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| 416 | ); |
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| 417 | } |
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| 418 | |
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[5e657e2] | 419 | static inline void arm_cp15_tlb_data_invalidate(void) |
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[39c8fdb] | 420 | { |
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| 421 | ARM_SWITCH_REGISTERS; |
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[5e657e2] | 422 | uint32_t sbz = 0; |
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[39c8fdb] | 423 | |
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[139ec149] | 424 | __asm__ volatile ( |
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[39c8fdb] | 425 | ARM_SWITCH_TO_ARM |
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[5e657e2] | 426 | "mcr p15, 0, %[sbz], c8, c6, 0\n" |
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[39c8fdb] | 427 | ARM_SWITCH_BACK |
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| 428 | : ARM_SWITCH_OUTPUT |
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[5e657e2] | 429 | : [sbz] "r" (sbz) |
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[39c8fdb] | 430 | ); |
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| 431 | } |
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| 432 | |
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[5e657e2] | 433 | static inline void arm_cp15_tlb_data_invalidate_entry(const void *mva) |
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[39c8fdb] | 434 | { |
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| 435 | ARM_SWITCH_REGISTERS; |
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| 436 | |
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[5e657e2] | 437 | mva = ARM_CP15_TLB_PREPARE_MVA(mva); |
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[39c8fdb] | 438 | |
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[139ec149] | 439 | __asm__ volatile ( |
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[39c8fdb] | 440 | ARM_SWITCH_TO_ARM |
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[5e657e2] | 441 | "mcr p15, 0, %[mva], c8, c6, 1\n" |
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[39c8fdb] | 442 | ARM_SWITCH_BACK |
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| 443 | : ARM_SWITCH_OUTPUT |
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| 444 | : [mva] "r" (mva) |
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| 445 | ); |
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| 446 | } |
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| 447 | |
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[5e657e2] | 448 | static inline void arm_cp15_tlb_lockdown_entry(const void *mva) |
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[39c8fdb] | 449 | { |
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[5e657e2] | 450 | uint32_t arm_switch_reg; |
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[39c8fdb] | 451 | |
---|
[139ec149] | 452 | __asm__ volatile ( |
---|
[39c8fdb] | 453 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 454 | "add %[arm_switch_reg], pc, #16\n" |
---|
| 455 | "mcr p15, 0, %[arm_switch_reg], c7, c13, 1\n" |
---|
| 456 | "mcr p15, 0, %[mva], c8, c7, 1\n" |
---|
| 457 | "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
| 458 | "orr %[arm_switch_reg], #0x1\n" |
---|
| 459 | "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
| 460 | "ldr %[mva], [%[mva]]\n" |
---|
| 461 | "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
| 462 | "bic %[arm_switch_reg], #0x1\n" |
---|
| 463 | "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" |
---|
[39c8fdb] | 464 | ARM_SWITCH_BACK |
---|
[5e657e2] | 465 | : [mva] "=r" (mva), [arm_switch_reg] "=&r" (arm_switch_reg) |
---|
| 466 | : "[mva]" (mva) |
---|
[39c8fdb] | 467 | ); |
---|
| 468 | } |
---|
| 469 | |
---|
[5e657e2] | 470 | /** @} */ |
---|
| 471 | |
---|
| 472 | /** |
---|
| 473 | * @name Cache Functions |
---|
| 474 | * |
---|
| 475 | * @{ |
---|
| 476 | */ |
---|
| 477 | |
---|
| 478 | static inline uint32_t arm_cp15_get_cache_type(void) |
---|
[39c8fdb] | 479 | { |
---|
| 480 | ARM_SWITCH_REGISTERS; |
---|
[5e657e2] | 481 | uint32_t val; |
---|
[39c8fdb] | 482 | |
---|
[139ec149] | 483 | __asm__ volatile ( |
---|
[5e657e2] | 484 | ARM_SWITCH_TO_ARM |
---|
| 485 | "mrc p15, 0, %[val], c0, c0, 1\n" |
---|
| 486 | ARM_SWITCH_BACK |
---|
| 487 | : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT |
---|
| 488 | ); |
---|
| 489 | |
---|
| 490 | return val; |
---|
| 491 | } |
---|
| 492 | |
---|
[d2d02961] | 493 | static inline uint32_t arm_cp15_get_min_cache_line_size(void) |
---|
| 494 | { |
---|
| 495 | uint32_t mcls = 0; |
---|
| 496 | uint32_t ct = arm_cp15_get_cache_type(); |
---|
| 497 | uint32_t format = (ct >> 29) & 0x7U; |
---|
| 498 | |
---|
| 499 | if (format == 0x4) { |
---|
| 500 | mcls = (1U << (ct & 0xf)) * 4; |
---|
| 501 | } else if (format == 0x0) { |
---|
| 502 | uint32_t mask = (1U << 12) - 1; |
---|
| 503 | uint32_t dcls = (ct >> 12) & mask; |
---|
| 504 | uint32_t icls = ct & mask; |
---|
| 505 | |
---|
| 506 | mcls = dcls <= icls ? dcls : icls; |
---|
| 507 | } |
---|
| 508 | |
---|
| 509 | return mcls; |
---|
| 510 | } |
---|
| 511 | |
---|
[5e657e2] | 512 | static inline void arm_cp15_cache_invalidate(void) |
---|
| 513 | { |
---|
| 514 | ARM_SWITCH_REGISTERS; |
---|
| 515 | uint32_t sbz = 0; |
---|
[39c8fdb] | 516 | |
---|
[139ec149] | 517 | __asm__ volatile ( |
---|
[39c8fdb] | 518 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 519 | "mcr p15, 0, %[sbz], c7, c7, 0\n" |
---|
[39c8fdb] | 520 | ARM_SWITCH_BACK |
---|
| 521 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 522 | : [sbz] "r" (sbz) |
---|
[39c8fdb] | 523 | : "memory" |
---|
| 524 | ); |
---|
| 525 | } |
---|
| 526 | |
---|
[5e657e2] | 527 | static inline void arm_cp15_instruction_cache_invalidate(void) |
---|
[39c8fdb] | 528 | { |
---|
| 529 | ARM_SWITCH_REGISTERS; |
---|
[5e657e2] | 530 | uint32_t sbz = 0; |
---|
[39c8fdb] | 531 | |
---|
[139ec149] | 532 | __asm__ volatile ( |
---|
[39c8fdb] | 533 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 534 | "mcr p15, 0, %[sbz], c7, c5, 0\n" |
---|
[39c8fdb] | 535 | ARM_SWITCH_BACK |
---|
| 536 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 537 | : [sbz] "r" (sbz) |
---|
[39c8fdb] | 538 | : "memory" |
---|
| 539 | ); |
---|
| 540 | } |
---|
| 541 | |
---|
[5e657e2] | 542 | static inline void arm_cp15_instruction_cache_invalidate_line(const void *mva) |
---|
[39c8fdb] | 543 | { |
---|
| 544 | ARM_SWITCH_REGISTERS; |
---|
| 545 | |
---|
| 546 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
| 547 | |
---|
[139ec149] | 548 | __asm__ volatile ( |
---|
[39c8fdb] | 549 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 550 | "mcr p15, 0, %[mva], c7, c5, 1\n" |
---|
[39c8fdb] | 551 | ARM_SWITCH_BACK |
---|
| 552 | : ARM_SWITCH_OUTPUT |
---|
| 553 | : [mva] "r" (mva) |
---|
| 554 | : "memory" |
---|
| 555 | ); |
---|
| 556 | } |
---|
| 557 | |
---|
[5e657e2] | 558 | static inline void arm_cp15_instruction_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) |
---|
[39c8fdb] | 559 | { |
---|
| 560 | ARM_SWITCH_REGISTERS; |
---|
| 561 | |
---|
[139ec149] | 562 | __asm__ volatile ( |
---|
[39c8fdb] | 563 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 564 | "mcr p15, 0, %[set_and_way], c7, c5, 2\n" |
---|
[39c8fdb] | 565 | ARM_SWITCH_BACK |
---|
| 566 | : ARM_SWITCH_OUTPUT |
---|
| 567 | : [set_and_way] "r" (set_and_way) |
---|
| 568 | : "memory" |
---|
| 569 | ); |
---|
| 570 | } |
---|
| 571 | |
---|
[5e657e2] | 572 | static inline void arm_cp15_instruction_cache_prefetch_line(const void *mva) |
---|
[39c8fdb] | 573 | { |
---|
| 574 | ARM_SWITCH_REGISTERS; |
---|
| 575 | |
---|
[5e657e2] | 576 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
| 577 | |
---|
[139ec149] | 578 | __asm__ volatile ( |
---|
[39c8fdb] | 579 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 580 | "mcr p15, 0, %[mva], c7, c13, 1\n" |
---|
[39c8fdb] | 581 | ARM_SWITCH_BACK |
---|
| 582 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 583 | : [mva] "r" (mva) |
---|
[39c8fdb] | 584 | ); |
---|
| 585 | } |
---|
| 586 | |
---|
[5e657e2] | 587 | static inline void arm_cp15_data_cache_invalidate(void) |
---|
[39c8fdb] | 588 | { |
---|
| 589 | ARM_SWITCH_REGISTERS; |
---|
[5e657e2] | 590 | uint32_t sbz = 0; |
---|
[39c8fdb] | 591 | |
---|
[139ec149] | 592 | __asm__ volatile ( |
---|
[39c8fdb] | 593 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 594 | "mcr p15, 0, %[sbz], c7, c6, 0\n" |
---|
[39c8fdb] | 595 | ARM_SWITCH_BACK |
---|
| 596 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 597 | : [sbz] "r" (sbz) |
---|
[39c8fdb] | 598 | : "memory" |
---|
| 599 | ); |
---|
| 600 | } |
---|
| 601 | |
---|
[5e657e2] | 602 | static inline void arm_cp15_data_cache_invalidate_line(const void *mva) |
---|
[39c8fdb] | 603 | { |
---|
| 604 | ARM_SWITCH_REGISTERS; |
---|
| 605 | |
---|
[5e657e2] | 606 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
| 607 | |
---|
[139ec149] | 608 | __asm__ volatile ( |
---|
[39c8fdb] | 609 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 610 | "mcr p15, 0, %[mva], c7, c6, 1\n" |
---|
[39c8fdb] | 611 | ARM_SWITCH_BACK |
---|
| 612 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 613 | : [mva] "r" (mva) |
---|
[39c8fdb] | 614 | : "memory" |
---|
| 615 | ); |
---|
| 616 | } |
---|
| 617 | |
---|
[5e657e2] | 618 | static inline void arm_cp15_data_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) |
---|
[39c8fdb] | 619 | { |
---|
| 620 | ARM_SWITCH_REGISTERS; |
---|
| 621 | |
---|
[139ec149] | 622 | __asm__ volatile ( |
---|
[39c8fdb] | 623 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 624 | "mcr p15, 0, %[set_and_way], c7, c6, 2\n" |
---|
[39c8fdb] | 625 | ARM_SWITCH_BACK |
---|
| 626 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 627 | : [set_and_way] "r" (set_and_way) |
---|
[39c8fdb] | 628 | : "memory" |
---|
| 629 | ); |
---|
| 630 | } |
---|
| 631 | |
---|
[5e657e2] | 632 | static inline void arm_cp15_data_cache_clean_line(const void *mva) |
---|
[39c8fdb] | 633 | { |
---|
| 634 | ARM_SWITCH_REGISTERS; |
---|
[5e657e2] | 635 | |
---|
| 636 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
[39c8fdb] | 637 | |
---|
[139ec149] | 638 | __asm__ volatile ( |
---|
[39c8fdb] | 639 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 640 | "mcr p15, 0, %[mva], c7, c10, 1\n" |
---|
[39c8fdb] | 641 | ARM_SWITCH_BACK |
---|
| 642 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 643 | : [mva] "r" (mva) |
---|
[39c8fdb] | 644 | : "memory" |
---|
| 645 | ); |
---|
| 646 | } |
---|
| 647 | |
---|
[5e657e2] | 648 | static inline void arm_cp15_data_cache_clean_line_by_set_and_way(uint32_t set_and_way) |
---|
[39c8fdb] | 649 | { |
---|
| 650 | ARM_SWITCH_REGISTERS; |
---|
| 651 | |
---|
[139ec149] | 652 | __asm__ volatile ( |
---|
[39c8fdb] | 653 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 654 | "mcr p15, 0, %[set_and_way], c7, c10, 2\n" |
---|
[39c8fdb] | 655 | ARM_SWITCH_BACK |
---|
| 656 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 657 | : [set_and_way] "r" (set_and_way) |
---|
[39c8fdb] | 658 | : "memory" |
---|
| 659 | ); |
---|
| 660 | } |
---|
| 661 | |
---|
[5e657e2] | 662 | static inline void arm_cp15_data_cache_test_and_clean(void) |
---|
[39c8fdb] | 663 | { |
---|
| 664 | ARM_SWITCH_REGISTERS; |
---|
| 665 | |
---|
[139ec149] | 666 | __asm__ volatile ( |
---|
[39c8fdb] | 667 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 668 | "1:\n" |
---|
| 669 | "mrc p15, 0, r15, c7, c10, 3\n" |
---|
| 670 | "bne 1b\n" |
---|
[39c8fdb] | 671 | ARM_SWITCH_BACK |
---|
| 672 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 673 | : |
---|
| 674 | : "memory" |
---|
[39c8fdb] | 675 | ); |
---|
| 676 | } |
---|
| 677 | |
---|
[76de8a8e] | 678 | /* In DDI0301H_arm1176jzfs_r0p7_trm |
---|
| 679 | * 'MCR p15, 0, <Rd>, c7, c14, 0' means |
---|
| 680 | * Clean and Invalidate Entire Data Cache |
---|
| 681 | */ |
---|
| 682 | static inline void arm_cp15_data_cache_clean_and_invalidate(void) |
---|
| 683 | { |
---|
| 684 | ARM_SWITCH_REGISTERS; |
---|
| 685 | |
---|
| 686 | uint32_t sbz = 0; |
---|
| 687 | |
---|
| 688 | __asm__ volatile ( |
---|
| 689 | ARM_SWITCH_TO_ARM |
---|
| 690 | "mcr p15, 0, %[sbz], c7, c14, 0\n" |
---|
| 691 | ARM_SWITCH_BACK |
---|
| 692 | : ARM_SWITCH_OUTPUT |
---|
| 693 | : [sbz] "r" (sbz) |
---|
| 694 | : "memory" |
---|
| 695 | ); |
---|
| 696 | |
---|
| 697 | } |
---|
| 698 | |
---|
[5e657e2] | 699 | static inline void arm_cp15_data_cache_clean_and_invalidate_line(const void *mva) |
---|
[39c8fdb] | 700 | { |
---|
| 701 | ARM_SWITCH_REGISTERS; |
---|
| 702 | |
---|
[5e657e2] | 703 | mva = ARM_CP15_CACHE_PREPARE_MVA(mva); |
---|
[39c8fdb] | 704 | |
---|
[139ec149] | 705 | __asm__ volatile ( |
---|
[39c8fdb] | 706 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 707 | "mcr p15, 0, %[mva], c7, c14, 1\n" |
---|
[39c8fdb] | 708 | ARM_SWITCH_BACK |
---|
| 709 | : ARM_SWITCH_OUTPUT |
---|
| 710 | : [mva] "r" (mva) |
---|
[5e657e2] | 711 | : "memory" |
---|
[39c8fdb] | 712 | ); |
---|
| 713 | } |
---|
| 714 | |
---|
[5e657e2] | 715 | static inline void arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(uint32_t set_and_way) |
---|
[39c8fdb] | 716 | { |
---|
| 717 | ARM_SWITCH_REGISTERS; |
---|
| 718 | |
---|
[139ec149] | 719 | __asm__ volatile ( |
---|
[39c8fdb] | 720 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 721 | "mcr p15, 0, %[set_and_way], c7, c14, 2\n" |
---|
[39c8fdb] | 722 | ARM_SWITCH_BACK |
---|
| 723 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 724 | : [set_and_way] "r" (set_and_way) |
---|
| 725 | : "memory" |
---|
[39c8fdb] | 726 | ); |
---|
| 727 | } |
---|
| 728 | |
---|
[5e657e2] | 729 | static inline void arm_cp15_data_cache_test_and_clean_and_invalidate(void) |
---|
[39c8fdb] | 730 | { |
---|
| 731 | ARM_SWITCH_REGISTERS; |
---|
| 732 | |
---|
[139ec149] | 733 | __asm__ volatile ( |
---|
[39c8fdb] | 734 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 735 | "1:\n" |
---|
| 736 | "mrc p15, 0, r15, c7, c14, 3\n" |
---|
| 737 | "bne 1b\n" |
---|
[39c8fdb] | 738 | ARM_SWITCH_BACK |
---|
| 739 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 740 | : |
---|
| 741 | : "memory" |
---|
[39c8fdb] | 742 | ); |
---|
| 743 | } |
---|
| 744 | |
---|
[5e657e2] | 745 | /** @} */ |
---|
| 746 | |
---|
| 747 | static inline void arm_cp15_drain_write_buffer(void) |
---|
[39c8fdb] | 748 | { |
---|
| 749 | ARM_SWITCH_REGISTERS; |
---|
| 750 | uint32_t sbz = 0; |
---|
| 751 | |
---|
[139ec149] | 752 | __asm__ volatile ( |
---|
[39c8fdb] | 753 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 754 | "mcr p15, 0, %[sbz], c7, c10, 4\n" |
---|
[39c8fdb] | 755 | ARM_SWITCH_BACK |
---|
| 756 | : ARM_SWITCH_OUTPUT |
---|
| 757 | : [sbz] "r" (sbz) |
---|
[5e657e2] | 758 | : "memory" |
---|
[39c8fdb] | 759 | ); |
---|
| 760 | } |
---|
| 761 | |
---|
[5e657e2] | 762 | static inline void arm_cp15_wait_for_interrupt(void) |
---|
[39c8fdb] | 763 | { |
---|
| 764 | ARM_SWITCH_REGISTERS; |
---|
[5e657e2] | 765 | uint32_t sbz = 0; |
---|
[39c8fdb] | 766 | |
---|
[139ec149] | 767 | __asm__ volatile ( |
---|
[39c8fdb] | 768 | ARM_SWITCH_TO_ARM |
---|
[5e657e2] | 769 | "mcr p15, 0, %[sbz], c7, c0, 4\n" |
---|
[39c8fdb] | 770 | ARM_SWITCH_BACK |
---|
| 771 | : ARM_SWITCH_OUTPUT |
---|
[5e657e2] | 772 | : [sbz] "r" (sbz) |
---|
| 773 | : "memory" |
---|
[39c8fdb] | 774 | ); |
---|
| 775 | } |
---|
| 776 | |
---|
[5e657e2] | 777 | /** @} */ |
---|
[39c8fdb] | 778 | |
---|
| 779 | #ifdef __cplusplus |
---|
| 780 | } |
---|
| 781 | #endif /* __cplusplus */ |
---|
| 782 | |
---|
| 783 | #endif /* LIBCPU_SHARED_ARM_CP15_H */ |
---|