source: rtems/c/src/lib/libcpu/arm/shared/include/am335x.h @ b51842b

4.115
Last change on this file since b51842b was b51842b, checked in by Ben Gras <beng@…>, on 11/03/14 at 18:52:03

Add some generic ARM am335x and omap definitions
  • Property mode set to 100644
File size: 10.1 KB
Line 
1/*
2 * Copyright (c) 2012 Claas Ziemke. All rights reserved.
3 *
4 *  Claas Ziemke
5 *  Kernerstrasse 11
6 *  70182 Stuttgart
7 *  Germany
8 *  <claas.ziemke@gmx.net>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 *
14 * Modified by Ben Gras <beng@shrike-systems.com> to add lots
15 * of beagleboard/beaglebone definitions, delete lpc32xx specific
16 * ones, and merge with some other header files.
17 */
18
19/* Interrupt controller memory map */
20#define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */
21
22/* Interrupt controller memory map */
23#define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */
24
25#define AM335X_INT_EMUINT             0
26    /* Emulation interrupt (EMUICINTR) */
27#define AM335X_INT_COMMTX             1
28    /* CortexA8 COMMTX */
29#define AM335X_INT_COMMRX             2
30    /* CortexA8 COMMRX */
31#define AM335X_INT_BENCH              3
32    /* CortexA8 NPMUIRQ */
33#define AM335X_INT_ELM_IRQ            4
34    /* Sinterrupt (Error location process completion) */
35#define AM335X_INT_NMI                7
36    /* nmi_int */
37#define AM335X_INT_L3DEBUG            9
38    /* l3_FlagMux_top_FlagOut1 */
39#define AM335X_INT_L3APPINT           10
40    /* l3_FlagMux_top_FlagOut0  */
41#define AM335X_INT_PRCMINT            11
42    /* irq_mpu */
43#define AM335X_INT_EDMACOMPINT        12
44    /* tpcc_int_pend_po0 */
45#define AM335X_INT_EDMAMPERR          13
46    /* tpcc_mpint_pend_po */
47#define AM335X_INT_EDMAERRINT         14
48    /* tpcc_errint_pend_po */
49#define AM335X_INT_ADC_TSC_GENINT     16
50    /* gen_intr_pend */
51#define AM335X_INT_USBSSINT           17
52    /* usbss_intr_pend */
53#define AM335X_INT_USB0               18
54    /* usb0_intr_pend */
55#define AM335X_INT_USB1               19
56    /* usb1_intr_pend */
57#define AM335X_INT_PRUSS1_EVTOUT0     20
58    /* pr1_host_intr0_intr_pend */
59#define AM335X_INT_PRUSS1_EVTOUT1     21
60    /* pr1_host_intr1_intr_pend */
61#define AM335X_INT_PRUSS1_EVTOUT2     22
62    /* pr1_host_intr2_intr_pend */
63#define AM335X_INT_PRUSS1_EVTOUT3     23
64    /* pr1_host_intr3_intr_pend */
65#define AM335X_INT_PRUSS1_EVTOUT4     24
66    /* pr1_host_intr4_intr_pend */
67#define AM335X_INT_PRUSS1_EVTOUT5     25
68    /* pr1_host_intr5_intr_pend */
69#define AM335X_INT_PRUSS1_EVTOUT6     26
70    /* pr1_host_intr6_intr_pend */
71#define AM335X_INT_PRUSS1_EVTOUT7     27
72    /* pr1_host_intr7_intr_pend */
73#define AM335X_INT_MMCSD1INT          28
74    /* MMCSD1  SINTERRUPTN */
75#define AM335X_INT_MMCSD2INT          29
76    /* MMCSD2  SINTERRUPT */
77#define AM335X_INT_I2C2INT            30
78    /* I2C2  POINTRPEND */
79#define AM335X_INT_eCAP0INT           31
80    /* ecap_intr_intr_pend */
81#define AM335X_INT_GPIOINT2A          32
82    /* GPIO 2  POINTRPEND1 */
83#define AM335X_INT_GPIOINT2B          33
84    /* GPIO 2  POINTRPEND2 */
85#define AM335X_INT_USBWAKEUP          34
86    /* USBSS  slv0p_Swakeup */
87#define AM335X_INT_LCDCINT            36
88    /* LCDC  lcd_irq */
89#define AM335X_INT_GFXINT             37
90    /* SGX530  THALIAIRQ */
91#define AM335X_INT_ePWM2INT           39
92    /* (PWM Subsystem)  epwm_intr_intr_pend */
93#define AM335X_INT_3PGSWRXTHR0        40
94    /* (Ethernet)  c0_rx_thresh_pend (RX_THRESH_PULSE) */
95#define AM335X_INT_3PGSWRXINT0        41
96    /* CPSW (Ethernet)  c0_rx_pend */
97#define AM335X_INT_3PGSWTXINT0        42
98    /* CPSW (Ethernet)  c0_tx_pend */
99#define AM335X_INT_3PGSWMISC0         43
100    /* CPSW (Ethernet)  c0_misc_pend */
101#define AM335X_INT_UART3INT           44
102    /* UART3  niq */
103#define AM335X_INT_UART4INT           45
104    /* UART4  niq */
105#define AM335X_INT_UART5INT           46
106    /* UART5  niq */
107#define AM335X_INT_eCAP1INT           47
108    /* (PWM Subsystem)  ecap_intr_intr_pend */
109#define AM335X_INT_DCAN0_INT0         52
110    /* DCAN0  dcan_intr0_intr_pend */
111#define AM335X_INT_DCAN0_INT1         53
112    /* DCAN0  dcan_intr1_intr_pend */
113#define AM335X_INT_DCAN0_PARITY       54
114    /* DCAN0  dcan_uerr_intr_pend */
115#define AM335X_INT_DCAN1_INT0         55
116    /* DCAN1  dcan_intr0_intr_pend */
117#define AM335X_INT_DCAN1_INT1         56
118    /* DCAN1  dcan_intr1_intr_pend */
119#define AM335X_INT_DCAN1_PARITY       57
120    /* DCAN1  dcan_uerr_intr_pend */
121#define AM335X_INT_ePWM0_TZINT        58
122    /* eHRPWM0 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
123#define AM335X_INT_ePWM1_TZINT        59
124    /* eHRPWM1 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
125#define AM335X_INT_ePWM2_TZINT        60
126    /* eHRPWM2 TZ interrupt (PWM  epwm_tz_intr_pend Subsystem) */
127#define AM335X_INT_eCAP2INT           61
128    /* eCAP2 (PWM Subsystem)  ecap_intr_intr_pend */
129#define AM335X_INT_GPIOINT3A          62
130    /* GPIO 3  POINTRPEND1 */
131#define AM335X_INT_GPIOINT3B          63
132    /* GPIO 3  POINTRPEND2 */
133#define AM335X_INT_MMCSD0INT          64
134    /* MMCSD0  SINTERRUPTN */
135#define AM335X_INT_SPI0INT            65
136    /* McSPI0  SINTERRUPTN */
137#define AM335X_INT_TINT0              66
138    /* Timer0  POINTR_PEND */
139#define AM335X_INT_TINT1_1MS          67
140    /* DMTIMER_1ms  POINTR_PEND */
141#define AM335X_INT_TINT2              68
142    /* DMTIMER2  POINTR_PEND */
143#define AM335X_INT_TINT3              69
144    /* DMTIMER3  POINTR_PEND */
145#define AM335X_INT_I2C0INT            70
146    /* I2C0  POINTRPEND */
147#define AM335X_INT_I2C1INT            71
148    /* I2C1  POINTRPEND */
149#define AM335X_INT_UART0INT           72
150    /* UART0  niq */
151#define AM335X_INT_UART1INT           73
152    /* UART1  niq */
153#define AM335X_INT_UART2INT           74
154    /* UART2  niq */
155#define AM335X_INT_RTCINT             75
156    /* RTC  timer_intr_pend */
157#define AM335X_INT_RTCALARMINT        76
158    /* RTC  alarm_intr_pend */
159#define AM335X_INT_MBINT0             77
160    /* Mailbox0 (mail_u0_irq)  initiator_sinterrupt_q_n */
161#define AM335X_INT_M3_TXEV            78
162    /* Wake M3 Subsystem  TXEV */
163#define AM335X_INT_eQEP0INT           79
164    /* eQEP0 (PWM Subsystem)  eqep_intr_intr_pend */
165#define AM335X_INT_MCATXINT0          80
166    /* McASP0  mcasp_x_intr_pend */
167#define AM335X_INT_MCARXINT0          81
168    /* McASP0  mcasp_r_intr_pend */
169#define AM335X_INT_MCATXINT1          82
170    /* McASP1  mcasp_x_intr_pend */
171#define AM335X_INT_MCARXINT1          83
172    /* McASP1  mcasp_r_intr_pend */
173#define AM335X_INT_ePWM0INT           86
174    /* (PWM Subsystem)  epwm_intr_intr_pend */
175#define AM335X_INT_ePWM1INT           87
176    /* (PWM Subsystem)  epwm_intr_intr_pend */
177#define AM335X_INT_eQEP1INT           88
178    /* (PWM Subsystem)  eqep_intr_intr_pend */
179#define AM335X_INT_eQEP2INT           89
180    /* (PWM Subsystem)  eqep_intr_intr_pend */
181#define AM335X_INT_DMA_INTR_PIN2      90
182    /* External DMA/Interrupt Pin2  */
183#define AM335X_INT_WDT1INT            91
184    /* (Public Watchdog) WDTIMER1 PO_INT_PEND */
185#define AM335X_INT_TINT4              92
186    /* DMTIMER4  POINTR_PEN */
187#define AM335X_INT_TINT5              93
188    /* DMTIMER5  POINTR_PEN */
189#define AM335X_INT_TINT6              94
190    /* DMTIMER6  POINTR_PEND */
191#define AM335X_INT_TINT7              95
192    /* DMTIMER7  POINTR_PEND */
193#define AM335X_INT_GPIOINT0A          96
194    /* GPIO 0  POINTRPEND1 */
195#define AM335X_INT_GPIOINT0B          97
196    /* GPIO 0  POINTRPEND2 */
197#define AM335X_INT_GPIOINT1A          98
198    /* GPIO 1  POINTRPEND1 */
199#define AM335X_INT_GPIOINT1B          99
200    /* GPIO 1  POINTRPEND2 */
201#define AM335X_INT_GPMCINT            100
202    /* GPMC  gpmc_sinterrupt */
203#define AM335X_INT_DDRERR0            101
204    /* EMIF  sys_err_intr_pend */
205#define AM335X_INT_TCERRINT0          112
206    /* TPTC0  tptc_erint_pend_po */
207#define AM335X_INT_TCERRINT1          113
208    /* TPTC1  tptc_erint_pend_po */
209#define AM335X_INT_TCERRINT2          114
210    /* TPTC2  tptc_erint_pend_po */
211#define AM335X_INT_ADC_TSC_PENINT     115
212    /* ADC_TSC  pen_intr_pend */
213#define AM335X_INT_SMRFLX_Sabertooth  120
214    /* Smart Reflex 0  intrpen */
215#define AM335X_INT_SMRFLX_Core        121
216    /* Smart Reflex 1  intrpend */
217#define AM335X_INT_DMA_INTR_PIN0      123
218    /* pi_x_dma_event_intr0 (xdma_event_intr0) */
219#define AM335X_INT_DMA_INTR_PIN1      124
220    /* pi_x_dma_event_intr1 (xdma_event_intr1) */
221#define AM335X_INT_SPI1INT            125
222    /* McSPI1  SINTERRUPTN */
223
224#define OMAP3_AM335X_NR_IRQ_VECTORS    125
225
226#define AM335X_DMTIMER0_BASE      0x44E05000
227    /* DMTimer0 Registers */
228#define AM335X_DMTIMER1_1MS_BASE  0x44E31000
229    /* DMTimer1 1ms Registers (Accurate 1ms timer) */
230#define AM335X_DMTIMER2_BASE      0x48040000
231    /*  DMTimer2 Registers */
232#define AM335X_DMTIMER3_BASE      0x48042000
233    /*  DMTimer3 Registers */
234#define AM335X_DMTIMER4_BASE      0x48044000
235    /* DMTimer4 Registers  */
236#define AM335X_DMTIMER5_BASE      0x48046000
237    /* DMTimer5 Registers  */
238#define AM335X_DMTIMER6_BASE      0x48048000
239    /*  DMTimer6 Registers */
240#define AM335X_DMTIMER7_BASE      0x4804A000
241    /*  DMTimer7 Registers */
242
243/* General-purpose timer registers
244   AM335x non 1MS timers have different offsets */
245#define AM335X_TIMER_TIDR             0x000
246    /* IP revision code */
247#define AM335X_TIMER_TIOCP_CFG        0x010
248    /* Controls params for GP timer L4 interface */
249#define AM335X_TIMER_IRQSTATUS_RAW    0x024
250    /* Timer IRQSTATUS Raw Register */
251#define AM335X_TIMER_IRQSTATUS        0x028
252    /* Timer IRQSTATUS Register */
253#define AM335X_TIMER_IRQENABLE_SET    0x02C
254    /* Timer IRQENABLE Set Register */
255#define AM335X_TIMER_IRQENABLE_CLR    0x030
256    /* Timer IRQENABLE Clear Register */
257#define AM335X_TIMER_IRQWAKEEN        0x034
258    /* Timer IRQ Wakeup Enable Register */
259#define AM335X_TIMER_TCLR             0x038
260    /* Controls optional features */
261#define AM335X_TIMER_TCRR             0x03C
262    /* Internal counter value */
263#define AM335X_TIMER_TLDR             0x040
264    /* Timer load value */
265#define AM335X_TIMER_TTGR             0x044
266    /* Triggers counter reload */
267#define AM335X_TIMER_TWPS             0x048
268    /* Indicates if Write-Posted pending */
269#define AM335X_TIMER_TMAR             0x04C
270    /* Value to be compared with counter */
271#define AM335X_TIMER_TCAR1            0x050
272    /* First captured value of counter register */
273#define AM335X_TIMER_TSICR            0x054
274    /* Control posted mode and functional SW reset */
275#define AM335X_TIMER_TCAR2            0x058
276    /* Second captured value of counter register */
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