1 | /* |
---|
2 | * Copyright (c) 2012 Claas Ziemke. All rights reserved. |
---|
3 | * |
---|
4 | * Claas Ziemke |
---|
5 | * Kernerstrasse 11 |
---|
6 | * 70182 Stuttgart |
---|
7 | * Germany |
---|
8 | * <claas.ziemke@gmx.net> |
---|
9 | * |
---|
10 | * The license and distribution terms for this file may be |
---|
11 | * found in the file LICENSE in this distribution or at |
---|
12 | * http://www.rtems.org/license/LICENSE. |
---|
13 | * |
---|
14 | * Modified by Ben Gras <beng@shrike-systems.com> to add lots |
---|
15 | * of beagleboard/beaglebone definitions, delete lpc32xx specific |
---|
16 | * ones, and merge with some other header files. |
---|
17 | */ |
---|
18 | |
---|
19 | /* Interrupt controller memory map */ |
---|
20 | #define OMAP3_DM37XX_INTR_BASE 0x48200000 /* INTCPS physical address */ |
---|
21 | |
---|
22 | /* Interrupt controller memory map */ |
---|
23 | #define OMAP3_AM335X_INTR_BASE 0x48200000 /* INTCPS physical address */ |
---|
24 | |
---|
25 | #define AM335X_INT_EMUINT 0 |
---|
26 | /* Emulation interrupt (EMUICINTR) */ |
---|
27 | #define AM335X_INT_COMMTX 1 |
---|
28 | /* CortexA8 COMMTX */ |
---|
29 | #define AM335X_INT_COMMRX 2 |
---|
30 | /* CortexA8 COMMRX */ |
---|
31 | #define AM335X_INT_BENCH 3 |
---|
32 | /* CortexA8 NPMUIRQ */ |
---|
33 | #define AM335X_INT_ELM_IRQ 4 |
---|
34 | /* Sinterrupt (Error location process completion) */ |
---|
35 | #define AM335X_INT_NMI 7 |
---|
36 | /* nmi_int */ |
---|
37 | #define AM335X_INT_L3DEBUG 9 |
---|
38 | /* l3_FlagMux_top_FlagOut1 */ |
---|
39 | #define AM335X_INT_L3APPINT 10 |
---|
40 | /* l3_FlagMux_top_FlagOut0 */ |
---|
41 | #define AM335X_INT_PRCMINT 11 |
---|
42 | /* irq_mpu */ |
---|
43 | #define AM335X_INT_EDMACOMPINT 12 |
---|
44 | /* tpcc_int_pend_po0 */ |
---|
45 | #define AM335X_INT_EDMAMPERR 13 |
---|
46 | /* tpcc_mpint_pend_po */ |
---|
47 | #define AM335X_INT_EDMAERRINT 14 |
---|
48 | /* tpcc_errint_pend_po */ |
---|
49 | #define AM335X_INT_ADC_TSC_GENINT 16 |
---|
50 | /* gen_intr_pend */ |
---|
51 | #define AM335X_INT_USBSSINT 17 |
---|
52 | /* usbss_intr_pend */ |
---|
53 | #define AM335X_INT_USB0 18 |
---|
54 | /* usb0_intr_pend */ |
---|
55 | #define AM335X_INT_USB1 19 |
---|
56 | /* usb1_intr_pend */ |
---|
57 | #define AM335X_INT_PRUSS1_EVTOUT0 20 |
---|
58 | /* pr1_host_intr0_intr_pend */ |
---|
59 | #define AM335X_INT_PRUSS1_EVTOUT1 21 |
---|
60 | /* pr1_host_intr1_intr_pend */ |
---|
61 | #define AM335X_INT_PRUSS1_EVTOUT2 22 |
---|
62 | /* pr1_host_intr2_intr_pend */ |
---|
63 | #define AM335X_INT_PRUSS1_EVTOUT3 23 |
---|
64 | /* pr1_host_intr3_intr_pend */ |
---|
65 | #define AM335X_INT_PRUSS1_EVTOUT4 24 |
---|
66 | /* pr1_host_intr4_intr_pend */ |
---|
67 | #define AM335X_INT_PRUSS1_EVTOUT5 25 |
---|
68 | /* pr1_host_intr5_intr_pend */ |
---|
69 | #define AM335X_INT_PRUSS1_EVTOUT6 26 |
---|
70 | /* pr1_host_intr6_intr_pend */ |
---|
71 | #define AM335X_INT_PRUSS1_EVTOUT7 27 |
---|
72 | /* pr1_host_intr7_intr_pend */ |
---|
73 | #define AM335X_INT_MMCSD1INT 28 |
---|
74 | /* MMCSD1 SINTERRUPTN */ |
---|
75 | #define AM335X_INT_MMCSD2INT 29 |
---|
76 | /* MMCSD2 SINTERRUPT */ |
---|
77 | #define AM335X_INT_I2C2INT 30 |
---|
78 | /* I2C2 POINTRPEND */ |
---|
79 | #define AM335X_INT_eCAP0INT 31 |
---|
80 | /* ecap_intr_intr_pend */ |
---|
81 | #define AM335X_INT_GPIOINT2A 32 |
---|
82 | /* GPIO 2 POINTRPEND1 */ |
---|
83 | #define AM335X_INT_GPIOINT2B 33 |
---|
84 | /* GPIO 2 POINTRPEND2 */ |
---|
85 | #define AM335X_INT_USBWAKEUP 34 |
---|
86 | /* USBSS slv0p_Swakeup */ |
---|
87 | #define AM335X_INT_LCDCINT 36 |
---|
88 | /* LCDC lcd_irq */ |
---|
89 | #define AM335X_INT_GFXINT 37 |
---|
90 | /* SGX530 THALIAIRQ */ |
---|
91 | #define AM335X_INT_ePWM2INT 39 |
---|
92 | /* (PWM Subsystem) epwm_intr_intr_pend */ |
---|
93 | #define AM335X_INT_3PGSWRXTHR0 40 |
---|
94 | /* (Ethernet) c0_rx_thresh_pend (RX_THRESH_PULSE) */ |
---|
95 | #define AM335X_INT_3PGSWRXINT0 41 |
---|
96 | /* CPSW (Ethernet) c0_rx_pend */ |
---|
97 | #define AM335X_INT_3PGSWTXINT0 42 |
---|
98 | /* CPSW (Ethernet) c0_tx_pend */ |
---|
99 | #define AM335X_INT_3PGSWMISC0 43 |
---|
100 | /* CPSW (Ethernet) c0_misc_pend */ |
---|
101 | #define AM335X_INT_UART3INT 44 |
---|
102 | /* UART3 niq */ |
---|
103 | #define AM335X_INT_UART4INT 45 |
---|
104 | /* UART4 niq */ |
---|
105 | #define AM335X_INT_UART5INT 46 |
---|
106 | /* UART5 niq */ |
---|
107 | #define AM335X_INT_eCAP1INT 47 |
---|
108 | /* (PWM Subsystem) ecap_intr_intr_pend */ |
---|
109 | #define AM335X_INT_DCAN0_INT0 52 |
---|
110 | /* DCAN0 dcan_intr0_intr_pend */ |
---|
111 | #define AM335X_INT_DCAN0_INT1 53 |
---|
112 | /* DCAN0 dcan_intr1_intr_pend */ |
---|
113 | #define AM335X_INT_DCAN0_PARITY 54 |
---|
114 | /* DCAN0 dcan_uerr_intr_pend */ |
---|
115 | #define AM335X_INT_DCAN1_INT0 55 |
---|
116 | /* DCAN1 dcan_intr0_intr_pend */ |
---|
117 | #define AM335X_INT_DCAN1_INT1 56 |
---|
118 | /* DCAN1 dcan_intr1_intr_pend */ |
---|
119 | #define AM335X_INT_DCAN1_PARITY 57 |
---|
120 | /* DCAN1 dcan_uerr_intr_pend */ |
---|
121 | #define AM335X_INT_ePWM0_TZINT 58 |
---|
122 | /* eHRPWM0 TZ interrupt (PWM epwm_tz_intr_pend Subsystem) */ |
---|
123 | #define AM335X_INT_ePWM1_TZINT 59 |
---|
124 | /* eHRPWM1 TZ interrupt (PWM epwm_tz_intr_pend Subsystem) */ |
---|
125 | #define AM335X_INT_ePWM2_TZINT 60 |
---|
126 | /* eHRPWM2 TZ interrupt (PWM epwm_tz_intr_pend Subsystem) */ |
---|
127 | #define AM335X_INT_eCAP2INT 61 |
---|
128 | /* eCAP2 (PWM Subsystem) ecap_intr_intr_pend */ |
---|
129 | #define AM335X_INT_GPIOINT3A 62 |
---|
130 | /* GPIO 3 POINTRPEND1 */ |
---|
131 | #define AM335X_INT_GPIOINT3B 63 |
---|
132 | /* GPIO 3 POINTRPEND2 */ |
---|
133 | #define AM335X_INT_MMCSD0INT 64 |
---|
134 | /* MMCSD0 SINTERRUPTN */ |
---|
135 | #define AM335X_INT_SPI0INT 65 |
---|
136 | /* McSPI0 SINTERRUPTN */ |
---|
137 | #define AM335X_INT_TINT0 66 |
---|
138 | /* Timer0 POINTR_PEND */ |
---|
139 | #define AM335X_INT_TINT1_1MS 67 |
---|
140 | /* DMTIMER_1ms POINTR_PEND */ |
---|
141 | #define AM335X_INT_TINT2 68 |
---|
142 | /* DMTIMER2 POINTR_PEND */ |
---|
143 | #define AM335X_INT_TINT3 69 |
---|
144 | /* DMTIMER3 POINTR_PEND */ |
---|
145 | #define AM335X_INT_I2C0INT 70 |
---|
146 | /* I2C0 POINTRPEND */ |
---|
147 | #define AM335X_INT_I2C1INT 71 |
---|
148 | /* I2C1 POINTRPEND */ |
---|
149 | #define AM335X_INT_UART0INT 72 |
---|
150 | /* UART0 niq */ |
---|
151 | #define AM335X_INT_UART1INT 73 |
---|
152 | /* UART1 niq */ |
---|
153 | #define AM335X_INT_UART2INT 74 |
---|
154 | /* UART2 niq */ |
---|
155 | #define AM335X_INT_RTCINT 75 |
---|
156 | /* RTC timer_intr_pend */ |
---|
157 | #define AM335X_INT_RTCALARMINT 76 |
---|
158 | /* RTC alarm_intr_pend */ |
---|
159 | #define AM335X_INT_MBINT0 77 |
---|
160 | /* Mailbox0 (mail_u0_irq) initiator_sinterrupt_q_n */ |
---|
161 | #define AM335X_INT_M3_TXEV 78 |
---|
162 | /* Wake M3 Subsystem TXEV */ |
---|
163 | #define AM335X_INT_eQEP0INT 79 |
---|
164 | /* eQEP0 (PWM Subsystem) eqep_intr_intr_pend */ |
---|
165 | #define AM335X_INT_MCATXINT0 80 |
---|
166 | /* McASP0 mcasp_x_intr_pend */ |
---|
167 | #define AM335X_INT_MCARXINT0 81 |
---|
168 | /* McASP0 mcasp_r_intr_pend */ |
---|
169 | #define AM335X_INT_MCATXINT1 82 |
---|
170 | /* McASP1 mcasp_x_intr_pend */ |
---|
171 | #define AM335X_INT_MCARXINT1 83 |
---|
172 | /* McASP1 mcasp_r_intr_pend */ |
---|
173 | #define AM335X_INT_ePWM0INT 86 |
---|
174 | /* (PWM Subsystem) epwm_intr_intr_pend */ |
---|
175 | #define AM335X_INT_ePWM1INT 87 |
---|
176 | /* (PWM Subsystem) epwm_intr_intr_pend */ |
---|
177 | #define AM335X_INT_eQEP1INT 88 |
---|
178 | /* (PWM Subsystem) eqep_intr_intr_pend */ |
---|
179 | #define AM335X_INT_eQEP2INT 89 |
---|
180 | /* (PWM Subsystem) eqep_intr_intr_pend */ |
---|
181 | #define AM335X_INT_DMA_INTR_PIN2 90 |
---|
182 | /* External DMA/Interrupt Pin2 */ |
---|
183 | #define AM335X_INT_WDT1INT 91 |
---|
184 | /* (Public Watchdog) WDTIMER1 PO_INT_PEND */ |
---|
185 | #define AM335X_INT_TINT4 92 |
---|
186 | /* DMTIMER4 POINTR_PEN */ |
---|
187 | #define AM335X_INT_TINT5 93 |
---|
188 | /* DMTIMER5 POINTR_PEN */ |
---|
189 | #define AM335X_INT_TINT6 94 |
---|
190 | /* DMTIMER6 POINTR_PEND */ |
---|
191 | #define AM335X_INT_TINT7 95 |
---|
192 | /* DMTIMER7 POINTR_PEND */ |
---|
193 | #define AM335X_INT_GPIOINT0A 96 |
---|
194 | /* GPIO 0 POINTRPEND1 */ |
---|
195 | #define AM335X_INT_GPIOINT0B 97 |
---|
196 | /* GPIO 0 POINTRPEND2 */ |
---|
197 | #define AM335X_INT_GPIOINT1A 98 |
---|
198 | /* GPIO 1 POINTRPEND1 */ |
---|
199 | #define AM335X_INT_GPIOINT1B 99 |
---|
200 | /* GPIO 1 POINTRPEND2 */ |
---|
201 | #define AM335X_INT_GPMCINT 100 |
---|
202 | /* GPMC gpmc_sinterrupt */ |
---|
203 | #define AM335X_INT_DDRERR0 101 |
---|
204 | /* EMIF sys_err_intr_pend */ |
---|
205 | #define AM335X_INT_TCERRINT0 112 |
---|
206 | /* TPTC0 tptc_erint_pend_po */ |
---|
207 | #define AM335X_INT_TCERRINT1 113 |
---|
208 | /* TPTC1 tptc_erint_pend_po */ |
---|
209 | #define AM335X_INT_TCERRINT2 114 |
---|
210 | /* TPTC2 tptc_erint_pend_po */ |
---|
211 | #define AM335X_INT_ADC_TSC_PENINT 115 |
---|
212 | /* ADC_TSC pen_intr_pend */ |
---|
213 | #define AM335X_INT_SMRFLX_Sabertooth 120 |
---|
214 | /* Smart Reflex 0 intrpen */ |
---|
215 | #define AM335X_INT_SMRFLX_Core 121 |
---|
216 | /* Smart Reflex 1 intrpend */ |
---|
217 | #define AM335X_INT_DMA_INTR_PIN0 123 |
---|
218 | /* pi_x_dma_event_intr0 (xdma_event_intr0) */ |
---|
219 | #define AM335X_INT_DMA_INTR_PIN1 124 |
---|
220 | /* pi_x_dma_event_intr1 (xdma_event_intr1) */ |
---|
221 | #define AM335X_INT_SPI1INT 125 |
---|
222 | /* McSPI1 SINTERRUPTN */ |
---|
223 | |
---|
224 | #define OMAP3_AM335X_NR_IRQ_VECTORS 125 |
---|
225 | |
---|
226 | #define AM335X_DMTIMER0_BASE 0x44E05000 |
---|
227 | /* DMTimer0 Registers */ |
---|
228 | #define AM335X_DMTIMER1_1MS_BASE 0x44E31000 |
---|
229 | /* DMTimer1 1ms Registers (Accurate 1ms timer) */ |
---|
230 | #define AM335X_DMTIMER2_BASE 0x48040000 |
---|
231 | /* DMTimer2 Registers */ |
---|
232 | #define AM335X_DMTIMER3_BASE 0x48042000 |
---|
233 | /* DMTimer3 Registers */ |
---|
234 | #define AM335X_DMTIMER4_BASE 0x48044000 |
---|
235 | /* DMTimer4 Registers */ |
---|
236 | #define AM335X_DMTIMER5_BASE 0x48046000 |
---|
237 | /* DMTimer5 Registers */ |
---|
238 | #define AM335X_DMTIMER6_BASE 0x48048000 |
---|
239 | /* DMTimer6 Registers */ |
---|
240 | #define AM335X_DMTIMER7_BASE 0x4804A000 |
---|
241 | /* DMTimer7 Registers */ |
---|
242 | |
---|
243 | /* General-purpose timer registers |
---|
244 | AM335x non 1MS timers have different offsets */ |
---|
245 | #define AM335X_TIMER_TIDR 0x000 |
---|
246 | /* IP revision code */ |
---|
247 | #define AM335X_TIMER_TIOCP_CFG 0x010 |
---|
248 | /* Controls params for GP timer L4 interface */ |
---|
249 | #define AM335X_TIMER_IRQSTATUS_RAW 0x024 |
---|
250 | /* Timer IRQSTATUS Raw Register */ |
---|
251 | #define AM335X_TIMER_IRQSTATUS 0x028 |
---|
252 | /* Timer IRQSTATUS Register */ |
---|
253 | #define AM335X_TIMER_IRQENABLE_SET 0x02C |
---|
254 | /* Timer IRQENABLE Set Register */ |
---|
255 | #define AM335X_TIMER_IRQENABLE_CLR 0x030 |
---|
256 | /* Timer IRQENABLE Clear Register */ |
---|
257 | #define AM335X_TIMER_IRQWAKEEN 0x034 |
---|
258 | /* Timer IRQ Wakeup Enable Register */ |
---|
259 | #define AM335X_TIMER_TCLR 0x038 |
---|
260 | /* Controls optional features */ |
---|
261 | #define AM335X_TIMER_TCRR 0x03C |
---|
262 | /* Internal counter value */ |
---|
263 | #define AM335X_TIMER_TLDR 0x040 |
---|
264 | /* Timer load value */ |
---|
265 | #define AM335X_TIMER_TTGR 0x044 |
---|
266 | /* Triggers counter reload */ |
---|
267 | #define AM335X_TIMER_TWPS 0x048 |
---|
268 | /* Indicates if Write-Posted pending */ |
---|
269 | #define AM335X_TIMER_TMAR 0x04C |
---|
270 | /* Value to be compared with counter */ |
---|
271 | #define AM335X_TIMER_TCAR1 0x050 |
---|
272 | /* First captured value of counter register */ |
---|
273 | #define AM335X_TIMER_TSICR 0x054 |
---|
274 | /* Control posted mode and functional SW reset */ |
---|
275 | #define AM335X_TIMER_TCAR2 0x058 |
---|
276 | /* Second captured value of counter register */ |
---|
277 | #define AM335X_WDT_BASE 0x44E35000 |
---|
278 | /* Watchdog timer */ |
---|
279 | #define AM335X_WDT_WWPS 0x34 |
---|
280 | /* Command posted status */ |
---|
281 | #define AM335X_WDT_WSPR 0x48 |
---|
282 | /* Activate/deactivate sequence */ |
---|
283 | |
---|
284 | /* RTC registers */ |
---|
285 | #define AM335X_RTC_BASE 0x44E3E000 |
---|
286 | #define AM335X_RTC_SECS 0x0 |
---|
287 | #define AM335X_RTC_MINS 0x4 |
---|
288 | #define AM335X_RTC_HOURS 0x8 |
---|
289 | #define AM335X_RTC_DAYS 0xc |
---|
290 | #define AM335X_RTC_MONTHS 0x10 |
---|
291 | #define AM335X_RTC_YEARS 0x14 |
---|
292 | #define AM335X_RTC_WEEKS 0x18 |
---|
293 | #define AM335X_RTC_CTRL_REG 0x40 |
---|
294 | #define AM335X_RTC_STATUS_REG 0x44 |
---|
295 | #define AM335X_RTC_REV_REG 0x74 |
---|
296 | #define AM335X_RTC_SYSCONFIG 0x78 |
---|
297 | #define AM335X_RTC_KICK0 0x6c |
---|
298 | #define AM335X_RTC_KICK1 0x70 |
---|
299 | #define AM335X_RTC_OSC_CLOCK 0x54 |
---|
300 | |
---|
301 | #define AM335X_RTC_KICK0_KEY 0x83E70B13 |
---|
302 | #define AM335X_RTC_KICK1_KEY 0x95A4F1E0 |
---|
303 | |
---|
304 | /* GPIO memory-mapped registers */ |
---|
305 | |
---|
306 | #define AM335X_GPIO0_BASE 0x44E07000 |
---|
307 | /* GPIO Bank 0 base Register */ |
---|
308 | #define AM335X_GPIO1_BASE 0x4804C000 |
---|
309 | /* GPIO Bank 1 base Register */ |
---|
310 | #define AM335X_GPIO2_BASE 0x481AC000 |
---|
311 | /* GPIO Bank 2 base Register */ |
---|
312 | #define AM335X_GPIO3_BASE 0x481AE000 |
---|
313 | /* GPIO Bank 3 base Register */ |
---|
314 | |
---|
315 | #define AM335X_GPIO_REVISION 0x00 |
---|
316 | #define AM335X_GPIO_SYSCONFIG 0x10 |
---|
317 | #define AM335X_GPIO_EOI 0x20 |
---|
318 | #define AM335X_GPIO_IRQSTATUS_RAW_0 0x24 |
---|
319 | #define AM335X_GPIO_IRQSTATUS_RAW_1 0x28 |
---|
320 | #define AM335X_GPIO_IRQSTATUS_0 0x2C |
---|
321 | #define AM335X_GPIO_IRQSTATUS_1 0x30 |
---|
322 | #define AM335X_GPIO_IRQSTATUS_SET_0 0x34 |
---|
323 | #define AM335X_GPIO_IRQSTATUS_SET_1 0x38 |
---|
324 | #define AM335X_GPIO_IRQSTATUS_CLR_0 0x3C |
---|
325 | #define AM335X_GPIO_IRQSTATUS_CLR_1 0x40 |
---|
326 | #define AM335X_GPIO_IRQWAKEN_0 0x44 |
---|
327 | #define AM335X_GPIO_IRQWAKEN_1 0x48 |
---|
328 | #define AM335X_GPIO_SYSSTATUS 0x114 |
---|
329 | #define AM335X_GPIO_CTRL 0x130 |
---|
330 | #define AM335X_GPIO_OE 0x134 |
---|
331 | #define AM335X_GPIO_DATAIN 0x138 |
---|
332 | #define AM335X_GPIO_DATAOUT 0x13C |
---|
333 | #define AM335X_GPIO_LEVELDETECT0 0x140 |
---|
334 | #define AM335X_GPIO_LEVELDETECT1 0x144 |
---|
335 | #define AM335X_GPIO_RISINGDETECT 0x148 |
---|
336 | #define AM335X_GPIO_FALLINGDETECT 0x14C |
---|
337 | #define AM335X_GPIO_DEBOUNCENABLE 0x150 |
---|
338 | #define AM335X_GPIO_DEBOUNCINGTIME 0x154 |
---|
339 | #define AM335X_GPIO_CLEARDATAOUT 0x190 |
---|
340 | #define AM335X_GPIO_SETDATAOUT 0x194 |
---|
341 | |
---|
342 | /* AM335X Pad Configuration Register Base */ |
---|
343 | #define AM335X_PADCONF_BASE 0x44E10000 |
---|
344 | |
---|
345 | /* Memory mapped register offset for Control Module */ |
---|
346 | #define AM335X_CONF_GPMC_AD0 0x800 |
---|
347 | #define AM335X_CONF_GPMC_AD1 0x804 |
---|
348 | #define AM335X_CONF_GPMC_AD2 0x808 |
---|
349 | #define AM335X_CONF_GPMC_AD3 0x80C |
---|
350 | #define AM335X_CONF_GPMC_AD4 0x810 |
---|
351 | #define AM335X_CONF_GPMC_AD5 0x814 |
---|
352 | #define AM335X_CONF_GPMC_AD6 0x818 |
---|
353 | #define AM335X_CONF_GPMC_AD7 0x81C |
---|
354 | #define AM335X_CONF_GPMC_AD8 0x820 |
---|
355 | #define AM335X_CONF_GPMC_AD9 0x824 |
---|
356 | #define AM335X_CONF_GPMC_AD10 0x828 |
---|
357 | #define AM335X_CONF_GPMC_AD11 0x82C |
---|
358 | #define AM335X_CONF_GPMC_AD12 0x830 |
---|
359 | #define AM335X_CONF_GPMC_AD13 0x834 |
---|
360 | #define AM335X_CONF_GPMC_AD14 0x838 |
---|
361 | #define AM335X_CONF_GPMC_AD15 0x83C |
---|
362 | #define AM335X_CONF_GPMC_A0 0x840 |
---|
363 | #define AM335X_CONF_GPMC_A1 0x844 |
---|
364 | #define AM335X_CONF_GPMC_A2 0x848 |
---|
365 | #define AM335X_CONF_GPMC_A3 0x84C |
---|
366 | #define AM335X_CONF_GPMC_A4 0x850 |
---|
367 | #define AM335X_CONF_GPMC_A5 0x854 |
---|
368 | #define AM335X_CONF_GPMC_A6 0x858 |
---|
369 | #define AM335X_CONF_GPMC_A7 0x85C |
---|
370 | #define AM335X_CONF_GPMC_A8 0x860 |
---|
371 | #define AM335X_CONF_GPMC_A9 0x864 |
---|
372 | #define AM335X_CONF_GPMC_A10 0x868 |
---|
373 | #define AM335X_CONF_GPMC_A11 0x86C |
---|
374 | #define AM335X_CONF_GPMC_WAIT0 0x870 |
---|
375 | #define AM335X_CONF_GPMC_WPN 0x874 |
---|
376 | #define AM335X_CONF_GPMC_BEN1 0x878 |
---|
377 | #define AM335X_CONF_GPMC_CSN0 0x87C |
---|
378 | #define AM335X_CONF_GPMC_CSN1 0x880 |
---|
379 | #define AM335X_CONF_GPMC_CSN2 0x884 |
---|
380 | #define AM335X_CONF_GPMC_CSN3 0x888 |
---|
381 | #define AM335X_CONF_GPMC_CLK 0x88C |
---|
382 | #define AM335X_CONF_GPMC_ADVN_ALE 0x890 |
---|
383 | #define AM335X_CONF_GPMC_OEN_REN 0x894 |
---|
384 | #define AM335X_CONF_GPMC_WEN 0x898 |
---|
385 | #define AM335X_CONF_GPMC_BEN0_CLE 0x89C |
---|
386 | #define AM335X_CONF_LCD_DATA0 0x8A0 |
---|
387 | #define AM335X_CONF_LCD_DATA1 0x8A4 |
---|
388 | #define AM335X_CONF_LCD_DATA2 0x8A8 |
---|
389 | #define AM335X_CONF_LCD_DATA3 0x8AC |
---|
390 | #define AM335X_CONF_LCD_DATA4 0x8B0 |
---|
391 | #define AM335X_CONF_LCD_DATA5 0x8B4 |
---|
392 | #define AM335X_CONF_LCD_DATA6 0x8B8 |
---|
393 | #define AM335X_CONF_LCD_DATA7 0x8BC |
---|
394 | #define AM335X_CONF_LCD_DATA8 0x8C0 |
---|
395 | #define AM335X_CONF_LCD_DATA9 0x8C4 |
---|
396 | #define AM335X_CONF_LCD_DATA10 0x8C8 |
---|
397 | #define AM335X_CONF_LCD_DATA11 0x8CC |
---|
398 | #define AM335X_CONF_LCD_DATA12 0x8D0 |
---|
399 | #define AM335X_CONF_LCD_DATA13 0x8D4 |
---|
400 | #define AM335X_CONF_LCD_DATA14 0x8D8 |
---|
401 | #define AM335X_CONF_LCD_DATA15 0x8DC |
---|
402 | #define AM335X_CONF_LCD_VSYNC 0x8E0 |
---|
403 | #define AM335X_CONF_LCD_HSYNC 0x8E4 |
---|
404 | #define AM335X_CONF_LCD_PCLK 0x8E8 |
---|
405 | #define AM335X_CONF_LCD_AC_BIAS_EN 0x8EC |
---|
406 | #define AM335X_CONF_MMC0_DAT3 0x8F0 |
---|
407 | #define AM335X_CONF_MMC0_DAT2 0x8F4 |
---|
408 | #define AM335X_CONF_MMC0_DAT1 0x8F8 |
---|
409 | #define AM335X_CONF_MMC0_DAT0 0x8FC |
---|
410 | #define AM335X_CONF_MMC0_CLK 0x900 |
---|
411 | #define AM335X_CONF_MMC0_CMD 0x904 |
---|
412 | #define AM335X_CONF_MII1_COL 0x908 |
---|
413 | #define AM335X_CONF_MII1_CRS 0x90C |
---|
414 | #define AM335X_CONF_MII1_RX_ER 0x910 |
---|
415 | #define AM335X_CONF_MII1_TX_EN 0x914 |
---|
416 | #define AM335X_CONF_MII1_RX_DV 0x918 |
---|
417 | #define AM335X_CONF_MII1_TXD3 0x91C |
---|
418 | #define AM335X_CONF_MII1_TXD2 0x920 |
---|
419 | #define AM335X_CONF_MII1_TXD1 0x924 |
---|
420 | #define AM335X_CONF_MII1_TXD0 0x928 |
---|
421 | #define AM335X_CONF_MII1_TX_CLK 0x92C |
---|
422 | #define AM335X_CONF_MII1_RX_CLK 0x930 |
---|
423 | #define AM335X_CONF_MII1_RXD3 0x934 |
---|
424 | #define AM335X_CONF_MII1_RXD2 0x938 |
---|
425 | #define AM335X_CONF_MII1_RXD1 0x93C |
---|
426 | #define AM335X_CONF_MII1_RXD0 0x940 |
---|
427 | #define AM335X_CONF_RMII1_REF_CLK 0x944 |
---|
428 | #define AM335X_CONF_MDIO 0x948 |
---|
429 | #define AM335X_CONF_MDC 0x94C |
---|
430 | #define AM335X_CONF_SPI0_SCLK 0x950 |
---|
431 | #define AM335X_CONF_SPI0_D0 0x954 |
---|
432 | #define AM335X_CONF_SPI0_D1 0x958 |
---|
433 | #define AM335X_CONF_SPI0_CS0 0x95C |
---|
434 | #define AM335X_CONF_SPI0_CS1 0x960 |
---|
435 | #define AM335X_CONF_ECAP0_IN_PWM0_OUT 0x964 |
---|
436 | #define AM335X_CONF_UART0_CTSN 0x968 |
---|
437 | #define AM335X_CONF_UART0_RTSN 0x96C |
---|
438 | #define AM335X_CONF_UART0_RXD 0x970 |
---|
439 | #define AM335X_CONF_UART0_TXD 0x974 |
---|
440 | #define AM335X_CONF_UART1_CTSN 0x978 |
---|
441 | #define AM335X_CONF_UART1_RTSN 0x97C |
---|
442 | #define AM335X_CONF_UART1_RXD 0x980 |
---|
443 | #define AM335X_CONF_UART1_TXD 0x984 |
---|
444 | #define AM335X_CONF_I2C0_SDA 0x988 |
---|
445 | #define AM335X_CONF_I2C0_SCL 0x98C |
---|
446 | #define AM335X_CONF_MCASP0_ACLKX 0x990 |
---|
447 | #define AM335X_CONF_MCASP0_FSX 0x994 |
---|
448 | #define AM335X_CONF_MCASP0_AXR0 0x998 |
---|
449 | #define AM335X_CONF_MCASP0_AHCLKR 0x99C |
---|
450 | #define AM335X_CONF_MCASP0_ACLKR 0x9A0 |
---|
451 | #define AM335X_CONF_MCASP0_FSR 0x9A4 |
---|
452 | #define AM335X_CONF_MCASP0_AXR1 0x9A8 |
---|
453 | #define AM335X_CONF_MCASP0_AHCLKX 0x9AC |
---|
454 | #define AM335X_CONF_XDMA_EVENT_INTR0 0x9B0 |
---|
455 | #define AM335X_CONF_XDMA_EVENT_INTR1 0x9B4 |
---|
456 | #define AM335X_CONF_WARMRSTN 0x9B8 |
---|
457 | #define AM335X_CONF_NNMI 0x9C0 |
---|
458 | #define AM335X_CONF_TMS 0x9D0 |
---|
459 | #define AM335X_CONF_TDI 0x9D4 |
---|
460 | #define AM335X_CONF_TDO 0x9D8 |
---|
461 | #define AM335X_CONF_TCK 0x9DC |
---|
462 | #define AM335X_CONF_TRSTN 0x9E0 |
---|
463 | #define AM335X_CONF_EMU0 0x9E4 |
---|
464 | #define AM335X_CONF_EMU1 0x9E8 |
---|
465 | #define AM335X_CONF_RTC_PWRONRSTN 0x9F8 |
---|
466 | #define AM335X_CONF_PMIC_POWER_EN 0x9FC |
---|
467 | #define AM335X_CONF_EXT_WAKEUP 0xA00 |
---|
468 | #define AM335X_CONF_RTC_KALDO_ENN 0xA04 |
---|
469 | #define AM335X_CONF_USB0_DRVVBUS 0xA1C |
---|
470 | #define AM335X_CONF_USB1_DRVVBUS 0xA34 |
---|