source: rtems/c/src/lib/libcpu/arm/s3c24xx/include/s3c2400.h @ c193baad

4.104.11
Last change on this file since c193baad was c193baad, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Apr 9, 2010 at 8:24:57 PM

unify irq data types and code, merge s3c2400/s3c2410 support

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File size: 29.7 KB
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1/************************************************
2 * NAME     : s3c2400.h
3 * Version  : 3.7.2002
4 *
5 * Based on 24x.h for the Samsung Development Board
6 ************************************************/
7
8#ifndef S3C2400_H_
9#define S3C2400_H_
10
11/* to be used in assembly code */
12#define rINTOFFSET_ADDR 0x14400014
13/* Memory control */
14#define rBWSCON         (*(volatile unsigned *)0x14000000)
15#define rBANKCON0       (*(volatile unsigned *)0x14000004)
16#define rBANKCON1       (*(volatile unsigned *)0x14000008)
17#define rBANKCON2       (*(volatile unsigned *)0x1400000C)
18#define rBANKCON3       (*(volatile unsigned *)0x14000010)
19#define rBANKCON4       (*(volatile unsigned *)0x14000014)
20#define rBANKCON5       (*(volatile unsigned *)0x14000018)
21#define rBANKCON6       (*(volatile unsigned *)0x1400001C)
22#define rBANKCON7       (*(volatile unsigned *)0x14000020)
23#define rREFRESH        (*(volatile unsigned *)0x14000024)
24#define rBANKSIZE       (*(volatile unsigned *)0x14000028)
25#define rMRSRB6         (*(volatile unsigned *)0x1400002C)
26#define rMRSRB7         (*(volatile unsigned *)0x14000030)
27
28
29/* INTERRUPT */
30#define rSRCPND         (*(volatile unsigned *)0x14400000)
31#define rINTMOD         (*(volatile unsigned *)0x14400004)
32#define rINTMSK         (*(volatile unsigned *)0x14400008)
33#define rPRIORITY       (*(volatile unsigned *)0x1440000C)
34#define rINTPND         (*(volatile unsigned *)0x14400010)
35#define rINTOFFSET      (*(volatile unsigned *)0x14400014)
36
37
38/* DMA */
39#define rDISRC0         (*(volatile unsigned *)0x14600000)
40#define rDIDST0         (*(volatile unsigned *)0x14600004)
41#define rDCON0          (*(volatile unsigned *)0x14600008)
42#define rDSTAT0         (*(volatile unsigned *)0x1460000C)
43#define rDCSRC0         (*(volatile unsigned *)0x14600010)
44#define rDCDST0         (*(volatile unsigned *)0x14600014)
45#define rDMASKTRIG0     (*(volatile unsigned *)0x14600018)
46#define rDISRC1         (*(volatile unsigned *)0x14600020)
47#define rDIDST1         (*(volatile unsigned *)0x14600024)
48#define rDCON1          (*(volatile unsigned *)0x14600028)
49#define rDSTAT1         (*(volatile unsigned *)0x1460002C)
50#define rDCSRC1         (*(volatile unsigned *)0x14600030)
51#define rDCDST1         (*(volatile unsigned *)0x14600034)
52#define rDMASKTRIG1     (*(volatile unsigned *)0x14600038)
53#define rDISRC2         (*(volatile unsigned *)0x14600040)
54#define rDIDST2         (*(volatile unsigned *)0x14600044)
55#define rDCON2          (*(volatile unsigned *)0x14600048)
56#define rDSTAT2         (*(volatile unsigned *)0x1460004C)
57#define rDCSRC2         (*(volatile unsigned *)0x14600050)
58#define rDCDST2         (*(volatile unsigned *)0x14600054)
59#define rDMASKTRIG2     (*(volatile unsigned *)0x14600058)
60#define rDISRC3         (*(volatile unsigned *)0x14600060)
61#define rDIDST3         (*(volatile unsigned *)0x14600064)
62#define rDCON3          (*(volatile unsigned *)0x14600068)
63#define rDSTAT3         (*(volatile unsigned *)0x1460006C)
64#define rDCSRC3         (*(volatile unsigned *)0x14600070)
65#define rDCDST3         (*(volatile unsigned *)0x14600074)
66#define rDMASKTRIG3     (*(volatile unsigned *)0x14600078)
67
68
69/* CLOCK & POWER MANAGEMENT */
70#define rLOCKTIME       (*(volatile unsigned *)0x14800000)
71#define rMPLLCON        (*(volatile unsigned *)0x14800004)
72#define rUPLLCON        (*(volatile unsigned *)0x14800008)
73#define rCLKCON         (*(volatile unsigned *)0x1480000C)
74#define rCLKSLOW        (*(volatile unsigned *)0x14800010)
75#define rCLKDIVN        (*(volatile unsigned *)0x14800014)
76
77
78/* LCD CONTROLLER */
79#define rLCDCON1        (*(volatile unsigned *)0x14A00000)
80#define rLCDCON2        (*(volatile unsigned *)0x14A00004)
81#define rLCDCON3        (*(volatile unsigned *)0x14A00008)
82#define rLCDCON4        (*(volatile unsigned *)0x14A0000C)
83#define rLCDCON5        (*(volatile unsigned *)0x14A00010)
84#define rLCDSADDR1      (*(volatile unsigned *)0x14A00014)
85#define rLCDSADDR2      (*(volatile unsigned *)0x14A00018)
86#define rLCDSADDR3      (*(volatile unsigned *)0x14A0001C)
87#define rREDLUT         (*(volatile unsigned *)0x14A00020)
88#define rGREENLUT       (*(volatile unsigned *)0x14A00024)
89#define rBLUELUT        (*(volatile unsigned *)0x14A00028)
90#define rDP1_2          (*(volatile unsigned *)0x14A0002C)
91#define rDP4_7          (*(volatile unsigned *)0x14A00030)
92#define rDP3_5          (*(volatile unsigned *)0x14A00034)
93#define rDP2_3          (*(volatile unsigned *)0x14A00038)
94#define rDP5_7          (*(volatile unsigned *)0x14A0003c)
95#define rDP3_4          (*(volatile unsigned *)0x14A00040)
96#define rDP4_5          (*(volatile unsigned *)0x14A00044)
97#define rDP6_7          (*(volatile unsigned *)0x14A00048)
98#define rDITHMODE       (*(volatile unsigned *)0x14A0004C)
99#define rTPAL           (*(volatile unsigned *)0x14A00050)
100#define GP32_PALETTE    (*(volatile unsigned *)0x14A00400)      /* SJS */
101
102
103/* UART */
104#define rULCON0         (*(volatile unsigned char *)0x15000000)
105#define rUCON0          (*(volatile unsigned short *)0x15000004)
106#define rUFCON0         (*(volatile unsigned char *)0x15000008)
107#define rUMCON0         (*(volatile unsigned char *)0x1500000C)
108#define rUTRSTAT0       (*(volatile unsigned char *)0x15000010)
109#define rUERSTAT0       (*(volatile unsigned char *)0x15000014)
110#define rUFSTAT0        (*(volatile unsigned short *)0x15000018)
111#define rUMSTAT0        (*(volatile unsigned char *)0x1500001C)
112#define rUBRDIV0        (*(volatile unsigned short *)0x15000028)
113
114#define rULCON1         (*(volatile unsigned char *)0x15004000)
115#define rUCON1          (*(volatile unsigned short *)0x15004004)
116#define rUFCON1         (*(volatile unsigned char *)0x15004008)
117#define rUMCON1         (*(volatile unsigned char *)0x1500400C)
118#define rUTRSTAT1       (*(volatile unsigned char *)0x15004010)
119#define rUERSTAT1       (*(volatile unsigned char *)0x15004014)
120#define rUFSTAT1        (*(volatile unsigned short *)0x15004018)
121#define rUMSTAT1        (*(volatile unsigned char *)0x1500401C)
122#define rUBRDIV1        (*(volatile unsigned short *)0x15004028)
123
124#ifdef __BIG_ENDIAN
125#define rUTXH0          (*(volatile unsigned char *)0x15000023)
126#define rURXH0          (*(volatile unsigned char *)0x15000027)
127#define rUTXH1          (*(volatile unsigned char *)0x15004023)
128#define rURXH1          (*(volatile unsigned char *)0x15004027)
129
130#define WrUTXH0(ch)     (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch)
131#define RdURXH0()       (*(volatile unsigned char *)0x15000027)
132#define WrUTXH1(ch)     (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch)
133#define RdURXH1()       (*(volatile unsigned char *)0x15004027)
134
135#define UTXH0           (0x15000020+3)  /* byte_access address by DMA */
136#define URXH0           (0x15000024+3)
137#define UTXH1           (0x15004020+3)
138#define URXH1           (0x15004024+3)
139
140#else /* Little Endian */
141#define rUTXH0          (*(volatile unsigned char *)0x15000020)
142#define rURXH0          (*(volatile unsigned char *)0x15000024)
143#define rUTXH1          (*(volatile unsigned char *)0x15004020)
144#define rURXH1          (*(volatile unsigned char *)0x15004024)
145
146#define WrUTXH0(ch)     (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch)
147#define RdURXH0()       (*(volatile unsigned char *)0x15000024)
148#define WrUTXH1(ch)     (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch)
149#define RdURXH1()       (*(volatile unsigned char *)0x15004024)
150
151#define UTXH0           (0x15000020)    /* byte_access address by DMA */
152#define URXH0           (0x15000024)
153#define UTXH1           (0x15004020)
154#define URXH1           (0x15004024)
155#endif
156
157
158/* PWM TIMER */
159#define rTCFG0          (*(volatile unsigned *)0x15100000)
160#define rTCFG1          (*(volatile unsigned *)0x15100004)
161#define rTCON           (*(volatile unsigned *)0x15100008)
162#define rTCNTB0         (*(volatile unsigned *)0x1510000C)
163#define rTCMPB0         (*(volatile unsigned *)0x15100010)
164#define rTCNTO0         (*(volatile unsigned *)0x15100014)
165#define rTCNTB1         (*(volatile unsigned *)0x15100018)
166#define rTCMPB1         (*(volatile unsigned *)0x1510001C)
167#define rTCNTO1         (*(volatile unsigned *)0x15100020)
168#define rTCNTB2         (*(volatile unsigned *)0x15100024)
169#define rTCMPB2         (*(volatile unsigned *)0x15100028)
170#define rTCNTO2         (*(volatile unsigned *)0x1510002C)
171#define rTCNTB3         (*(volatile unsigned *)0x15100030)
172#define rTCMPB3         (*(volatile unsigned *)0x15100034)
173#define rTCNTO3         (*(volatile unsigned *)0x15100038)
174#define rTCNTB4         (*(volatile unsigned *)0x1510003C)
175#define rTCNTO4         (*(volatile unsigned *)0x15100040)
176
177
178/* USB DEVICE */
179#define rFUNC_ADDR_REG  (*(volatile unsigned *)0x15200140)
180#define rPWR_REG        (*(volatile unsigned *)0x15200144)
181#define rINT_REG        (*(volatile unsigned *)0x15200148)
182#define rINT_MASK_REG   (*(volatile unsigned *)0x1520014C)
183#define rFRAME_NUM_REG  (*(volatile unsigned *)0x15200150)
184#define rRESUME_CON_REG (*(volatile unsigned *)0x15200154)
185#define rEP0_CSR        (*(volatile unsigned *)0x15200160)
186#define rEP0_MAXP       (*(volatile unsigned *)0x15200164)
187#define rEP0_OUT_CNT    (*(volatile unsigned *)0x15200168)
188#define rEP0_FIFO       (*(volatile unsigned *)0x1520016C)
189#define rEP1_IN_CSR     (*(volatile unsigned *)0x15200180)
190#define rEP1_IN_MAXP    (*(volatile unsigned *)0x15200184)
191#define rEP1_FIFO       (*(volatile unsigned *)0x15200188)
192#define rEP2_IN_CSR     (*(volatile unsigned *)0x15200190)
193#define rEP2_IN_MAXP    (*(volatile unsigned *)0x15200194)
194#define rEP2_FIFO       (*(volatile unsigned *)0x15200198)
195#define rEP3_OUT_CSR    (*(volatile unsigned *)0x152001A0)
196#define rEP3_OUT_MAXP   (*(volatile unsigned *)0x152001A4)
197#define rEP3_OUT_CNT    (*(volatile unsigned *)0x152001A8)
198#define rEP3_FIFO       (*(volatile unsigned *)0x152001AC)
199#define rEP4_OUT_CSR    (*(volatile unsigned *)0x152001B0)
200#define rEP4_OUT_MAXP   (*(volatile unsigned *)0x152001B4)
201#define rEP4_OUT_CNT    (*(volatile unsigned *)0x152001B8)
202#define rEP4_FIFO       (*(volatile unsigned *)0x152001BC)
203#define rDMA_CON        (*(volatile unsigned *)0x152001C0)
204#define rDMA_UNIT       (*(volatile unsigned *)0x152001C4)
205#define rDMA_FIFO       (*(volatile unsigned *)0x152001C8)
206#define rDMA_TX         (*(volatile unsigned *)0x152001CC)
207#define rTEST_MODE      (*(volatile unsigned *)0x152001F4)
208#define rIN_CON_REG     (*(volatile unsigned *)0x152001F8)
209
210
211/* WATCH DOG TIMER */
212#define rWTCON          (*(volatile unsigned *)0x15300000)
213#define rWTDAT          (*(volatile unsigned *)0x15300004)
214#define rWTCNT          (*(volatile unsigned *)0x15300008)
215
216
217/* IIC */
218#define rIICCON         (*(volatile unsigned *)0x15400000)
219#define rIICSTAT        (*(volatile unsigned *)0x15400004)
220#define rIICADD         (*(volatile unsigned *)0x15400008)
221#define rIICDS          (*(volatile unsigned *)0x1540000C)
222
223
224/* IIS */
225#define rIISCON         (*(volatile unsigned *)0x15508000)
226#define rIISMOD         (*(volatile unsigned *)0x15508004)
227#define rIISPSR         (*(volatile unsigned *)0x15508008)
228#define rIISFIFCON      (*(volatile unsigned *)0x1550800C)
229
230#ifdef __BIG_ENDIAN
231#define IISFIF          ((volatile unsigned short *)0x15508012)
232
233#else /* Little Endian */
234#define IISFIF          ((volatile unsigned short *)0x15508010)
235#endif
236
237
238/* I/O PORT */
239#define rPACON          (*(volatile unsigned *)0x15600000)
240#define rPADAT          (*(volatile unsigned *)0x15600004)
241
242#define rPBCON          (*(volatile unsigned *)0x15600008)
243#define rPBDAT          (*(volatile unsigned *)0x1560000C)
244#define rPBUP           (*(volatile unsigned *)0x15600010)
245
246#define rPCCON          (*(volatile unsigned *)0x15600014)
247#define rPCDAT          (*(volatile unsigned *)0x15600018)
248#define rPCUP           (*(volatile unsigned *)0x1560001C)
249
250#define rPDCON          (*(volatile unsigned *)0x15600020)
251#define rPDDAT          (*(volatile unsigned *)0x15600024)
252#define rPDUP           (*(volatile unsigned *)0x15600028)
253
254#define rPECON          (*(volatile unsigned *)0x1560002C)
255#define rPEDAT          (*(volatile unsigned *)0x15600030)
256#define rPEUP           (*(volatile unsigned *)0x15600034)
257
258#define rPFCON          (*(volatile unsigned *)0x15600038)
259#define rPFDAT          (*(volatile unsigned *)0x1560003C)
260#define rPFUP           (*(volatile unsigned *)0x15600040)
261
262#define rPGCON          (*(volatile unsigned *)0x15600044)
263#define rPGDAT          (*(volatile unsigned *)0x15600048)
264#define rPGUP           (*(volatile unsigned *)0x1560004C)
265
266#define rOPENCR         (*(volatile unsigned *)0x15600050)
267#define rMISCCR         (*(volatile unsigned *)0x15600054)
268#define rEXTINT         (*(volatile unsigned *)0x15600058)
269
270
271/* RTC */
272#ifdef __BIG_ENDIAN
273#define rRTCCON         (*(volatile unsigned char *)0x15700043)
274#define rRTCALM         (*(volatile unsigned char *)0x15700053)
275#define rALMSEC         (*(volatile unsigned char *)0x15700057)
276#define rALMMIN         (*(volatile unsigned char *)0x1570005B)
277#define rALMHOUR        (*(volatile unsigned char *)0x1570005F)
278#define rALMDAY         (*(volatile unsigned char *)0x15700063)
279#define rALMMON         (*(volatile unsigned char *)0x15700067)
280#define rALMYEAR        (*(volatile unsigned char *)0x1570006B)
281#define rRTCRST         (*(volatile unsigned char *)0x1570006F)
282#define rBCDSEC         (*(volatile unsigned char *)0x15700073)
283#define rBCDMIN         (*(volatile unsigned char *)0x15700077)
284#define rBCDHOUR        (*(volatile unsigned char *)0x1570007B)
285#define rBCDDAY         (*(volatile unsigned char *)0x1570007F)
286#define rBCDDATE        (*(volatile unsigned char *)0x15700083)
287#define rBCDMON         (*(volatile unsigned char *)0x15700087)
288#define rBCDYEAR        (*(volatile unsigned char *)0x1570008B)
289#define rTICINT         (*(volatile unsigned char *)0x15700047)
290
291#else /* Little Endian */
292#define rRTCCON         (*(volatile unsigned char *)0x15700040)
293#define rRTCALM         (*(volatile unsigned char *)0x15700050)
294#define rALMSEC         (*(volatile unsigned char *)0x15700054)
295#define rALMMIN         (*(volatile unsigned char *)0x15700058)
296#define rALMHOUR        (*(volatile unsigned char *)0x1570005C)
297#define rALMDAY         (*(volatile unsigned char *)0x15700060)
298#define rALMMON         (*(volatile unsigned char *)0x15700064)
299#define rALMYEAR        (*(volatile unsigned char *)0x15700068)
300#define rRTCRST         (*(volatile unsigned char *)0x1570006C)
301#define rBCDSEC         (*(volatile unsigned char *)0x15700070)
302#define rBCDMIN         (*(volatile unsigned char *)0x15700074)
303#define rBCDHOUR        (*(volatile unsigned char *)0x15700078)
304#define rBCDDAY         (*(volatile unsigned char *)0x1570007C)
305#define rBCDDATE        (*(volatile unsigned char *)0x15700080)
306#define rBCDMON         (*(volatile unsigned char *)0x15700084)
307#define rBCDYEAR        (*(volatile unsigned char *)0x15700088)
308#define rTICINT         (*(volatile unsigned char *)0x15700044)
309#endif
310
311
312/* ADC */
313#define rADCCON         (*(volatile unsigned *)0x15800000)
314#define rADCDAT         (*(volatile unsigned *)0x15800004)
315
316
317/* SPI */
318#define rSPCON          (*(volatile unsigned *)0x15900000)
319#define rSPSTA          (*(volatile unsigned *)0x15900004)
320#define rSPPIN          (*(volatile unsigned *)0x15900008)
321#define rSPPRE          (*(volatile unsigned *)0x1590000C)
322#define rSPTDAT         (*(volatile unsigned *)0x15900010)
323#define rSPRDAT         (*(volatile unsigned *)0x15900014)
324
325
326/* MMC INTERFACE */
327#define rMMCON          (*(volatile unsigned *)0x15a00000)
328#define rMMCRR          (*(volatile unsigned *)0x15a00004)
329#define rMMFCON         (*(volatile unsigned *)0x15a00008)
330#define rMMSTA          (*(volatile unsigned *)0x15a0000C)
331#define rMMFSTA         (*(volatile unsigned *)0x15a00010)
332#define rMMPRE          (*(volatile unsigned *)0x15a00014)
333#define rMMLEN          (*(volatile unsigned *)0x15a00018)
334#define rMMCR7          (*(volatile unsigned *)0x15a0001C)
335#define rMMRSP0         (*(volatile unsigned *)0x15a00020)
336#define rMMRSP1         (*(volatile unsigned *)0x15a00024)
337#define rMMRSP2         (*(volatile unsigned *)0x15a00028)
338#define rMMRSP3         (*(volatile unsigned *)0x15a0002C)
339#define rMMCMD0         (*(volatile unsigned *)0x15a00030)
340#define rMMCMD1         (*(volatile unsigned *)0x15a00034)
341#define rMMCR16         (*(volatile unsigned *)0x15a00038)
342#define rMMDAT          (*(volatile unsigned *)0x15a0003C)
343
344
345#define _ISR_STARTADDRESS rtems_vector_table
346/* ISR */
347#define pISR_RESET      (*(unsigned *)(_ISR_STARTADDRESS+0x0))
348#define pISR_UNDEF      (*(unsigned *)(_ISR_STARTADDRESS+0x4))
349#define pISR_SWI        (*(unsigned *)(_ISR_STARTADDRESS+0x8))
350#define pISR_PABORT     (*(unsigned *)(_ISR_STARTADDRESS+0xC))
351#define pISR_DABORT     (*(unsigned *)(_ISR_STARTADDRESS+0x10))
352#define pISR_RESERVED   (*(unsigned *)(_ISR_STARTADDRESS+0x14))
353#define pISR_IRQ        (*(unsigned *)(_ISR_STARTADDRESS+0x18))
354#define pISR_FIQ        (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
355
356#define pISR_EINT0      (*(unsigned *)(_ISR_STARTADDRESS+0x20))
357#define pISR_EINT1      (*(unsigned *)(_ISR_STARTADDRESS+0x24))
358#define pISR_EINT2      (*(unsigned *)(_ISR_STARTADDRESS+0x28))
359#define pISR_EINT3      (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
360#define pISR_EINT4      (*(unsigned *)(_ISR_STARTADDRESS+0x30))
361#define pISR_EINT5      (*(unsigned *)(_ISR_STARTADDRESS+0x34))
362#define pISR_EINT6      (*(unsigned *)(_ISR_STARTADDRESS+0x38))
363#define pISR_EINT7      (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
364#define pISR_TICK       (*(unsigned *)(_ISR_STARTADDRESS+0x40))
365#define pISR_WDT        (*(unsigned *)(_ISR_STARTADDRESS+0x44))
366#define pISR_TIMER0     (*(unsigned *)(_ISR_STARTADDRESS+0x48))
367#define pISR_TIMER1     (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
368#define pISR_TIMER2     (*(unsigned *)(_ISR_STARTADDRESS+0x50))
369#define pISR_TIMER3     (*(unsigned *)(_ISR_STARTADDRESS+0x54))
370#define pISR_TIMER4     (*(unsigned *)(_ISR_STARTADDRESS+0x58))
371#define pISR_UERR01     (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
372#define pISR_NOTUSED    (*(unsigned *)(_ISR_STARTADDRESS+0x60))
373#define pISR_DMA0       (*(unsigned *)(_ISR_STARTADDRESS+0x64))
374#define pISR_DMA1       (*(unsigned *)(_ISR_STARTADDRESS+0x68))
375#define pISR_DMA2       (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
376#define pISR_DMA3       (*(unsigned *)(_ISR_STARTADDRESS+0x70))
377#define pISR_MMC        (*(unsigned *)(_ISR_STARTADDRESS+0x74))
378#define pISR_SPI        (*(unsigned *)(_ISR_STARTADDRESS+0x78))
379#define pISR_URXD0      (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
380#define pISR_URXD1      (*(unsigned *)(_ISR_STARTADDRESS+0x80))
381#define pISR_USBD       (*(unsigned *)(_ISR_STARTADDRESS+0x84))
382#define pISR_USBH       (*(unsigned *)(_ISR_STARTADDRESS+0x88))
383#define pISR_IIC        (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
384#define pISR_UTXD0      (*(unsigned *)(_ISR_STARTADDRESS+0x90))
385#define pISR_UTXD1      (*(unsigned *)(_ISR_STARTADDRESS+0x94))
386#define pISR_RTC        (*(unsigned *)(_ISR_STARTADDRESS+0x98))
387#define pISR_ADC        (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
388
389
390/* PENDING BIT */
391#define BIT_EINT0       (0x1)
392#define BIT_EINT1       (0x1<<1)
393#define BIT_EINT2       (0x1<<2)
394#define BIT_EINT3       (0x1<<3)
395#define BIT_EINT4       (0x1<<4)
396#define BIT_EINT5       (0x1<<5)
397#define BIT_EINT6       (0x1<<6)
398#define BIT_EINT7       (0x1<<7)
399#define BIT_TICK        (0x1<<8)
400#define BIT_WDT         (0x1<<9)
401#define BIT_TIMER0      (0x1<<10)
402#define BIT_TIMER1      (0x1<<11)
403#define BIT_TIMER2      (0x1<<12)
404#define BIT_TIMER3      (0x1<<13)
405#define BIT_TIMER4      (0x1<<14)
406#define BIT_UERR01      (0x1<<15)
407#define BIT_NOTUSED     (0x1<<16)
408#define BIT_DMA0        (0x1<<17)
409#define BIT_DMA1        (0x1<<18)
410#define BIT_DMA2        (0x1<<19)
411#define BIT_DMA3        (0x1<<20)
412#define BIT_MMC         (0x1<<21)
413#define BIT_SPI         (0x1<<22)
414#define BIT_URXD0       (0x1<<23)
415#define BIT_URXD1       (0x1<<24)
416#define BIT_USBD        (0x1<<25)
417#define BIT_USBH        (0x1<<26)
418#define BIT_IIC         (0x1<<27)
419#define BIT_UTXD0       (0x1<<28)
420#define BIT_UTXD1       (0x1<<29)
421#define BIT_RTC         (0x1<<30)
422#define BIT_ADC         (0x1<<31)
423#define BIT_ALLMSK      (0xFFFFFFFF)
424
425#define ClearPending(bit) {\
426                 rSRCPND = bit;\
427                 rINTPND = bit;\
428                 rINTPND;\
429                 }
430/* Wait until rINTPND is changed for the case that the ISR is very short. */
431
432#ifndef ASM
433/* Typedefs */
434typedef union {
435  struct _reg {
436    unsigned STOP_BIT:1;   /* Enters STOP mode. This bit isn't be */
437                           /*    cleared automatically. */
438    unsigned SL_IDLE:1;    /* SL_IDLE mode option. This bit isn't cleared */
439                           /*    automatically. To enter SL_IDLE mode, */
440                           /* CLKCON register has to be 0xe. */
441    unsigned IDLE_BIT:1;   /* Enters IDLE mode. This bit isn't be cleared */
442                           /*    automatically. */
443    unsigned LCDC:1;       /* Controls HCLK into LCDC block */
444    unsigned USB_host:1;   /* Controls HCLK into USB host block */
445    unsigned USB_device:1; /* Controls PCLK into USB device block */
446    unsigned PWMTIMER:1;   /* Controls PCLK into PWMTIMER block */
447    unsigned MMC:1;        /* Controls PCLK into MMC interface block */
448    unsigned UART0:1;      /* Controls PCLK into UART0 block */
449    unsigned UART1:1;      /* Controls PCLK into UART1 block */
450    unsigned GPIO:1;       /* Controls PCLK into GPIO block */
451    unsigned RTC:1;        /* Controls PCLK into RTC control block. Even if */
452                           /*   this bit is cleared to 0, RTC timer is alive. */
453    unsigned ADC:1;        /* Controls PCLK into ADC block */
454    unsigned IIC:1;        /* Controls PCLK into IIC block */
455    unsigned IIS:1;        /* Controls PCLK into IIS block */
456    unsigned SPI:1;        /* Controls PCLK into SPI block */
457  } reg;
458  unsigned long all;
459} CLKCON;
460
461typedef union
462{
463  struct {
464    unsigned ENVID:1;    /* LCD video output and the logic 1=enable/0=disable. */
465    unsigned BPPMODE:4;  /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */
466                         /*   1110 = 16 bpp TFT skipmode */
467    unsigned PNRMODE:2;  /* TFT: 3 */
468    unsigned MMODE:1;    /* This bit determines the toggle rate of the VM. */
469                         /*   0 = Each Frame, 1 = The rate defined by the MVAL */
470    unsigned CLKVAL:10;  /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */
471    unsigned LINECNT:10; /* (read only) These bits provide the status of the */
472                         /*   line counter. Down count from LINEVAL to 0 */
473  } reg;
474  unsigned long all;
475} LCDCON1;
476
477typedef union {
478  struct {
479    unsigned VSPW:6;    /* TFT: Vertical sync pulse width determines the */
480                        /*   VSYNC pulse's high level width by counting the */
481                        /*   number of inactive lines. */
482    unsigned VFPD:8;    /* TFT: Vertical front porch is the number of */
483                        /*   inactive lines at the end of a frame, before */
484                        /*   vertical synchronization period. */
485    unsigned LINEVAL:10;  /* TFT/STN: These bits determine the vertical size */
486                        /*   of LCD panel. */
487    unsigned VBPD:8;    /* TFT: Vertical back porch is the number of inactive */
488                        /*   lines at the start of a frame, after */
489                        /*   vertical synchronization period. */
490  } reg;
491  unsigned long all;
492} LCDCON2;
493
494typedef union {
495  struct {
496    unsigned HFPD:8;    /* TFT: Horizontal front porch is the number of */
497                        /*   VCLK periods between the end of active data */
498                        /*   and the rising edge of HSYNC. */
499    unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */
500                        /*   size of LCD panel. 2n bytes. */
501    unsigned HBPD:7;    /* TFT: Horizontal back porch is the number of VCLK */
502                        /*   periods between the falling edge of HSYNC and */
503                        /*   the start of active data. */
504  } reg;
505  unsigned long all;
506} LCDCON3;
507
508typedef union {
509  struct {
510    unsigned HSPW:8;     /* TFT: Horizontal sync pulse width determines the */
511                         /*   HSYNC pulse's high level width by counting the */
512                         /*   number of the VCLK. */
513    unsigned MVAL:8;     /* STN: */
514    unsigned ADDVAL:8;   /* TFT: Palette Index offset value */
515    unsigned PALADDEN:1; /* TFT: Palette Index offset enable. */
516                         /*   0 = Disable 1 = Enable */
517  } reg;
518  unsigned long all;
519} LCDCON4;
520
521typedef union {
522  struct {
523    unsigned HWSWP:1;     /* STN/TFT: Half-Word swap control bit. */
524                          /*    0 = Swap Disable 1 = Swap Enable */
525    unsigned BSWP:1;      /* STN/TFT: Byte swap control bit. */
526                          /*    0 = Swap Disable 1 = Swap Enable */
527    unsigned ENLEND:1;    /* TFT: LEND output signal enable/disable. */
528                          /*    0 = Disable LEND signal. */
529                          /*    1 = Enable LEND signal */
530    unsigned RESERVED1:1;
531    unsigned INVENDLINE:1;/* TFT: This bit indicates the LEND signal */
532                          /*    polarity. 0 = normal 1 = inverted */
533    unsigned RESERVED2:1;
534    unsigned INVVDEN:1;   /* TFT: This bit indicates the VDEN signal */
535                          /*    polarity. */
536                          /*    0 = normal 1 = inverted */
537    unsigned INVVD:1;     /* STN/TFT: This bit indicates the VD (video data) */
538                          /*    pulse polarity. 0 = Normal. */
539                          /*    1 = VD is inverted. */
540    unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */
541                          /*    pulse polarity. 0 = normal 1 = inverted */
542    unsigned INVVLINE:1;  /* STN/TFT: This bit indicates the VLINE/HSYNC */
543                          /*    pulse polarity. 0 = normal 1 = inverted */
544    unsigned INVVCLK:1;   /* STN/TFT: This bit controls the polarity of the */
545                          /*    VCLK active edge. 0 = The video data is */
546                          /*    fetched at VCLK falling edge. 1 = The video */
547                          /*    data is fetched at VCLK rising edge */
548    unsigned RESERVED3:2;
549    unsigned SELFREF:1;   /* STN: */
550    unsigned SLOWCLKSYNC:1; /* STN: */
551    unsigned RESERVED4:2; /* must be 0 */
552    unsigned HSTATUS:2;   /* TFT: Horizontal Status (Read only) */
553                          /*    00 = HSYNC */
554                          /*    01 = BACK Porch. */
555                          /*    10 = ACTIVE */
556                          /*    11 = FRONT Porch */
557    unsigned VSTATUS:2;   /* TFT: Vertical Status (Read only). */
558                          /*    00 = VSYNC */
559                          /*    01 = BACK Porch. */
560                          /*    10 = ACTIVE */
561                          /*    11 = FRONT Porch */
562  } reg;
563  unsigned long all;
564} LCDCON5;
565
566typedef union {
567  struct {
568    unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */
569                          /*    A[21:1] of the start address of the LCD */
570                          /*    frame buffer. */
571    unsigned LCDBANK:7;   /* A[28:22] */
572  } reg;
573  unsigned long all;
574} LCDSADDR1;
575
576typedef union {
577  struct {
578    unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/
579                          /*    of the end address of the LCD frame buffer. */
580                          /*    LCDBASEL = ((the fame end address) >>1) + 1 */
581                          /*    = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */
582  } reg;
583  unsigned long all;
584} LCDSADDR2;
585
586typedef union {
587  struct {
588    unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */
589                          /*    words) This value defines the width of the */
590                          /*    view port in the frame */
591    unsigned OFFSIZE:11;  /* Virtual screen offset size(the number of half */
592                          /*    words) This value defines the difference */
593                          /*    between the address of the last half word */
594                          /*    displayed on the previous LCD line and the */
595                          /*    address of the first half word to be */
596                          /*    displayed in the new LCD line. */
597  } reg;
598  unsigned long all;
599} LCDSADDR3;
600
601/*
602 *
603 */
604
605typedef union {
606  struct {
607    unsigned IISIFENA:1;  /* IIS interface enable (start) */
608    unsigned IISPSENA:1;  /* IIS prescaler enable */
609    unsigned RXCHIDLE:1;  /* Receive channel idle command */
610    unsigned TXCHIDLE:1;  /* Transmit channel idle command */
611    unsigned RXDMAENA:1;  /* Receive DMA service request enable */
612    unsigned TXDMAENA:1;  /* Transmit DMA service request enable */
613    unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */
614    unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */
615    unsigned LRINDEX:1;   /* Left/right channel index (read only) */
616  } reg;
617  unsigned long all;
618} IISCON;
619
620typedef union {
621  struct {
622    unsigned SBCLKFS:2;  /* Serial bit clock frequency select */
623    unsigned MCLKFS:1;   /* Master clock frequency select */
624    unsigned SDBITS:1;   /* Serial data bit per channel */
625    unsigned SIFMT:1;    /* Serial interface format */
626    unsigned ACTLEVCH:1; /* Active level pf left/right channel */
627    unsigned TXRXMODE:2; /* Transmit/receive mode select */
628    unsigned MODE:1;     /* Master/slave mode select */
629  } reg;
630  unsigned long all;
631} IISMOD;
632
633typedef union {
634  struct {
635    unsigned PSB:5;      /* Prescaler control B */
636    unsigned PSA:5;      /* Prescaler control A */
637  } reg;
638  unsigned long all;
639} IISPSR;
640
641typedef union {
642  struct {
643    unsigned RXFIFOCNT:4;  /* (read only) */
644    unsigned TXFIFOCNT:4;  /* (read only) */
645    /*signed RXFIFOENA:1;  /* */
646    unsigned TXFIFOENA:1;  /* */
647    unsigned RXFIFOMODE:1; /* */
648    unsigned TXFIFOMODE:1; /* */
649  } reg;
650  unsigned long all;
651} IISSFIFCON;
652
653typedef union {
654  struct {
655    unsigned FENTRY:16;    /* */
656  } reg;
657  unsigned long all;
658} IISSFIF;
659#endif //ASM
660
661#define LCD_WIDTH 240
662#define LCD_HEIGHT 320
663#define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT))
664
665#define GP32_KEY_SELECT 512
666#define GP32_KEY_START 256
667#define GP32_KEY_A 64
668#define GP32_KEY_B 32
669#define GP32_KEY_L 16
670#define GP32_KEY_R 128
671#define GP32_KEY_UP 8
672#define GP32_KEY_DOWN 2
673#define GP32_KEY_LEFT 1
674#define GP32_KEY_RIGHT 4
675
676#endif /*S3C2400_H_*/
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