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s3c2410.h @ dbdb0255

4.104.114.95

Last change on this file since dbdb0255 was dbdb0255, checked in by Joel Sherrill <joel.sherrill@…>, on 05/06/08 at 20:58:05

2008-05-06 Ray Xu <rayx.cn@…>

Makefile.am, configure.ac, preinstall.am, s3c2400/include/s3c2400.h: Add CPU type s3c2410. Add a new s3c24xx common file shared between s3c2400 and s3c2410. Most content is moved from s3c2400 now. Some were changed to include <s3c24xx.h> instead of <s3c2400.h>.
s3c2410/include/s3c2410.h, s3c2410/irq/bsp_irq_asm.S, s3c2410/irq/irq.h, s3c24xx/clock/clockdrv.c, s3c24xx/clock/support.c, s3c24xx/include/s3c24xx.h, s3c24xx/irq/bsp_irq_init.c, s3c24xx/irq/irq.c, s3c24xx/irq/irq.h, s3c24xx/timer/timer.c: New files.

Property mode set to 100644

File size: 41.4 KB

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1	/************************************************
2	* NAME : s3c2410.h
3	* Version : 3.7.2002
4	*
5	* Based on 24x.h for the Samsung Development Board
6	************************************************/
7
8	#ifndef S3C2410_H_
9	#define S3C2410_H_
10	/* Memory control */
11	#define rBWSCON ((volatile unsigned )0x48000000)
12	#define rBANKCON0 ((volatile unsigned )0x48000004)
13	#define rBANKCON1 ((volatile unsigned )0x48000008)
14	#define rBANKCON2 ((volatile unsigned )0x4800000C)
15	#define rBANKCON3 ((volatile unsigned )0x48000010)
16	#define rBANKCON4 ((volatile unsigned )0x48000014)
17	#define rBANKCON5 ((volatile unsigned )0x48000018)
18	#define rBANKCON6 ((volatile unsigned )0x4800001C)
19	#define rBANKCON7 ((volatile unsigned )0x48000020)
20	#define rREFRESH ((volatile unsigned )0x48000024)
21	#define rBANKSIZE ((volatile unsigned )0x48000028)
22	#define rMRSRB6 ((volatile unsigned )0x4800002C)
23	#define rMRSRB7 ((volatile unsigned )0x48000030)
24
25	/* USB Host Controller */
26	#define rHcRevision ((volatile unsigned )0x49000000)
27	#define rHcControl ((volatile unsigned )0x49000004)
28	#define rHcCommonStatus ((volatile unsigned )0x49000008)
29	#define rHcInterruptStatus ((volatile unsigned )0x4900000C)
30	#define rHcInterruptEnable ((volatile unsigned )0x49000010)
31	#define rHcInterruptDisable ((volatile unsigned )0x49000014)
32	#define rHcHCCA ((volatile unsigned )0x49000018)
33	#define rHcPeriodCuttendED ((volatile unsigned )0x4900001C)
34	#define rHcControlHeadED ((volatile unsigned )0x49000020)
35	#define rHcControlCurrentED ((volatile unsigned )0x49000024)
36	#define rHcBulkHeadED ((volatile unsigned )0x49000028)
37	#define rHcBuldCurrentED ((volatile unsigned )0x4900002C)
38	#define rHcDoneHead ((volatile unsigned )0x49000030)
39	#define rHcRmInterval ((volatile unsigned )0x49000034)
40	#define rHcFmRemaining ((volatile unsigned )0x49000038)
41	#define rHcFmNumber ((volatile unsigned )0x4900003C)
42	#define rHcPeriodicStart ((volatile unsigned )0x49000040)
43	#define rHcLSThreshold ((volatile unsigned )0x49000044)
44	#define rHcRhDescriptorA ((volatile unsigned )0x49000048)
45	#define rHcRhDescriptorB ((volatile unsigned )0x4900004C)
46	#define rHcRhStatus ((volatile unsigned )0x49000050)
47	#define rHcRhPortStatus1 ((volatile unsigned )0x49000054)
48	#define rHcRhPortStatus2 ((volatile unsigned )0x49000058)
49
50	/* INTERRUPT */
51	#define rSRCPND ((volatile unsigned )0x4A000000)
52	#define rINTMOD ((volatile unsigned )0x4A000004)
53	#define rINTMSK ((volatile unsigned )0x4A000008)
54	#define rPRIORITY ((volatile unsigned )0x4A00000C)
55	#define rINTPND ((volatile unsigned )0x4A000010)
56	#define rINTOFFSET ((volatile unsigned )0x4A000014)
57	#define rSUBSRCPND ((volatile unsigned )0x4A000018)
58	#define rINTSUBMSK ((volatile unsigned )0x4A00001c)
59
60
61	/* DMA */
62	#define rDISRC0 ((volatile unsigned )0x4B000000)
63	#define rDISRCC0 ((volatile unsigned )0x4B000004)
64	#define rDIDST0 ((volatile unsigned )0x4B000008)
65	#define rDIDSTC0 ((volatile unsigned )0x4B00000C)
66	#define rDCON0 ((volatile unsigned )0x4B000010)
67	#define rDSTAT0 ((volatile unsigned )0x4B000014)
68	#define rDCSRC0 ((volatile unsigned )0x4B000018)
69	#define rDCDST0 ((volatile unsigned )0x4B00001C)
70	#define rDMASKTRIG0 ((volatile unsigned )0x4B000020)
71	#define rDISRC1 ((volatile unsigned )0x4B000040)
72	#define rDISRCC1 ((volatile unsigned )0x4B000044)
73	#define rDIDST1 ((volatile unsigned )0x4B000048)
74	#define rDIDSTC1 ((volatile unsigned )0x4B00004C)
75	#define rDCON1 ((volatile unsigned )0x4B000050)
76	#define rDSTAT1 ((volatile unsigned )0x4B000054)
77	#define rDCSRC1 ((volatile unsigned )0x4B000058)
78	#define rDCDST1 ((volatile unsigned )0x4B00005C)
79	#define rDMASKTRIG1 ((volatile unsigned )0x4B000060)
80	#define rDISRC2 ((volatile unsigned )0x4B000080)
81	#define rDISRCC2 ((volatile unsigned )0x4B000084)
82	#define rDIDST2 ((volatile unsigned )0x4B000088)
83	#define rDIDSTC2 ((volatile unsigned )0x4B00008C)
84	#define rDCON2 ((volatile unsigned )0x4B000090)
85	#define rDSTAT2 ((volatile unsigned )0x4B000094)
86	#define rDCSRC2 ((volatile unsigned )0x4B000098)
87	#define rDCDST2 ((volatile unsigned )0x4B00009C)
88	#define rDMASKTRIG2 ((volatile unsigned )0x4B0000A0)
89	#define rDISRC3 ((volatile unsigned )0x4B0000C0)
90	#define rDISRCC3 ((volatile unsigned )0x4B0000C4)
91	#define rDIDST3 ((volatile unsigned )0x4B0000C8)
92	#define rDIDSTC3 ((volatile unsigned )0x4B0000CC)
93	#define rDCON3 ((volatile unsigned )0x4B0000D0)
94	#define rDSTAT3 ((volatile unsigned )0x4B0000D4)
95	#define rDCSRC3 ((volatile unsigned )0x4B0000D8)
96	#define rDCDST3 ((volatile unsigned )0x4B0000DC)
97	#define rDMASKTRIG3 ((volatile unsigned )0x4B0000E0)
98
99
100	/* CLOCK & POWER MANAGEMENT */
101	#define rLOCKTIME ((volatile unsigned )0x4C000000)
102	#define rMPLLCON ((volatile unsigned )0x4C000004)
103	#define rUPLLCON ((volatile unsigned )0x4C000008)
104	#define rCLKCON ((volatile unsigned )0x4C00000C)
105	#define rCLKSLOW ((volatile unsigned )0x4C000010)
106	#define rCLKDIVN ((volatile unsigned )0x4C000014)
107
108
109	/* LCD CONTROLLER */
110	#define rLCDCON1 ((volatile unsigned )0x4D000000)
111	#define rLCDCON2 ((volatile unsigned )0x4D000004)
112	#define rLCDCON3 ((volatile unsigned )0x4D000008)
113	#define rLCDCON4 ((volatile unsigned )0x4D00000C)
114	#define rLCDCON5 ((volatile unsigned )0x4D000010)
115	#define rLCDSADDR1 ((volatile unsigned )0x4D000014)
116	#define rLCDSADDR2 ((volatile unsigned )0x4D000018)
117	#define rLCDSADDR3 ((volatile unsigned )0x4D00001C)
118	#define rREDLUT ((volatile unsigned )0x4D000020)
119	#define rGREENLUT ((volatile unsigned )0x4D000024)
120	#define rBLUELUT ((volatile unsigned )0x4D000028)
121	#define rREDLUT ((volatile unsigned )0x4D000020)
122	#define rGREENLUT ((volatile unsigned )0x4D000024)
123	#define rBLUELUT ((volatile unsigned )0x4D000028)
124	#define rDITHMODE ((volatile unsigned )0x4D00004C)
125	#define rTPAL ((volatile unsigned )0x4D000050)
126	#define rLCDINTPND ((volatile unsigned )0x4D000054)
127	#define rLCDSRCPND ((volatile unsigned )0x4D000058)
128	#define rLCDINTMSK ((volatile unsigned )0x4D00005C)
129	#define rTCONSEL ((volatile unsigned )0x4D000060)
130	#define PALETTE 0x4d000400
131
132	/* NAND Flash */
133	#define rNFCONF ((volatile unsigned )0x4E000000)
134	#define rNFCMD ((volatile unsigned )0x4E000004)
135	#define rNFADDR ((volatile unsigned )0x4E000008)
136	#define rNFDATA ((volatile unsigned )0x4E00000C)
137	#define rNFSTAT ((volatile unsigned )0x4E000010)
138	#define rNFECC ((volatile unsigned )0x4E000014)
139
140	/* UART */
141	#define rULCON0 ((volatile unsigned char )0x50000000)
142	#define rUCON0 ((volatile unsigned short )0x50000004)
143	#define rUFCON0 ((volatile unsigned char )0x50000008)
144	#define rUMCON0 ((volatile unsigned char )0x5000000C)
145	#define rUTRSTAT0 ((volatile unsigned char )0x50000010)
146	#define rUERSTAT0 ((volatile unsigned char )0x50000014)
147	#define rUFSTAT0 ((volatile unsigned short )0x50000018)
148	#define rUMSTAT0 ((volatile unsigned char )0x5000001C)
149	#define rUBRDIV0 ((volatile unsigned short )0x50000028)
150
151	#define rULCON1 ((volatile unsigned char )0x50004000)
152	#define rUCON1 ((volatile unsigned short )0x50004004)
153	#define rUFCON1 ((volatile unsigned char )0x50004008)
154	#define rUMCON1 ((volatile unsigned char )0x5000400C)
155	#define rUTRSTAT1 ((volatile unsigned char )0x50004010)
156	#define rUERSTAT1 ((volatile unsigned char )0x50004014)
157	#define rUFSTAT1 ((volatile unsigned short )0x50004018)
158	#define rUMSTAT1 ((volatile unsigned char )0x5000401C)
159	#define rUBRDIV1 ((volatile unsigned short )0x50004028)
160
161	#define rULCON2 ((volatile unsigned char )0x50008000)
162	#define rUCON2 ((volatile unsigned short )0x50008004)
163	#define rUFCON2 ((volatile unsigned char )0x50008008)
164	#define rUTRSTAT2 ((volatile unsigned char )0x50008010)
165	#define rUERSTAT2 ((volatile unsigned char )0x50008014)
166	#define rUFSTAT2 ((volatile unsigned short )0x50008018)
167	#define rUBRDIV2 ((volatile unsigned short )0x50008028)
168
169	#ifdef __BIG_ENDIAN
170	#define rUTXH0 ((volatile unsigned char )0x50000023)
171	#define rURXH0 ((volatile unsigned char )0x50000027)
172	#define rUTXH1 ((volatile unsigned char )0x50004023)
173	#define rURXH1 ((volatile unsigned char )0x50004027)
174	#define rUTXH2 ((volatile unsigned char )0x50008023)
175	#define rURXH2 ((volatile unsigned char )0x50008027)
176
177	#define WrUTXH0(ch) ((volatile unsigned char )0x50000023)=(unsigned char)(ch)
178	#define RdURXH0() ((volatile unsigned char )0x50000027)
179	#define WrUTXH1(ch) ((volatile unsigned char )0x50004023)=(unsigned char)(ch)
180	#define RdURXH1() ((volatile unsigned char )0x50004027)
181	#define WrUTXH2(ch) ((volatile unsigned char )0x50008023)=(unsigned char)(ch)
182	#define RdURXH2() ((volatile unsigned char )0x50008027)
183
184	#define UTXH0 (0x50000020+3) /* byte_access address by DMA */
185	#define URXH0 (0x50000024+3)
186	#define UTXH1 (0x50004020+3)
187	#define URXH1 (0x50004024+3)
188	#define UTXH2 (0x50008020+3)
189	#define URXH2 (0x50008024+3)
190
191	#else /* Little Endian */
192	#define rUTXH0 ((volatile unsigned char )0x50000020)
193	#define rURXH0 ((volatile unsigned char )0x50000024)
194	#define rUTXH1 ((volatile unsigned char )0x50004020)
195	#define rURXH1 ((volatile unsigned char )0x50004024)
196	#define rUTXH2 ((volatile unsigned char )0x50008020)
197	#define rURXH2 ((volatile unsigned char )0x50008024)
198
199	#define WrUTXH0(ch) ((volatile unsigned char )0x50000020)=(unsigned char)(ch)
200	#define RdURXH0() ((volatile unsigned char )0x50000024)
201	#define WrUTXH1(ch) ((volatile unsigned char )0x50004020)=(unsigned char)(ch)
202	#define RdURXH1() ((volatile unsigned char )0x50004024)
203	#define WrUTXH2(ch) ((volatile unsigned char )0x50008020)=(unsigned char)(ch)
204	#define RdURXH2() ((volatile unsigned char )0x50008024)
205
206	#define UTXH0 (0x50000020)
207	#define URXH0 (0x50000024)
208	#define UTXH1 (0x50004020)
209	#define URXH1 (0x50004024)
210	#define UTXH2 (0x50008020)
211	#define URXH2 (0x50008024)
212	#endif
213
214
215	/* PWM TIMER */
216	#define rTCFG0 ((volatile unsigned )0x51000000)
217	#define rTCFG1 ((volatile unsigned )0x51000004)
218	#define rTCON ((volatile unsigned )0x51000008)
219	#define rTCNTB0 ((volatile unsigned )0x5100000C)
220	#define rTCMPB0 ((volatile unsigned )0x51000010)
221	#define rTCNTO0 ((volatile unsigned )0x51000014)
222	#define rTCNTB1 ((volatile unsigned )0x51000018)
223	#define rTCMPB1 ((volatile unsigned )0x5100001C)
224	#define rTCNTO1 ((volatile unsigned )0x51000020)
225	#define rTCNTB2 ((volatile unsigned )0x51000024)
226	#define rTCMPB2 ((volatile unsigned )0x51000028)
227	#define rTCNTO2 ((volatile unsigned )0x5100002C)
228	#define rTCNTB3 ((volatile unsigned )0x51000030)
229	#define rTCMPB3 ((volatile unsigned )0x51000034)
230	#define rTCNTO3 ((volatile unsigned )0x51000038)
231	#define rTCNTB4 ((volatile unsigned )0x5100003C)
232	#define rTCNTO4 ((volatile unsigned )0x51000040)
233
234
235	/* USB DEVICE */
236	#ifdef __BIG_ENDIAN
237	#define rFUNC_ADDR_REG ((volatile unsigned char )0x52000143) //Function address
238	#define rPWR_REG ((volatile unsigned char )0x52000147) //Power management
239	#define rEP_INT_REG ((volatile unsigned char )0x5200014b) //EP Interrupt pending and clear
240	#define rUSB_INT_REG ((volatile unsigned char )0x5200015b) //USB Interrupt pending and clear
241	#define rEP_INT_EN_REG ((volatile unsigned char )0x5200015f) //Interrupt enable
242	#define rUSB_INT_EN_REG ((volatile unsigned char )0x5200016f)
243	#define rFRAME_NUM1_REG ((volatile unsigned char )0x52000173) //Frame number lower byte
244	#define rFRAME_NUM2_REG ((volatile unsigned char )0x52000177) //Frame number higher byte
245	#define rINDEX_REG ((volatile unsigned char )0x5200017b) //Register index
246	#define rMAXP_REG ((volatile unsigned char )0x52000183) //Endpoint max packet
247	#define rEP0_CSR ((volatile unsigned char )0x52000187) //Endpoint 0 status
248	#define rIN_CSR1_REG ((volatile unsigned char )0x52000187) //In endpoint control status
249	#define rIN_CSR2_REG ((volatile unsigned char )0x5200018b)
250	#define rOUT_CSR1_REG ((volatile unsigned char )0x52000193) //Out endpoint control status
251	#define rOUT_CSR2_REG ((volatile unsigned char )0x52000197)
252	#define rOUT_FIFO_CNT1_REG ((volatile unsigned char )0x5200019b) //Endpoint out write count
253	#define rOUT_FIFO_CNT2_REG ((volatile unsigned char )0x5200019f)
254	#define rEP0_FIFO ((volatile unsigned char )0x520001c3) //Endpoint 0 FIFO
255	#define rEP1_FIFO ((volatile unsigned char )0x520001c7) //Endpoint 1 FIFO
256	#define rEP2_FIFO ((volatile unsigned char )0x520001cb) //Endpoint 2 FIFO
257	#define rEP3_FIFO ((volatile unsigned char )0x520001cf) //Endpoint 3 FIFO
258	#define rEP4_FIFO ((volatile unsigned char )0x520001d3) //Endpoint 4 FIFO
259	#define rEP1_DMA_CON ((volatile unsigned char )0x52000203) //EP1 DMA interface control
260	#define rEP1_DMA_UNIT ((volatile unsigned char )0x52000207) //EP1 DMA Tx unit counter
261	#define rEP1_DMA_FIFO ((volatile unsigned char )0x5200020b) //EP1 DMA Tx FIFO counter
262	#define rEP1_DMA_TTC_L ((volatile unsigned char )0x5200020f) //EP1 DMA total Tx counter
263	#define rEP1_DMA_TTC_M ((volatile unsigned char )0x52000213)
264	#define rEP1_DMA_TTC_H ((volatile unsigned char )0x52000217)
265	#define rEP2_DMA_CON ((volatile unsigned char )0x5200021b) //EP2 DMA interface control
266	#define rEP2_DMA_UNIT ((volatile unsigned char )0x5200021f) //EP2 DMA Tx unit counter
267	#define rEP2_DMA_FIFO ((volatile unsigned char )0x52000223) //EP2 DMA Tx FIFO counter
268	#define rEP2_DMA_TTC_L ((volatile unsigned char )0x52000227) //EP2 DMA total Tx counter
269	#define rEP2_DMA_TTC_M ((volatile unsigned char )0x5200022b)
270	#define rEP2_DMA_TTC_H ((volatile unsigned char )0x5200022f)
271	#define rEP3_DMA_CON ((volatile unsigned char )0x52000243) //EP3 DMA interface control
272	#define rEP3_DMA_UNIT ((volatile unsigned char )0x52000247) //EP3 DMA Tx unit counter
273	#define rEP3_DMA_FIFO ((volatile unsigned char )0x5200024b) //EP3 DMA Tx FIFO counter
274	#define rEP3_DMA_TTC_L ((volatile unsigned char )0x5200024f) //EP3 DMA total Tx counter
275	#define rEP3_DMA_TTC_M ((volatile unsigned char )0x52000253)
276	#define rEP3_DMA_TTC_H ((volatile unsigned char )0x52000257)
277	#define rEP4_DMA_CON ((volatile unsigned char )0x5200025b) //EP4 DMA interface control
278	#define rEP4_DMA_UNIT ((volatile unsigned char )0x5200025f) //EP4 DMA Tx unit counter
279	#define rEP4_DMA_FIFO ((volatile unsigned char )0x52000263) //EP4 DMA Tx FIFO counter
280	#define rEP4_DMA_TTC_L ((volatile unsigned char )0x52000267) //EP4 DMA total Tx counter
281	#define rEP4_DMA_TTC_M ((volatile unsigned char )0x5200026b)
282	#define rEP4_DMA_TTC_H ((volatile unsigned char )0x5200026f)
283
284	#else // Little Endian
285	#define rFUNC_ADDR_REG ((volatile unsigned char )0x52000140) //Function address
286	#define rPWR_REG ((volatile unsigned char )0x52000144) //Power management
287	#define rEP_INT_REG ((volatile unsigned char )0x52000148) //EP Interrupt pending and clear
288	#define rUSB_INT_REG ((volatile unsigned char )0x52000158) //USB Interrupt pending and clear
289	#define rEP_INT_EN_REG ((volatile unsigned char )0x5200015c) //Interrupt enable
290	#define rUSB_INT_EN_REG ((volatile unsigned char )0x5200016c)
291	#define rFRAME_NUM1_REG ((volatile unsigned char )0x52000170) //Frame number lower byte
292	#define rFRAME_NUM2_REG ((volatile unsigned char )0x52000174) //Frame number higher byte
293	#define rINDEX_REG ((volatile unsigned char )0x52000178) //Register index
294	#define rMAXP_REG ((volatile unsigned char )0x52000180) //Endpoint max packet
295	#define rEP0_CSR ((volatile unsigned char )0x52000184) //Endpoint 0 status
296	#define rIN_CSR1_REG ((volatile unsigned char )0x52000184) //In endpoint control status
297	#define rIN_CSR2_REG ((volatile unsigned char )0x52000188)
298	#define rOUT_CSR1_REG ((volatile unsigned char )0x52000190) //Out endpoint control status
299	#define rOUT_CSR2_REG ((volatile unsigned char )0x52000194)
300	#define rOUT_FIFO_CNT1_REG ((volatile unsigned char )0x52000198) //Endpoint out write count
301	#define rOUT_FIFO_CNT2_REG ((volatile unsigned char )0x5200019c)
302	#define rEP0_FIFO ((volatile unsigned char )0x520001c0) //Endpoint 0 FIFO
303	#define rEP1_FIFO ((volatile unsigned char )0x520001c4) //Endpoint 1 FIFO
304	#define rEP2_FIFO ((volatile unsigned char )0x520001c8) //Endpoint 2 FIFO
305	#define rEP3_FIFO ((volatile unsigned char )0x520001cc) //Endpoint 3 FIFO
306	#define rEP4_FIFO ((volatile unsigned char )0x520001d0) //Endpoint 4 FIFO
307	#define rEP1_DMA_CON ((volatile unsigned char )0x52000200) //EP1 DMA interface control
308	#define rEP1_DMA_UNIT ((volatile unsigned char )0x52000204) //EP1 DMA Tx unit counter
309	#define rEP1_DMA_FIFO ((volatile unsigned char )0x52000208) //EP1 DMA Tx FIFO counter
310	#define rEP1_DMA_TTC_L ((volatile unsigned char )0x5200020c) //EP1 DMA total Tx counter
311	#define rEP1_DMA_TTC_M ((volatile unsigned char )0x52000210)
312	#define rEP1_DMA_TTC_H ((volatile unsigned char )0x52000214)
313	#define rEP2_DMA_CON ((volatile unsigned char )0x52000218) //EP2 DMA interface control
314	#define rEP2_DMA_UNIT ((volatile unsigned char )0x5200021c) //EP2 DMA Tx unit counter
315	#define rEP2_DMA_FIFO ((volatile unsigned char )0x52000220) //EP2 DMA Tx FIFO counter
316	#define rEP2_DMA_TTC_L ((volatile unsigned char )0x52000224) //EP2 DMA total Tx counter
317	#define rEP2_DMA_TTC_M ((volatile unsigned char )0x52000228)
318	#define rEP2_DMA_TTC_H ((volatile unsigned char )0x5200022c)
319	#define rEP3_DMA_CON ((volatile unsigned char )0x52000240) //EP3 DMA interface control
320	#define rEP3_DMA_UNIT ((volatile unsigned char )0x52000244) //EP3 DMA Tx unit counter
321	#define rEP3_DMA_FIFO ((volatile unsigned char )0x52000248) //EP3 DMA Tx FIFO counter
322	#define rEP3_DMA_TTC_L ((volatile unsigned char )0x5200024c) //EP3 DMA total Tx counter
323	#define rEP3_DMA_TTC_M ((volatile unsigned char )0x52000250)
324	#define rEP3_DMA_TTC_H ((volatile unsigned char )0x52000254)
325	#define rEP4_DMA_CON ((volatile unsigned char )0x52000258) //EP4 DMA interface control
326	#define rEP4_DMA_UNIT ((volatile unsigned char )0x5200025c) //EP4 DMA Tx unit counter
327	#define rEP4_DMA_FIFO ((volatile unsigned char )0x52000260) //EP4 DMA Tx FIFO counter
328	#define rEP4_DMA_TTC_L ((volatile unsigned char )0x52000264) //EP4 DMA total Tx counter
329	#define rEP4_DMA_TTC_M ((volatile unsigned char )0x52000268)
330	#define rEP4_DMA_TTC_H ((volatile unsigned char )0x5200026c)
331	#endif // __BIG_ENDIAN
332
333	/* WATCH DOG TIMER */
334	#define rWTCON ((volatile unsigned )0x53000000)
335	#define rWTDAT ((volatile unsigned )0x53000004)
336	#define rWTCNT ((volatile unsigned )0x53000008)
337
338
339	/* IIC */
340	#define rIICCON ((volatile unsigned )0x54000000)
341	#define rIICSTAT ((volatile unsigned )0x54000004)
342	#define rIICADD ((volatile unsigned )0x54000008)
343	#define rIICDS ((volatile unsigned )0x5400000C)
344
345
346	/* IIS */
347	#define rIISCON ((volatile unsigned )0x55000000)
348	#define rIISMOD ((volatile unsigned )0x55000004)
349	#define rIISPSR ((volatile unsigned )0x55000008)
350	#define rIISFIFCON ((volatile unsigned )0x5500000C)
351
352	#ifdef __BIG_ENDIAN
353	#define IISFIFO ((volatile unsigned short *)0x55000012)
354
355	#else /* Little Endian */
356	#define IISFIFO ((volatile unsigned short *)0x55000010)
357	#endif
358
359
360	/* I/O PORT */
361	#define rGPACON ((volatile unsigned )0x56000000) //Port A control
362	#define rGPADAT ((volatile unsigned )0x56000004) //Port A data
363
364	#define rGPBCON ((volatile unsigned )0x56000010) //Port B control
365	#define rGPBDAT ((volatile unsigned )0x56000014) //Port B data
366	#define rGPBUP ((volatile unsigned )0x56000018) //Pull-up control B
367
368	#define rGPCCON ((volatile unsigned )0x56000020) //Port C control
369	#define rGPCDAT ((volatile unsigned )0x56000024) //Port C data
370	#define rGPCUP ((volatile unsigned )0x56000028) //Pull-up control C
371
372	#define rGPDCON ((volatile unsigned )0x56000030) //Port D control
373	#define rGPDDAT ((volatile unsigned )0x56000034) //Port D data
374	#define rGPDUP ((volatile unsigned )0x56000038) //Pull-up control D
375
376	#define rGPECON ((volatile unsigned )0x56000040) //Port E control
377	#define rGPEDAT ((volatile unsigned )0x56000044) //Port E data
378	#define rGPEUP ((volatile unsigned )0x56000048) //Pull-up control E
379
380	#define rGPFCON ((volatile unsigned )0x56000050) //Port F control
381	#define rGPFDAT ((volatile unsigned )0x56000054) //Port F data
382	#define rGPFUP ((volatile unsigned )0x56000058) //Pull-up control F
383
384	#define rGPGCON ((volatile unsigned )0x56000060) //Port G control
385	#define rGPGDAT ((volatile unsigned )0x56000064) //Port G data
386	#define rGPGUP ((volatile unsigned )0x56000068) //Pull-up control G
387
388	#define rGPHCON ((volatile unsigned )0x56000070) //Port H control
389	#define rGPHDAT ((volatile unsigned )0x56000074) //Port H data
390	#define rGPHUP ((volatile unsigned )0x56000078) //Pull-up control H
391
392	#define rMISCCR ((volatile unsigned )0x56000080) //Miscellaneous control
393	#define rDCLKCON ((volatile unsigned )0x56000084) //DCLK0/1 control
394	#define rEXTINT0 ((volatile unsigned )0x56000088) //External interrupt control register 0
395	#define rEXTINT1 ((volatile unsigned )0x5600008c) //External interrupt control register 1
396	#define rEXTINT2 ((volatile unsigned )0x56000090) //External interrupt control register 2
397	#define rEINTFLT0 ((volatile unsigned )0x56000094) //Reserved
398	#define rEINTFLT1 ((volatile unsigned )0x56000098) //Reserved
399	#define rEINTFLT2 ((volatile unsigned )0x5600009c) //External interrupt filter control register 2
400	#define rEINTFLT3 ((volatile unsigned )0x560000a0) //External interrupt filter control register 3
401	#define rEINTMASK ((volatile unsigned )0x560000a4) //External interrupt mask
402	#define rEINTPEND ((volatile unsigned )0x560000a8) //External interrupt pending
403	#define rGSTATUS0 ((volatile unsigned )0x560000ac) //External pin status
404	#define rGSTATUS1 ((volatile unsigned )0x560000b0) //Chip ID(0x32440000)
405
406	/* RTC */
407	#ifdef __BIG_ENDIAN
408	#define rRTCCON ((volatile unsigned char )0x57000043) //RTC control
409	#define rTICNT ((volatile unsigned char )0x57000047) //Tick time count
410	#define rRTCALM ((volatile unsigned char )0x57000053) //RTC alarm control
411	#define rALMSEC ((volatile unsigned char )0x57000057) //Alarm second
412	#define rALMMIN ((volatile unsigned char )0x5700005b) //Alarm minute
413	#define rALMHOUR ((volatile unsigned char )0x5700005f) //Alarm Hour
414	#define rALMDATE ((volatile unsigned char )0x57000063) //Alarm date //edited by junon
415	#define rALMMON ((volatile unsigned char )0x57000067) //Alarm month
416	#define rALMYEAR ((volatile unsigned char )0x5700006b) //Alarm year
417	#define rRTCRST ((volatile unsigned char )0x5700006f) //RTC round reset
418	#define rBCDSEC ((volatile unsigned char )0x57000073) //BCD second
419	#define rBCDMIN ((volatile unsigned char )0x57000077) //BCD minute
420	#define rBCDHOUR ((volatile unsigned char )0x5700007b) //BCD hour
421	#define rBCDDATE ((volatile unsigned char )0x5700007f) //BCD date //edited by junon
422	#define rBCDDAY ((volatile unsigned char )0x57000083) //BCD day //edited by junon
423	#define rBCDMON ((volatile unsigned char )0x57000087) //BCD month
424	#define rBCDYEAR ((volatile unsigned char )0x5700008b) //BCD year
425
426	#else //Little Endian
427	#define rRTCCON ((volatile unsigned char )0x57000040) //RTC control
428	#define rTICNT ((volatile unsigned char )0x57000044) //Tick time count
429	#define rRTCALM ((volatile unsigned char )0x57000050) //RTC alarm control
430	#define rALMSEC ((volatile unsigned char )0x57000054) //Alarm second
431	#define rALMMIN ((volatile unsigned char )0x57000058) //Alarm minute
432	#define rALMHOUR ((volatile unsigned char )0x5700005c) //Alarm Hour
433	#define rALMDATE ((volatile unsigned char )0x57000060) //Alarm date // edited by junon
434	#define rALMMON ((volatile unsigned char )0x57000064) //Alarm month
435	#define rALMYEAR ((volatile unsigned char )0x57000068) //Alarm year
436	#define rRTCRST ((volatile unsigned char )0x5700006c) //RTC round reset
437	#define rBCDSEC ((volatile unsigned char )0x57000070) //BCD second
438	#define rBCDMIN ((volatile unsigned char )0x57000074) //BCD minute
439	#define rBCDHOUR ((volatile unsigned char )0x57000078) //BCD hour
440	#define rBCDDATE ((volatile unsigned char )0x5700007c) //BCD date //edited by junon
441	#define rBCDDAY ((volatile unsigned char )0x57000080) //BCD day //edited by junon
442	#define rBCDMON ((volatile unsigned char )0x57000084) //BCD month
443	#define rBCDYEAR ((volatile unsigned char )0x57000088) //BCD year
444	#endif //RTC
445
446
447	/* ADC */
448	#define rADCCON ((volatile unsigned )0x58000000)
449	#define rADCTSC ((volatile unsigned )0x58000004)
450	#define rADCDLY ((volatile unsigned )0x58000008)
451	#define rADCDAT0 ((volatile unsigned )0x5800000c)
452	#define rADCDAT1 ((volatile unsigned )0x58000010)
453
454
455	/* SPI */
456	#define rSPCON0 ((volatile unsigned )0x59000000) //SPI0 control
457	#define rSPSTA0 ((volatile unsigned )0x59000004) //SPI0 status
458	#define rSPPIN0 ((volatile unsigned )0x59000008) //SPI0 pin control
459	#define rSPPRE0 ((volatile unsigned )0x5900000c) //SPI0 baud rate prescaler
460	#define rSPTDAT0 ((volatile unsigned )0x59000010) //SPI0 Tx data
461	#define rSPRDAT0 ((volatile unsigned )0x59000014) //SPI0 Rx data
462
463	#define rSPCON1 ((volatile unsigned )0x59000020) //SPI1 control
464	#define rSPSTA1 ((volatile unsigned )0x59000024) //SPI1 status
465	#define rSPPIN1 ((volatile unsigned )0x59000028) //SPI1 pin control
466	#define rSPPRE1 ((volatile unsigned )0x5900002c) //SPI1 baud rate prescaler
467	#define rSPTDAT1 ((volatile unsigned )0x59000030) //SPI1 Tx data
468	#define rSPRDAT1 ((volatile unsigned )0x59000034) //SPI1 Rx data
469
470	/* SD interface */
471	#define rSDICON ((volatile unsigned )0x5a000000) //SDI control
472	#define rSDIPRE ((volatile unsigned )0x5a000004) //SDI baud rate prescaler
473	#define rSDICARG ((volatile unsigned )0x5a000008) //SDI command argument
474	#define rSDICCON ((volatile unsigned )0x5a00000c) //SDI command control
475	#define rSDICSTA ((volatile unsigned )0x5a000010) //SDI command status
476	#define rSDIRSP0 ((volatile unsigned )0x5a000014) //SDI response 0
477	#define rSDIRSP1 ((volatile unsigned )0x5a000018) //SDI response 1
478	#define rSDIRSP2 ((volatile unsigned )0x5a00001c) //SDI response 2
479	#define rSDIRSP3 ((volatile unsigned )0x5a000020) //SDI response 3
480	#define rSDIDTIMER ((volatile unsigned )0x5a000024) //SDI data/busy timer
481	#define rSDIBSIZE ((volatile unsigned )0x5a000028) //SDI block size
482	#define rSDIDATCON ((volatile unsigned )0x5a00002c) //SDI data control
483	#define rSDIDATCNT ((volatile unsigned )0x5a000030) //SDI data remain counter
484	#define rSDIDATSTA ((volatile unsigned )0x5a000034) //SDI data status
485	#define rSDIFSTA ((volatile unsigned )0x5a000038) //SDI FIFO status
486	#define rSDIIMSK ((volatile unsigned )0x5a000040) //SDI interrupt mask. edited for 2440A
487
488	#ifdef __BIG_ENDIAN
489	#define rSDIDAT ((volatile unsigned )0x5a00003F) //SDI data
490	#define SDIDAT 0x5a00003F
491	#else // Little Endian
492	#define rSDIDAT ((volatile unsigned )0x5a00003C) //SDI data
493	#define SDIDAT 0x5a00003C
494	#endif //SD Interface
495
496
497	#define _ISR_STARTADDRESS rtems_vector_table
498	/* ISR */
499	#define pISR_RESET ((unsigned )(_ISR_STARTADDRESS+0x0))
500	#define pISR_UNDEF ((unsigned )(_ISR_STARTADDRESS+0x4))
501	#define pISR_SWI ((unsigned )(_ISR_STARTADDRESS+0x8))
502	#define pISR_PABORT ((unsigned )(_ISR_STARTADDRESS+0xC))
503	#define pISR_DABORT ((unsigned )(_ISR_STARTADDRESS+0x10))
504	#define pISR_RESERVED ((unsigned )(_ISR_STARTADDRESS+0x14))
505	#define pISR_IRQ ((unsigned )(_ISR_STARTADDRESS+0x18))
506	#define pISR_FIQ ((unsigned )(_ISR_STARTADDRESS+0x1C))
507
508	#define pISR_EINT0 ((unsigned )(_ISR_STARTADDRESS+0x20))
509	#define pISR_EINT1 ((unsigned )(_ISR_STARTADDRESS+0x24))
510	#define pISR_EINT2 ((unsigned )(_ISR_STARTADDRESS+0x28))
511	#define pISR_EINT3 ((unsigned )(_ISR_STARTADDRESS+0x2C))
512	#define pISR_EINT4_7 ((unsigned )(_ISR_STARTADDRESS+0x30))
513	#define pISR_EINT8_23 ((unsigned )(_ISR_STARTADDRESS+0x34))
514	#define pISR_BAT_FLT ((unsigned )(_ISR_STARTADDRESS+0x3C))
515	#define pISR_TICK ((unsigned )(_ISR_STARTADDRESS+0x40))
516	#define pISR_WDT ((unsigned )(_ISR_STARTADDRESS+0x44))
517	#define pISR_TIMER0 ((unsigned )(_ISR_STARTADDRESS+0x48))
518	#define pISR_TIMER1 ((unsigned )(_ISR_STARTADDRESS+0x4C))
519	#define pISR_TIMER2 ((unsigned )(_ISR_STARTADDRESS+0x50))
520	#define pISR_TIMER3 ((unsigned )(_ISR_STARTADDRESS+0x54))
521	#define pISR_TIMER4 ((unsigned )(_ISR_STARTADDRESS+0x58))
522	#define pISR_UART2 ((unsigned )(_ISR_STARTADDRESS+0x5C))
523	#define pISR_NOTUSED ((unsigned )(_ISR_STARTADDRESS+0x60))
524	#define pISR_DMA0 ((unsigned )(_ISR_STARTADDRESS+0x64))
525	#define pISR_DMA1 ((unsigned )(_ISR_STARTADDRESS+0x68))
526	#define pISR_DMA2 ((unsigned )(_ISR_STARTADDRESS+0x6C))
527	#define pISR_DMA3 ((unsigned )(_ISR_STARTADDRESS+0x70))
528	#define pISR_SDI ((unsigned )(_ISR_STARTADDRESS+0x74))
529	#define pISR_SPI0 ((unsigned )(_ISR_STARTADDRESS+0x78))
530	#define pISR_UART1 ((unsigned )(_ISR_STARTADDRESS+0x7C))
531	#define pISR_USBD ((unsigned )(_ISR_STARTADDRESS+0x84))
532	#define pISR_USBH ((unsigned )(_ISR_STARTADDRESS+0x88))
533	#define pISR_IIC ((unsigned )(_ISR_STARTADDRESS+0x8C))
534	#define pISR_UART0 ((unsigned )(_ISR_STARTADDRESS+0x90))
535	#define pISR_SPI1 ((unsigned )(_ISR_STARTADDRESS+0x94))
536	#define pISR_RTC ((unsigned )(_ISR_STARTADDRESS+0x98))
537	#define pISR_ADC ((unsigned )(_ISR_STARTADDRESS+0xA0))
538
539
540	/* PENDING BIT */
541	#define BIT_EINT0 (0x1)
542	#define BIT_EINT1 (0x1<<1)
543	#define BIT_EINT2 (0x1<<2)
544	#define BIT_EINT3 (0x1<<3)
545	#define BIT_EINT4_7 (0x1<<4)
546	#define BIT_EINT8_23 (0x1<<5)
547	#define BIT_BAT_FLT (0x1<<7)
548	#define BIT_TICK (0x1<<8)
549	#define BIT_WDT (0x1<<9)
550	#define BIT_TIMER0 (0x1<<10)
551	#define BIT_TIMER1 (0x1<<11)
552	#define BIT_TIMER2 (0x1<<12)
553	#define BIT_TIMER3 (0x1<<13)
554	#define BIT_TIMER4 (0x1<<14)
555	#define BIT_UART2 (0x1<<15)
556	#define BIT_LCD (0x1<<16)
557	#define BIT_DMA0 (0x1<<17)
558	#define BIT_DMA1 (0x1<<18)
559	#define BIT_DMA2 (0x1<<19)
560	#define BIT_DMA3 (0x1<<20)
561	#define BIT_SDI (0x1<<21)
562	#define BIT_SPI0 (0x1<<22)
563	#define BIT_UART1 (0x1<<23)
564	#define BIT_USBD (0x1<<25)
565	#define BIT_USBH (0x1<<26)
566	#define BIT_IIC (0x1<<27)
567	#define BIT_UART0 (0x1<<28)
568	#define BIT_SPI1 (0x1<<29)
569	#define BIT_RTC (0x1<<30)
570	#define BIT_ADC (0x1<<31)
571	#define BIT_ALLMSK (0xFFFFFFFF)
572
573	#define ClearPending(bit) {\
574	rSRCPND = bit;\
575	rINTPND = bit;\
576	rINTPND;\
577	}
578	/* Wait until rINTPND is changed for the case that the ISR is very short. */
579	#ifndef __asm__
580	/* Typedefs */
581	typedef union {
582	struct _reg {
583	unsigned SM_BIT:1; /* Enters STOP mode. This bit isn't be */
584	/* cleared automatically. */
585	unsigned Reserved:1; /* SL_IDLE mode option. This bit isn't cleared */
586	/* automatically. To enter SL_IDLE mode, */
587	/* CLKCON register has to be 0xe. */
588	unsigned IDLE_BIT:1; /* Enters IDLE mode. This bit isn't be cleared */
589	/* automatically. */
590	unsigned POWER_OFF:1;
591	unsigned NAND_flash:1;
592	unsigned LCDC:1; /* Controls HCLK into LCDC block */
593	unsigned USB_host:1; /* Controls HCLK into USB host block */
594	unsigned USB_device:1; /* Controls PCLK into USB device block */
595	unsigned PWMTIMER:1; /* Controls PCLK into PWMTIMER block */
596	unsigned SDI:1; /* Controls PCLK into MMC interface block */
597	unsigned UART0:1; /* Controls PCLK into UART0 block */
598	unsigned UART1:1; /* Controls PCLK into UART1 block */
599	unsigned UART2:1; /* Controls PCLK into UART1 block */
600	unsigned GPIO:1; /* Controls PCLK into GPIO block */
601	unsigned RTC:1; /* Controls PCLK into RTC control block. Even if */
602	/* this bit is cleared to 0, RTC timer is alive. */
603	unsigned ADC:1; /* Controls PCLK into ADC block */
604	unsigned IIC:1; /* Controls PCLK into IIC block */
605	unsigned IIS:1; /* Controls PCLK into IIS block */
606	unsigned SPI:1; /* Controls PCLK into SPI block */
607	} reg;
608	unsigned long all;
609	} CLKCON;
610
611	typedef union
612	{
613	struct {
614	unsigned ENVID:1; /* LCD video output and the logic 1=enable/0=disable. */
615	unsigned BPPMODE:4; /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */
616	/* 1110 = 16 bpp TFT skipmode */
617	unsigned PNRMODE:2; /* TFT: 3 */
618	unsigned MMODE:1; /* This bit determines the toggle rate of the VM. */
619	/* 0 = Each Frame, 1 = The rate defined by the MVAL */
620	unsigned CLKVAL:10; /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */
621	unsigned LINECNT:10; /* (read only) These bits provide the status of the */
622	/* line counter. Down count from LINEVAL to 0 */
623	} reg;
624	unsigned long all;
625	} LCDCON1;
626
627	typedef union {
628	struct {
629	unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */
630	/* VSYNC pulse's high level width by counting the */
631	/* number of inactive lines. */
632	unsigned VFPD:8; /* TFT: Vertical front porch is the number of */
633	/* inactive lines at the end of a frame, before */
634	/* vertical synchronization period. */
635	unsigned LINEVAL:10; /* TFT/STN: These bits determine the vertical size */
636	/* of LCD panel. */
637	unsigned VBPD:8; /* TFT: Vertical back porch is the number of inactive */
638	/* lines at the start of a frame, after */
639	/* vertical synchronization period. */
640	} reg;
641	unsigned long all;
642	} LCDCON2;
643
644	typedef union {
645	struct {
646	unsigned HFPD:8; /* TFT: Horizontal front porch is the number of */
647	/* VCLK periods between the end of active data */
648	/* and the rising edge of HSYNC. */
649	unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */
650	/* size of LCD panel. 2n bytes. */
651	unsigned HBPD:7; /* TFT: Horizontal back porch is the number of VCLK */
652	/* periods between the falling edge of HSYNC and */
653	/* the start of active data. */
654	} reg;
655	unsigned long all;
656	} LCDCON3;
657
658	typedef union {
659	struct {
660	unsigned HSPW:8; /* TFT: Horizontal sync pulse width determines the */
661	/* HSYNC pulse's high level width by counting the */
662	/* number of the VCLK. */
663	unsigned MVAL:8; /* STN: */
664	} reg;
665	unsigned long all;
666	} LCDCON4;
667
668	typedef union {
669	struct {
670	unsigned HWSWP:1; /* STN/TFT: Half-Word swap control bit. */
671	/* 0 = Swap Disable 1 = Swap Enable */
672	unsigned BSWP:1; /* STN/TFT: Byte swap control bit. */
673	/* 0 = Swap Disable 1 = Swap Enable */
674	unsigned ENLEND:1; /* TFT: LEND output signal enable/disable. */
675	/* 0 = Disable LEND signal. */
676	/* 1 = Enable LEND signal */
677	unsigned PWREN:1;
678	unsigned INVLEND:1;/* TFT: This bit indicates the LEND signal */
679	/* polarity. 0 = normal 1 = inverted */
680	unsigned INVPWREN:1;
681	unsigned INVVDEN:1; /* TFT: This bit indicates the VDEN signal */
682	/* polarity. */
683	/* 0 = normal 1 = inverted */
684	unsigned INVVD:1; /* STN/TFT: This bit indicates the VD (video data) */
685	/* pulse polarity. 0 = Normal. */
686	/* 1 = VD is inverted. */
687	unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */
688	/* pulse polarity. 0 = normal 1 = inverted */
689	unsigned INVVLINE:1; /* STN/TFT: This bit indicates the VLINE/HSYNC */
690	/* pulse polarity. 0 = normal 1 = inverted */
691	unsigned INVVCLK:1; /* STN/TFT: This bit controls the polarity of the */
692	/* VCLK active edge. 0 = The video data is */
693	/* fetched at VCLK falling edge. 1 = The video */
694	/* data is fetched at VCLK rising edge */
695	unsigned FRM565:1;
696	unsigned BPP24BL:1;
697	unsigned HSTATUS:2; /* TFT: Horizontal Status (Read only) */
698	/* 00 = HSYNC */
699	/* 01 = BACK Porch. */
700	/* 10 = ACTIVE */
701	/* 11 = FRONT Porch */
702	unsigned VSTATUS:2; /* TFT: Vertical Status (Read only). */
703	/* 00 = VSYNC */
704	/* 01 = BACK Porch. */
705	/* 10 = ACTIVE */
706	/* 11 = FRONT Porch */
707	unsigned RESERVED:16;
708	} reg;
709	unsigned long all;
710	} LCDCON5;
711
712	typedef union {
713	struct {
714	unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */
715	/* A[21:1] of the start address of the LCD */
716	/* frame buffer. */
717	unsigned LCDBANK:9; /* A[28:22] */
718	} reg;
719	unsigned long all;
720	} LCDSADDR1;
721
722	typedef union {
723	struct {
724	unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/
725	/* of the end address of the LCD frame buffer. */
726	/* LCDBASEL = ((the fame end address) >>1) + 1 */
727	/* = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */
728	} reg;
729	unsigned long all;
730	} LCDSADDR2;
731
732	typedef union {
733	struct {
734	unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */
735	/* words) This value defines the width of the */
736	/* view port in the frame */
737	unsigned OFFSIZE:11; /* Virtual screen offset size(the number of half */
738	/* words) This value defines the difference */
739	/* between the address of the last half word */
740	/* displayed on the previous LCD line and the */
741	/* address of the first half word to be */
742	/* displayed in the new LCD line. */
743	} reg;
744	unsigned long all;
745	} LCDSADDR3;
746
747	/*
748	*
749	*/
750
751	typedef union {
752	struct {
753	unsigned IISIFENA:1; /* IIS interface enable (start) */
754	unsigned IISPSENA:1; /* IIS prescaler enable */
755	unsigned RXCHIDLE:1; /* Receive channel idle command */
756	unsigned TXCHIDLE:1; /* Transmit channel idle command */
757	unsigned RXDMAENA:1; /* Receive DMA service request enable */
758	unsigned TXDMAENA:1; /* Transmit DMA service request enable */
759	unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */
760	unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */
761	unsigned LRINDEX:1; /* Left/right channel index (read only) */
762	} reg;
763	unsigned long all;
764	} IISCON;
765
766	typedef union {
767	struct {
768	unsigned SBCLKFS:2; /* Serial bit clock frequency select */
769	unsigned MCLKFS:1; /* Master clock frequency select */
770	unsigned SDBITS:1; /* Serial data bit per channel */
771	unsigned SIFMT:1; /* Serial interface format */
772	unsigned ACTLEVCH:1; /* Active level pf left/right channel */
773	unsigned TXRXMODE:2; /* Transmit/receive mode select */
774	unsigned MODE:1; /* Master/slave mode select */
775	} reg;
776	unsigned long all;
777	} IISMOD;
778
779	typedef union {
780	struct {
781	unsigned PSB:5; /* Prescaler control B */
782	unsigned PSA:5; /* Prescaler control A */
783	} reg;
784	unsigned long all;
785	} IISPSR;
786
787	typedef union {
788	struct {
789	unsigned RXFIFOCNT:6; /* (read only) */
790	unsigned TXFIFOCNT:6; /* (read only) */
791	unsigned RXFIFOENA:1; /* */
792	unsigned TXFIFOENA:1; /* */
793	unsigned RXFIFOMODE:1; /* */
794	unsigned TXFIFOMODE:1; /* */
795	} reg;
796	unsigned long all;
797	} IISSFIFCON;
798
799	typedef union {
800	struct {
801	unsigned FENTRY:16; /* */
802	} reg;
803	unsigned long all;
804	} IISSFIF;
805	#endif //__asm__
806
807	#define LCD_WIDTH 240
808	#define LCD_HEIGHT 320
809	#define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT))
810
811	#define SMDK2410_KEY_SELECT 512
812	#define SMDK2410_KEY_START 256
813	#define SMDK2410_KEY_A 64
814	#define SMDK2410_KEY_B 32
815	#define SMDK2410_KEY_L 16
816	#define SMDK2410_KEY_R 128
817	#define SMDK2410_KEY_UP 8
818	#define SMDK2410_KEY_DOWN 2
819	#define SMDK2410_KEY_LEFT 1
820	#define SMDK2410_KEY_RIGHT 4
821
822	#endif /S3C2410_H_/

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source: rtems/c/src/lib/libcpu/arm/s3c2410/include/s3c2410.h @ dbdb0255

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