[dbdb0255] | 1 | /************************************************ |
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| 2 | * NAME : s3c2410.h |
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| 3 | * Version : 3.7.2002 |
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| 4 | * |
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| 5 | * Based on 24x.h for the Samsung Development Board |
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| 6 | ************************************************/ |
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| 7 | |
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| 8 | #ifndef S3C2410_H_ |
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| 9 | #define S3C2410_H_ |
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| 10 | /* Memory control */ |
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| 11 | #define rBWSCON (*(volatile unsigned *)0x48000000) |
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| 12 | #define rBANKCON0 (*(volatile unsigned *)0x48000004) |
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| 13 | #define rBANKCON1 (*(volatile unsigned *)0x48000008) |
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| 14 | #define rBANKCON2 (*(volatile unsigned *)0x4800000C) |
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| 15 | #define rBANKCON3 (*(volatile unsigned *)0x48000010) |
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| 16 | #define rBANKCON4 (*(volatile unsigned *)0x48000014) |
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| 17 | #define rBANKCON5 (*(volatile unsigned *)0x48000018) |
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| 18 | #define rBANKCON6 (*(volatile unsigned *)0x4800001C) |
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| 19 | #define rBANKCON7 (*(volatile unsigned *)0x48000020) |
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| 20 | #define rREFRESH (*(volatile unsigned *)0x48000024) |
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| 21 | #define rBANKSIZE (*(volatile unsigned *)0x48000028) |
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| 22 | #define rMRSRB6 (*(volatile unsigned *)0x4800002C) |
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| 23 | #define rMRSRB7 (*(volatile unsigned *)0x48000030) |
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| 24 | |
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| 25 | /* USB Host Controller */ |
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| 26 | #define rHcRevision (*(volatile unsigned *)0x49000000) |
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| 27 | #define rHcControl (*(volatile unsigned *)0x49000004) |
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| 28 | #define rHcCommonStatus (*(volatile unsigned *)0x49000008) |
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| 29 | #define rHcInterruptStatus (*(volatile unsigned *)0x4900000C) |
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| 30 | #define rHcInterruptEnable (*(volatile unsigned *)0x49000010) |
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| 31 | #define rHcInterruptDisable (*(volatile unsigned *)0x49000014) |
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| 32 | #define rHcHCCA (*(volatile unsigned *)0x49000018) |
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| 33 | #define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C) |
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| 34 | #define rHcControlHeadED (*(volatile unsigned *)0x49000020) |
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| 35 | #define rHcControlCurrentED (*(volatile unsigned *)0x49000024) |
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| 36 | #define rHcBulkHeadED (*(volatile unsigned *)0x49000028) |
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| 37 | #define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C) |
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| 38 | #define rHcDoneHead (*(volatile unsigned *)0x49000030) |
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| 39 | #define rHcRmInterval (*(volatile unsigned *)0x49000034) |
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| 40 | #define rHcFmRemaining (*(volatile unsigned *)0x49000038) |
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| 41 | #define rHcFmNumber (*(volatile unsigned *)0x4900003C) |
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| 42 | #define rHcPeriodicStart (*(volatile unsigned *)0x49000040) |
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| 43 | #define rHcLSThreshold (*(volatile unsigned *)0x49000044) |
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| 44 | #define rHcRhDescriptorA (*(volatile unsigned *)0x49000048) |
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| 45 | #define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C) |
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| 46 | #define rHcRhStatus (*(volatile unsigned *)0x49000050) |
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| 47 | #define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054) |
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| 48 | #define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058) |
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| 49 | |
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| 50 | /* INTERRUPT */ |
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| 51 | #define rSRCPND (*(volatile unsigned *)0x4A000000) |
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| 52 | #define rINTMOD (*(volatile unsigned *)0x4A000004) |
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| 53 | #define rINTMSK (*(volatile unsigned *)0x4A000008) |
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| 54 | #define rPRIORITY (*(volatile unsigned *)0x4A00000C) |
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| 55 | #define rINTPND (*(volatile unsigned *)0x4A000010) |
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| 56 | #define rINTOFFSET (*(volatile unsigned *)0x4A000014) |
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| 57 | #define rSUBSRCPND (*(volatile unsigned *)0x4A000018) |
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| 58 | #define rINTSUBMSK (*(volatile unsigned *)0x4A00001c) |
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| 59 | |
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| 60 | |
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| 61 | /* DMA */ |
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| 62 | #define rDISRC0 (*(volatile unsigned *)0x4B000000) |
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| 63 | #define rDISRCC0 (*(volatile unsigned *)0x4B000004) |
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| 64 | #define rDIDST0 (*(volatile unsigned *)0x4B000008) |
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| 65 | #define rDIDSTC0 (*(volatile unsigned *)0x4B00000C) |
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| 66 | #define rDCON0 (*(volatile unsigned *)0x4B000010) |
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| 67 | #define rDSTAT0 (*(volatile unsigned *)0x4B000014) |
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| 68 | #define rDCSRC0 (*(volatile unsigned *)0x4B000018) |
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| 69 | #define rDCDST0 (*(volatile unsigned *)0x4B00001C) |
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| 70 | #define rDMASKTRIG0 (*(volatile unsigned *)0x4B000020) |
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| 71 | #define rDISRC1 (*(volatile unsigned *)0x4B000040) |
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| 72 | #define rDISRCC1 (*(volatile unsigned *)0x4B000044) |
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| 73 | #define rDIDST1 (*(volatile unsigned *)0x4B000048) |
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| 74 | #define rDIDSTC1 (*(volatile unsigned *)0x4B00004C) |
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| 75 | #define rDCON1 (*(volatile unsigned *)0x4B000050) |
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| 76 | #define rDSTAT1 (*(volatile unsigned *)0x4B000054) |
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| 77 | #define rDCSRC1 (*(volatile unsigned *)0x4B000058) |
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| 78 | #define rDCDST1 (*(volatile unsigned *)0x4B00005C) |
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| 79 | #define rDMASKTRIG1 (*(volatile unsigned *)0x4B000060) |
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| 80 | #define rDISRC2 (*(volatile unsigned *)0x4B000080) |
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| 81 | #define rDISRCC2 (*(volatile unsigned *)0x4B000084) |
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| 82 | #define rDIDST2 (*(volatile unsigned *)0x4B000088) |
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| 83 | #define rDIDSTC2 (*(volatile unsigned *)0x4B00008C) |
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| 84 | #define rDCON2 (*(volatile unsigned *)0x4B000090) |
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| 85 | #define rDSTAT2 (*(volatile unsigned *)0x4B000094) |
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| 86 | #define rDCSRC2 (*(volatile unsigned *)0x4B000098) |
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| 87 | #define rDCDST2 (*(volatile unsigned *)0x4B00009C) |
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| 88 | #define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0) |
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| 89 | #define rDISRC3 (*(volatile unsigned *)0x4B0000C0) |
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| 90 | #define rDISRCC3 (*(volatile unsigned *)0x4B0000C4) |
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| 91 | #define rDIDST3 (*(volatile unsigned *)0x4B0000C8) |
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| 92 | #define rDIDSTC3 (*(volatile unsigned *)0x4B0000CC) |
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| 93 | #define rDCON3 (*(volatile unsigned *)0x4B0000D0) |
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| 94 | #define rDSTAT3 (*(volatile unsigned *)0x4B0000D4) |
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| 95 | #define rDCSRC3 (*(volatile unsigned *)0x4B0000D8) |
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| 96 | #define rDCDST3 (*(volatile unsigned *)0x4B0000DC) |
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| 97 | #define rDMASKTRIG3 (*(volatile unsigned *)0x4B0000E0) |
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| 98 | |
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| 99 | |
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| 100 | /* CLOCK & POWER MANAGEMENT */ |
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| 101 | #define rLOCKTIME (*(volatile unsigned *)0x4C000000) |
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| 102 | #define rMPLLCON (*(volatile unsigned *)0x4C000004) |
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| 103 | #define rUPLLCON (*(volatile unsigned *)0x4C000008) |
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| 104 | #define rCLKCON (*(volatile unsigned *)0x4C00000C) |
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| 105 | #define rCLKSLOW (*(volatile unsigned *)0x4C000010) |
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| 106 | #define rCLKDIVN (*(volatile unsigned *)0x4C000014) |
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| 107 | |
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| 108 | |
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| 109 | /* LCD CONTROLLER */ |
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| 110 | #define rLCDCON1 (*(volatile unsigned *)0x4D000000) |
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| 111 | #define rLCDCON2 (*(volatile unsigned *)0x4D000004) |
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| 112 | #define rLCDCON3 (*(volatile unsigned *)0x4D000008) |
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| 113 | #define rLCDCON4 (*(volatile unsigned *)0x4D00000C) |
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| 114 | #define rLCDCON5 (*(volatile unsigned *)0x4D000010) |
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| 115 | #define rLCDSADDR1 (*(volatile unsigned *)0x4D000014) |
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| 116 | #define rLCDSADDR2 (*(volatile unsigned *)0x4D000018) |
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| 117 | #define rLCDSADDR3 (*(volatile unsigned *)0x4D00001C) |
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| 118 | #define rREDLUT (*(volatile unsigned *)0x4D000020) |
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| 119 | #define rGREENLUT (*(volatile unsigned *)0x4D000024) |
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| 120 | #define rBLUELUT (*(volatile unsigned *)0x4D000028) |
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| 121 | #define rREDLUT (*(volatile unsigned *)0x4D000020) |
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| 122 | #define rGREENLUT (*(volatile unsigned *)0x4D000024) |
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| 123 | #define rBLUELUT (*(volatile unsigned *)0x4D000028) |
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| 124 | #define rDITHMODE (*(volatile unsigned *)0x4D00004C) |
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| 125 | #define rTPAL (*(volatile unsigned *)0x4D000050) |
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| 126 | #define rLCDINTPND (*(volatile unsigned *)0x4D000054) |
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| 127 | #define rLCDSRCPND (*(volatile unsigned *)0x4D000058) |
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| 128 | #define rLCDINTMSK (*(volatile unsigned *)0x4D00005C) |
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| 129 | #define rTCONSEL (*(volatile unsigned *)0x4D000060) |
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| 130 | #define PALETTE 0x4d000400 |
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| 131 | |
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| 132 | /* NAND Flash */ |
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| 133 | #define rNFCONF (*(volatile unsigned *)0x4E000000) |
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| 134 | #define rNFCMD (*(volatile unsigned *)0x4E000004) |
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| 135 | #define rNFADDR (*(volatile unsigned *)0x4E000008) |
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| 136 | #define rNFDATA (*(volatile unsigned *)0x4E00000C) |
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| 137 | #define rNFSTAT (*(volatile unsigned *)0x4E000010) |
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| 138 | #define rNFECC (*(volatile unsigned *)0x4E000014) |
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| 139 | |
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| 140 | /* UART */ |
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| 141 | #define rULCON0 (*(volatile unsigned char *)0x50000000) |
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| 142 | #define rUCON0 (*(volatile unsigned short *)0x50000004) |
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| 143 | #define rUFCON0 (*(volatile unsigned char *)0x50000008) |
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| 144 | #define rUMCON0 (*(volatile unsigned char *)0x5000000C) |
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| 145 | #define rUTRSTAT0 (*(volatile unsigned char *)0x50000010) |
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| 146 | #define rUERSTAT0 (*(volatile unsigned char *)0x50000014) |
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| 147 | #define rUFSTAT0 (*(volatile unsigned short *)0x50000018) |
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| 148 | #define rUMSTAT0 (*(volatile unsigned char *)0x5000001C) |
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| 149 | #define rUBRDIV0 (*(volatile unsigned short *)0x50000028) |
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| 150 | |
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| 151 | #define rULCON1 (*(volatile unsigned char *)0x50004000) |
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| 152 | #define rUCON1 (*(volatile unsigned short *)0x50004004) |
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| 153 | #define rUFCON1 (*(volatile unsigned char *)0x50004008) |
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| 154 | #define rUMCON1 (*(volatile unsigned char *)0x5000400C) |
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| 155 | #define rUTRSTAT1 (*(volatile unsigned char *)0x50004010) |
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| 156 | #define rUERSTAT1 (*(volatile unsigned char *)0x50004014) |
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| 157 | #define rUFSTAT1 (*(volatile unsigned short *)0x50004018) |
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| 158 | #define rUMSTAT1 (*(volatile unsigned char *)0x5000401C) |
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| 159 | #define rUBRDIV1 (*(volatile unsigned short *)0x50004028) |
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| 160 | |
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| 161 | #define rULCON2 (*(volatile unsigned char *)0x50008000) |
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| 162 | #define rUCON2 (*(volatile unsigned short *)0x50008004) |
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| 163 | #define rUFCON2 (*(volatile unsigned char *)0x50008008) |
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| 164 | #define rUTRSTAT2 (*(volatile unsigned char *)0x50008010) |
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| 165 | #define rUERSTAT2 (*(volatile unsigned char *)0x50008014) |
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| 166 | #define rUFSTAT2 (*(volatile unsigned short *)0x50008018) |
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| 167 | #define rUBRDIV2 (*(volatile unsigned short *)0x50008028) |
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| 168 | |
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| 169 | #ifdef __BIG_ENDIAN |
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| 170 | #define rUTXH0 (*(volatile unsigned char *)0x50000023) |
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| 171 | #define rURXH0 (*(volatile unsigned char *)0x50000027) |
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| 172 | #define rUTXH1 (*(volatile unsigned char *)0x50004023) |
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| 173 | #define rURXH1 (*(volatile unsigned char *)0x50004027) |
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| 174 | #define rUTXH2 (*(volatile unsigned char *)0x50008023) |
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| 175 | #define rURXH2 (*(volatile unsigned char *)0x50008027) |
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| 176 | |
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| 177 | #define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch) |
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| 178 | #define RdURXH0() (*(volatile unsigned char *)0x50000027) |
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| 179 | #define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch) |
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| 180 | #define RdURXH1() (*(volatile unsigned char *)0x50004027) |
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| 181 | #define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch) |
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| 182 | #define RdURXH2() (*(volatile unsigned char *)0x50008027) |
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| 183 | |
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| 184 | #define UTXH0 (0x50000020+3) /* byte_access address by DMA */ |
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| 185 | #define URXH0 (0x50000024+3) |
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| 186 | #define UTXH1 (0x50004020+3) |
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| 187 | #define URXH1 (0x50004024+3) |
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| 188 | #define UTXH2 (0x50008020+3) |
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| 189 | #define URXH2 (0x50008024+3) |
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| 190 | |
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| 191 | #else /* Little Endian */ |
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| 192 | #define rUTXH0 (*(volatile unsigned char *)0x50000020) |
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| 193 | #define rURXH0 (*(volatile unsigned char *)0x50000024) |
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| 194 | #define rUTXH1 (*(volatile unsigned char *)0x50004020) |
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| 195 | #define rURXH1 (*(volatile unsigned char *)0x50004024) |
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| 196 | #define rUTXH2 (*(volatile unsigned char *)0x50008020) |
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| 197 | #define rURXH2 (*(volatile unsigned char *)0x50008024) |
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| 198 | |
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| 199 | #define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch) |
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| 200 | #define RdURXH0() (*(volatile unsigned char *)0x50000024) |
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| 201 | #define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch) |
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| 202 | #define RdURXH1() (*(volatile unsigned char *)0x50004024) |
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| 203 | #define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch) |
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| 204 | #define RdURXH2() (*(volatile unsigned char *)0x50008024) |
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| 205 | |
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| 206 | #define UTXH0 (0x50000020) |
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| 207 | #define URXH0 (0x50000024) |
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| 208 | #define UTXH1 (0x50004020) |
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| 209 | #define URXH1 (0x50004024) |
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| 210 | #define UTXH2 (0x50008020) |
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| 211 | #define URXH2 (0x50008024) |
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| 212 | #endif |
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| 213 | |
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| 214 | |
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| 215 | /* PWM TIMER */ |
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| 216 | #define rTCFG0 (*(volatile unsigned *)0x51000000) |
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| 217 | #define rTCFG1 (*(volatile unsigned *)0x51000004) |
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| 218 | #define rTCON (*(volatile unsigned *)0x51000008) |
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| 219 | #define rTCNTB0 (*(volatile unsigned *)0x5100000C) |
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| 220 | #define rTCMPB0 (*(volatile unsigned *)0x51000010) |
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| 221 | #define rTCNTO0 (*(volatile unsigned *)0x51000014) |
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| 222 | #define rTCNTB1 (*(volatile unsigned *)0x51000018) |
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| 223 | #define rTCMPB1 (*(volatile unsigned *)0x5100001C) |
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| 224 | #define rTCNTO1 (*(volatile unsigned *)0x51000020) |
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| 225 | #define rTCNTB2 (*(volatile unsigned *)0x51000024) |
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| 226 | #define rTCMPB2 (*(volatile unsigned *)0x51000028) |
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| 227 | #define rTCNTO2 (*(volatile unsigned *)0x5100002C) |
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| 228 | #define rTCNTB3 (*(volatile unsigned *)0x51000030) |
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| 229 | #define rTCMPB3 (*(volatile unsigned *)0x51000034) |
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| 230 | #define rTCNTO3 (*(volatile unsigned *)0x51000038) |
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| 231 | #define rTCNTB4 (*(volatile unsigned *)0x5100003C) |
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| 232 | #define rTCNTO4 (*(volatile unsigned *)0x51000040) |
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| 233 | |
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| 234 | |
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| 235 | /* USB DEVICE */ |
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| 236 | #ifdef __BIG_ENDIAN |
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| 237 | #define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address |
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| 238 | #define rPWR_REG (*(volatile unsigned char *)0x52000147) //Power management |
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| 239 | #define rEP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear |
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| 240 | #define rUSB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear |
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| 241 | #define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable |
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| 242 | #define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016f) |
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| 243 | #define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte |
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| 244 | #define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte |
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| 245 | #define rINDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index |
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| 246 | #define rMAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet |
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| 247 | #define rEP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status |
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| 248 | #define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status |
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| 249 | #define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018b) |
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| 250 | #define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status |
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| 251 | #define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197) |
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| 252 | #define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count |
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| 253 | #define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f) |
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| 254 | #define rEP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO |
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| 255 | #define rEP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO |
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| 256 | #define rEP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO |
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| 257 | #define rEP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO |
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| 258 | #define rEP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO |
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| 259 | #define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control |
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| 260 | #define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter |
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| 261 | #define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter |
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| 262 | #define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter |
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| 263 | #define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213) |
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| 264 | #define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217) |
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| 265 | #define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control |
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| 266 | #define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter |
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| 267 | #define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter |
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| 268 | #define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter |
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| 269 | #define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b) |
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| 270 | #define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f) |
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| 271 | #define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control |
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| 272 | #define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter |
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| 273 | #define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter |
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| 274 | #define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter |
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| 275 | #define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253) |
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| 276 | #define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257) |
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| 277 | #define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control |
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| 278 | #define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter |
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| 279 | #define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter |
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| 280 | #define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter |
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| 281 | #define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b) |
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| 282 | #define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f) |
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| 283 | |
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| 284 | #else // Little Endian |
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| 285 | #define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address |
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| 286 | #define rPWR_REG (*(volatile unsigned char *)0x52000144) //Power management |
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| 287 | #define rEP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear |
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| 288 | #define rUSB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear |
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| 289 | #define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable |
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| 290 | #define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016c) |
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| 291 | #define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte |
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| 292 | #define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte |
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| 293 | #define rINDEX_REG (*(volatile unsigned char *)0x52000178) //Register index |
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| 294 | #define rMAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet |
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| 295 | #define rEP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status |
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| 296 | #define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status |
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| 297 | #define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188) |
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| 298 | #define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status |
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| 299 | #define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194) |
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| 300 | #define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count |
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| 301 | #define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c) |
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| 302 | #define rEP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO |
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| 303 | #define rEP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO |
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| 304 | #define rEP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO |
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| 305 | #define rEP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO |
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| 306 | #define rEP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO |
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| 307 | #define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control |
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| 308 | #define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter |
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| 309 | #define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter |
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| 310 | #define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter |
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| 311 | #define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210) |
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| 312 | #define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214) |
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| 313 | #define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control |
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| 314 | #define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter |
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| 315 | #define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter |
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| 316 | #define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter |
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| 317 | #define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228) |
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| 318 | #define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c) |
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| 319 | #define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control |
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| 320 | #define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter |
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| 321 | #define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter |
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| 322 | #define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter |
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| 323 | #define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250) |
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| 324 | #define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254) |
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| 325 | #define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control |
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| 326 | #define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter |
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| 327 | #define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter |
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| 328 | #define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter |
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| 329 | #define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268) |
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| 330 | #define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c) |
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| 331 | #endif // __BIG_ENDIAN |
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| 332 | |
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| 333 | /* WATCH DOG TIMER */ |
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| 334 | #define rWTCON (*(volatile unsigned *)0x53000000) |
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| 335 | #define rWTDAT (*(volatile unsigned *)0x53000004) |
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| 336 | #define rWTCNT (*(volatile unsigned *)0x53000008) |
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| 337 | |
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| 338 | |
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| 339 | /* IIC */ |
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| 340 | #define rIICCON (*(volatile unsigned *)0x54000000) |
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| 341 | #define rIICSTAT (*(volatile unsigned *)0x54000004) |
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| 342 | #define rIICADD (*(volatile unsigned *)0x54000008) |
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| 343 | #define rIICDS (*(volatile unsigned *)0x5400000C) |
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| 344 | |
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| 345 | |
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| 346 | /* IIS */ |
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| 347 | #define rIISCON (*(volatile unsigned *)0x55000000) |
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| 348 | #define rIISMOD (*(volatile unsigned *)0x55000004) |
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| 349 | #define rIISPSR (*(volatile unsigned *)0x55000008) |
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| 350 | #define rIISFIFCON (*(volatile unsigned *)0x5500000C) |
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| 351 | |
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| 352 | #ifdef __BIG_ENDIAN |
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| 353 | #define IISFIFO ((volatile unsigned short *)0x55000012) |
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| 354 | |
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| 355 | #else /* Little Endian */ |
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| 356 | #define IISFIFO ((volatile unsigned short *)0x55000010) |
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| 357 | #endif |
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| 358 | |
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| 359 | |
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| 360 | /* I/O PORT */ |
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| 361 | #define rGPACON (*(volatile unsigned *)0x56000000) //Port A control |
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| 362 | #define rGPADAT (*(volatile unsigned *)0x56000004) //Port A data |
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| 363 | |
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| 364 | #define rGPBCON (*(volatile unsigned *)0x56000010) //Port B control |
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| 365 | #define rGPBDAT (*(volatile unsigned *)0x56000014) //Port B data |
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| 366 | #define rGPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B |
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| 367 | |
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| 368 | #define rGPCCON (*(volatile unsigned *)0x56000020) //Port C control |
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| 369 | #define rGPCDAT (*(volatile unsigned *)0x56000024) //Port C data |
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| 370 | #define rGPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C |
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| 371 | |
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| 372 | #define rGPDCON (*(volatile unsigned *)0x56000030) //Port D control |
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| 373 | #define rGPDDAT (*(volatile unsigned *)0x56000034) //Port D data |
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| 374 | #define rGPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D |
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| 375 | |
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| 376 | #define rGPECON (*(volatile unsigned *)0x56000040) //Port E control |
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| 377 | #define rGPEDAT (*(volatile unsigned *)0x56000044) //Port E data |
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| 378 | #define rGPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E |
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| 379 | |
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| 380 | #define rGPFCON (*(volatile unsigned *)0x56000050) //Port F control |
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| 381 | #define rGPFDAT (*(volatile unsigned *)0x56000054) //Port F data |
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| 382 | #define rGPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F |
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| 383 | |
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| 384 | #define rGPGCON (*(volatile unsigned *)0x56000060) //Port G control |
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| 385 | #define rGPGDAT (*(volatile unsigned *)0x56000064) //Port G data |
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| 386 | #define rGPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G |
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| 387 | |
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| 388 | #define rGPHCON (*(volatile unsigned *)0x56000070) //Port H control |
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| 389 | #define rGPHDAT (*(volatile unsigned *)0x56000074) //Port H data |
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| 390 | #define rGPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H |
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| 391 | |
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| 392 | #define rMISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control |
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| 393 | #define rDCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control |
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| 394 | #define rEXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control register 0 |
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| 395 | #define rEXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control register 1 |
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| 396 | #define rEXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control register 2 |
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| 397 | #define rEINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved |
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| 398 | #define rEINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved |
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| 399 | #define rEINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control register 2 |
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| 400 | #define rEINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control register 3 |
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| 401 | #define rEINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask |
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| 402 | #define rEINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending |
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| 403 | #define rGSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status |
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| 404 | #define rGSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32440000) |
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| 405 | |
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| 406 | /* RTC */ |
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| 407 | #ifdef __BIG_ENDIAN |
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| 408 | #define rRTCCON (*(volatile unsigned char *)0x57000043) //RTC control |
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| 409 | #define rTICNT (*(volatile unsigned char *)0x57000047) //Tick time count |
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| 410 | #define rRTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control |
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| 411 | #define rALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second |
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| 412 | #define rALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute |
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| 413 | #define rALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour |
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| 414 | #define rALMDATE (*(volatile unsigned char *)0x57000063) //Alarm date //edited by junon |
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| 415 | #define rALMMON (*(volatile unsigned char *)0x57000067) //Alarm month |
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| 416 | #define rALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year |
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| 417 | #define rRTCRST (*(volatile unsigned char *)0x5700006f) //RTC round reset |
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| 418 | #define rBCDSEC (*(volatile unsigned char *)0x57000073) //BCD second |
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| 419 | #define rBCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute |
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| 420 | #define rBCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour |
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| 421 | #define rBCDDATE (*(volatile unsigned char *)0x5700007f) //BCD date //edited by junon |
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| 422 | #define rBCDDAY (*(volatile unsigned char *)0x57000083) //BCD day //edited by junon |
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| 423 | #define rBCDMON (*(volatile unsigned char *)0x57000087) //BCD month |
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| 424 | #define rBCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year |
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| 425 | |
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| 426 | #else //Little Endian |
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| 427 | #define rRTCCON (*(volatile unsigned char *)0x57000040) //RTC control |
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| 428 | #define rTICNT (*(volatile unsigned char *)0x57000044) //Tick time count |
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| 429 | #define rRTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control |
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| 430 | #define rALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second |
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| 431 | #define rALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute |
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| 432 | #define rALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour |
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| 433 | #define rALMDATE (*(volatile unsigned char *)0x57000060) //Alarm date // edited by junon |
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| 434 | #define rALMMON (*(volatile unsigned char *)0x57000064) //Alarm month |
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| 435 | #define rALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year |
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| 436 | #define rRTCRST (*(volatile unsigned char *)0x5700006c) //RTC round reset |
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| 437 | #define rBCDSEC (*(volatile unsigned char *)0x57000070) //BCD second |
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| 438 | #define rBCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute |
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| 439 | #define rBCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour |
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| 440 | #define rBCDDATE (*(volatile unsigned char *)0x5700007c) //BCD date //edited by junon |
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| 441 | #define rBCDDAY (*(volatile unsigned char *)0x57000080) //BCD day //edited by junon |
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| 442 | #define rBCDMON (*(volatile unsigned char *)0x57000084) //BCD month |
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| 443 | #define rBCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year |
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| 444 | #endif //RTC |
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| 445 | |
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| 446 | |
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| 447 | /* ADC */ |
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| 448 | #define rADCCON (*(volatile unsigned *)0x58000000) |
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| 449 | #define rADCTSC (*(volatile unsigned *)0x58000004) |
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| 450 | #define rADCDLY (*(volatile unsigned *)0x58000008) |
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| 451 | #define rADCDAT0 (*(volatile unsigned *)0x5800000c) |
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| 452 | #define rADCDAT1 (*(volatile unsigned *)0x58000010) |
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| 453 | |
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| 454 | |
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| 455 | /* SPI */ |
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| 456 | #define rSPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control |
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| 457 | #define rSPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status |
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| 458 | #define rSPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control |
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| 459 | #define rSPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud rate prescaler |
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| 460 | #define rSPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data |
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| 461 | #define rSPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data |
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| 462 | |
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| 463 | #define rSPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control |
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| 464 | #define rSPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status |
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| 465 | #define rSPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control |
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| 466 | #define rSPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud rate prescaler |
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| 467 | #define rSPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data |
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| 468 | #define rSPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data |
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| 469 | |
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| 470 | /* SD interface */ |
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| 471 | #define rSDICON (*(volatile unsigned *)0x5a000000) //SDI control |
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| 472 | #define rSDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud rate prescaler |
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| 473 | #define rSDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument |
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| 474 | #define rSDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control |
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| 475 | #define rSDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status |
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| 476 | #define rSDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI response 0 |
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| 477 | #define rSDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI response 1 |
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| 478 | #define rSDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI response 2 |
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| 479 | #define rSDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI response 3 |
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| 480 | #define rSDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer |
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| 481 | #define rSDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size |
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| 482 | #define rSDIDATCON (*(volatile unsigned *)0x5a00002c) //SDI data control |
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| 483 | #define rSDIDATCNT (*(volatile unsigned *)0x5a000030) //SDI data remain counter |
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| 484 | #define rSDIDATSTA (*(volatile unsigned *)0x5a000034) //SDI data status |
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| 485 | #define rSDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status |
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| 486 | #define rSDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask. edited for 2440A |
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| 487 | |
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| 488 | #ifdef __BIG_ENDIAN |
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| 489 | #define rSDIDAT (*(volatile unsigned *)0x5a00003F) //SDI data |
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| 490 | #define SDIDAT 0x5a00003F |
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| 491 | #else // Little Endian |
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| 492 | #define rSDIDAT (*(volatile unsigned *)0x5a00003C) //SDI data |
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| 493 | #define SDIDAT 0x5a00003C |
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| 494 | #endif //SD Interface |
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| 495 | |
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| 496 | |
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| 497 | #define _ISR_STARTADDRESS rtems_vector_table |
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| 498 | /* ISR */ |
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| 499 | #define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) |
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| 500 | #define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) |
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| 501 | #define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) |
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| 502 | #define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC)) |
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| 503 | #define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) |
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| 504 | #define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) |
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| 505 | #define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) |
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| 506 | #define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C)) |
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| 507 | |
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| 508 | #define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) |
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| 509 | #define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) |
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| 510 | #define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) |
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| 511 | #define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C)) |
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| 512 | #define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) |
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| 513 | #define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) |
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| 514 | #define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C)) |
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| 515 | #define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) |
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| 516 | #define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) |
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| 517 | #define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) |
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| 518 | #define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C)) |
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| 519 | #define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) |
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| 520 | #define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) |
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| 521 | #define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) |
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| 522 | #define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C)) |
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| 523 | #define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) |
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| 524 | #define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) |
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| 525 | #define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) |
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| 526 | #define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C)) |
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| 527 | #define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) |
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| 528 | #define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74)) |
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| 529 | #define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78)) |
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| 530 | #define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C)) |
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| 531 | #define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) |
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| 532 | #define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) |
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| 533 | #define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C)) |
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| 534 | #define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) |
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| 535 | #define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) |
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| 536 | #define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) |
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| 537 | #define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0)) |
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| 538 | |
---|
| 539 | |
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| 540 | /* PENDING BIT */ |
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| 541 | #define BIT_EINT0 (0x1) |
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| 542 | #define BIT_EINT1 (0x1<<1) |
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| 543 | #define BIT_EINT2 (0x1<<2) |
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| 544 | #define BIT_EINT3 (0x1<<3) |
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| 545 | #define BIT_EINT4_7 (0x1<<4) |
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| 546 | #define BIT_EINT8_23 (0x1<<5) |
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| 547 | #define BIT_BAT_FLT (0x1<<7) |
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| 548 | #define BIT_TICK (0x1<<8) |
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| 549 | #define BIT_WDT (0x1<<9) |
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| 550 | #define BIT_TIMER0 (0x1<<10) |
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| 551 | #define BIT_TIMER1 (0x1<<11) |
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| 552 | #define BIT_TIMER2 (0x1<<12) |
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| 553 | #define BIT_TIMER3 (0x1<<13) |
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| 554 | #define BIT_TIMER4 (0x1<<14) |
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| 555 | #define BIT_UART2 (0x1<<15) |
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| 556 | #define BIT_LCD (0x1<<16) |
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| 557 | #define BIT_DMA0 (0x1<<17) |
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| 558 | #define BIT_DMA1 (0x1<<18) |
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| 559 | #define BIT_DMA2 (0x1<<19) |
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| 560 | #define BIT_DMA3 (0x1<<20) |
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| 561 | #define BIT_SDI (0x1<<21) |
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| 562 | #define BIT_SPI0 (0x1<<22) |
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| 563 | #define BIT_UART1 (0x1<<23) |
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| 564 | #define BIT_USBD (0x1<<25) |
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| 565 | #define BIT_USBH (0x1<<26) |
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| 566 | #define BIT_IIC (0x1<<27) |
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| 567 | #define BIT_UART0 (0x1<<28) |
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| 568 | #define BIT_SPI1 (0x1<<29) |
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| 569 | #define BIT_RTC (0x1<<30) |
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| 570 | #define BIT_ADC (0x1<<31) |
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| 571 | #define BIT_ALLMSK (0xFFFFFFFF) |
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| 572 | |
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| 573 | #define ClearPending(bit) {\ |
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| 574 | rSRCPND = bit;\ |
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| 575 | rINTPND = bit;\ |
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| 576 | rINTPND;\ |
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| 577 | } |
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| 578 | /* Wait until rINTPND is changed for the case that the ISR is very short. */ |
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| 579 | #ifndef __asm__ |
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| 580 | /* Typedefs */ |
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| 581 | typedef union { |
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| 582 | struct _reg { |
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| 583 | unsigned SM_BIT:1; /* Enters STOP mode. This bit isn't be */ |
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| 584 | /* cleared automatically. */ |
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| 585 | unsigned Reserved:1; /* SL_IDLE mode option. This bit isn't cleared */ |
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| 586 | /* automatically. To enter SL_IDLE mode, */ |
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| 587 | /* CLKCON register has to be 0xe. */ |
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| 588 | unsigned IDLE_BIT:1; /* Enters IDLE mode. This bit isn't be cleared */ |
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| 589 | /* automatically. */ |
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| 590 | unsigned POWER_OFF:1; |
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| 591 | unsigned NAND_flash:1; |
---|
| 592 | unsigned LCDC:1; /* Controls HCLK into LCDC block */ |
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| 593 | unsigned USB_host:1; /* Controls HCLK into USB host block */ |
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| 594 | unsigned USB_device:1; /* Controls PCLK into USB device block */ |
---|
| 595 | unsigned PWMTIMER:1; /* Controls PCLK into PWMTIMER block */ |
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| 596 | unsigned SDI:1; /* Controls PCLK into MMC interface block */ |
---|
| 597 | unsigned UART0:1; /* Controls PCLK into UART0 block */ |
---|
| 598 | unsigned UART1:1; /* Controls PCLK into UART1 block */ |
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| 599 | unsigned UART2:1; /* Controls PCLK into UART1 block */ |
---|
| 600 | unsigned GPIO:1; /* Controls PCLK into GPIO block */ |
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| 601 | unsigned RTC:1; /* Controls PCLK into RTC control block. Even if */ |
---|
| 602 | /* this bit is cleared to 0, RTC timer is alive. */ |
---|
| 603 | unsigned ADC:1; /* Controls PCLK into ADC block */ |
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| 604 | unsigned IIC:1; /* Controls PCLK into IIC block */ |
---|
| 605 | unsigned IIS:1; /* Controls PCLK into IIS block */ |
---|
| 606 | unsigned SPI:1; /* Controls PCLK into SPI block */ |
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| 607 | } reg; |
---|
| 608 | unsigned long all; |
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| 609 | } CLKCON; |
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| 610 | |
---|
| 611 | typedef union |
---|
| 612 | { |
---|
| 613 | struct { |
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| 614 | unsigned ENVID:1; /* LCD video output and the logic 1=enable/0=disable. */ |
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| 615 | unsigned BPPMODE:4; /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */ |
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| 616 | /* 1110 = 16 bpp TFT skipmode */ |
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| 617 | unsigned PNRMODE:2; /* TFT: 3 */ |
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| 618 | unsigned MMODE:1; /* This bit determines the toggle rate of the VM. */ |
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| 619 | /* 0 = Each Frame, 1 = The rate defined by the MVAL */ |
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| 620 | unsigned CLKVAL:10; /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */ |
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| 621 | unsigned LINECNT:10; /* (read only) These bits provide the status of the */ |
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| 622 | /* line counter. Down count from LINEVAL to 0 */ |
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| 623 | } reg; |
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| 624 | unsigned long all; |
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| 625 | } LCDCON1; |
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| 626 | |
---|
| 627 | typedef union { |
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| 628 | struct { |
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| 629 | unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */ |
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| 630 | /* VSYNC pulse's high level width by counting the */ |
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| 631 | /* number of inactive lines. */ |
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| 632 | unsigned VFPD:8; /* TFT: Vertical front porch is the number of */ |
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| 633 | /* inactive lines at the end of a frame, before */ |
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| 634 | /* vertical synchronization period. */ |
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| 635 | unsigned LINEVAL:10; /* TFT/STN: These bits determine the vertical size */ |
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| 636 | /* of LCD panel. */ |
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| 637 | unsigned VBPD:8; /* TFT: Vertical back porch is the number of inactive */ |
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| 638 | /* lines at the start of a frame, after */ |
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| 639 | /* vertical synchronization period. */ |
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| 640 | } reg; |
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| 641 | unsigned long all; |
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| 642 | } LCDCON2; |
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| 643 | |
---|
| 644 | typedef union { |
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| 645 | struct { |
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| 646 | unsigned HFPD:8; /* TFT: Horizontal front porch is the number of */ |
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| 647 | /* VCLK periods between the end of active data */ |
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| 648 | /* and the rising edge of HSYNC. */ |
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| 649 | unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */ |
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| 650 | /* size of LCD panel. 2n bytes. */ |
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| 651 | unsigned HBPD:7; /* TFT: Horizontal back porch is the number of VCLK */ |
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| 652 | /* periods between the falling edge of HSYNC and */ |
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| 653 | /* the start of active data. */ |
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| 654 | } reg; |
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| 655 | unsigned long all; |
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| 656 | } LCDCON3; |
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| 657 | |
---|
| 658 | typedef union { |
---|
| 659 | struct { |
---|
| 660 | unsigned HSPW:8; /* TFT: Horizontal sync pulse width determines the */ |
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| 661 | /* HSYNC pulse's high level width by counting the */ |
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| 662 | /* number of the VCLK. */ |
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| 663 | unsigned MVAL:8; /* STN: */ |
---|
| 664 | } reg; |
---|
| 665 | unsigned long all; |
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| 666 | } LCDCON4; |
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| 667 | |
---|
| 668 | typedef union { |
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| 669 | struct { |
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| 670 | unsigned HWSWP:1; /* STN/TFT: Half-Word swap control bit. */ |
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| 671 | /* 0 = Swap Disable 1 = Swap Enable */ |
---|
| 672 | unsigned BSWP:1; /* STN/TFT: Byte swap control bit. */ |
---|
| 673 | /* 0 = Swap Disable 1 = Swap Enable */ |
---|
| 674 | unsigned ENLEND:1; /* TFT: LEND output signal enable/disable. */ |
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| 675 | /* 0 = Disable LEND signal. */ |
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| 676 | /* 1 = Enable LEND signal */ |
---|
| 677 | unsigned PWREN:1; |
---|
| 678 | unsigned INVLEND:1;/* TFT: This bit indicates the LEND signal */ |
---|
| 679 | /* polarity. 0 = normal 1 = inverted */ |
---|
| 680 | unsigned INVPWREN:1; |
---|
| 681 | unsigned INVVDEN:1; /* TFT: This bit indicates the VDEN signal */ |
---|
| 682 | /* polarity. */ |
---|
| 683 | /* 0 = normal 1 = inverted */ |
---|
| 684 | unsigned INVVD:1; /* STN/TFT: This bit indicates the VD (video data) */ |
---|
| 685 | /* pulse polarity. 0 = Normal. */ |
---|
| 686 | /* 1 = VD is inverted. */ |
---|
| 687 | unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */ |
---|
| 688 | /* pulse polarity. 0 = normal 1 = inverted */ |
---|
| 689 | unsigned INVVLINE:1; /* STN/TFT: This bit indicates the VLINE/HSYNC */ |
---|
| 690 | /* pulse polarity. 0 = normal 1 = inverted */ |
---|
| 691 | unsigned INVVCLK:1; /* STN/TFT: This bit controls the polarity of the */ |
---|
| 692 | /* VCLK active edge. 0 = The video data is */ |
---|
| 693 | /* fetched at VCLK falling edge. 1 = The video */ |
---|
| 694 | /* data is fetched at VCLK rising edge */ |
---|
| 695 | unsigned FRM565:1; |
---|
| 696 | unsigned BPP24BL:1; |
---|
| 697 | unsigned HSTATUS:2; /* TFT: Horizontal Status (Read only) */ |
---|
| 698 | /* 00 = HSYNC */ |
---|
| 699 | /* 01 = BACK Porch. */ |
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| 700 | /* 10 = ACTIVE */ |
---|
| 701 | /* 11 = FRONT Porch */ |
---|
| 702 | unsigned VSTATUS:2; /* TFT: Vertical Status (Read only). */ |
---|
| 703 | /* 00 = VSYNC */ |
---|
| 704 | /* 01 = BACK Porch. */ |
---|
| 705 | /* 10 = ACTIVE */ |
---|
| 706 | /* 11 = FRONT Porch */ |
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| 707 | unsigned RESERVED:16; |
---|
| 708 | } reg; |
---|
| 709 | unsigned long all; |
---|
| 710 | } LCDCON5; |
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| 711 | |
---|
| 712 | typedef union { |
---|
| 713 | struct { |
---|
| 714 | unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */ |
---|
| 715 | /* A[21:1] of the start address of the LCD */ |
---|
| 716 | /* frame buffer. */ |
---|
| 717 | unsigned LCDBANK:9; /* A[28:22] */ |
---|
| 718 | } reg; |
---|
| 719 | unsigned long all; |
---|
| 720 | } LCDSADDR1; |
---|
| 721 | |
---|
| 722 | typedef union { |
---|
| 723 | struct { |
---|
| 724 | unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/ |
---|
| 725 | /* of the end address of the LCD frame buffer. */ |
---|
| 726 | /* LCDBASEL = ((the fame end address) >>1) + 1 */ |
---|
| 727 | /* = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */ |
---|
| 728 | } reg; |
---|
| 729 | unsigned long all; |
---|
| 730 | } LCDSADDR2; |
---|
| 731 | |
---|
| 732 | typedef union { |
---|
| 733 | struct { |
---|
| 734 | unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */ |
---|
| 735 | /* words) This value defines the width of the */ |
---|
| 736 | /* view port in the frame */ |
---|
| 737 | unsigned OFFSIZE:11; /* Virtual screen offset size(the number of half */ |
---|
| 738 | /* words) This value defines the difference */ |
---|
| 739 | /* between the address of the last half word */ |
---|
| 740 | /* displayed on the previous LCD line and the */ |
---|
| 741 | /* address of the first half word to be */ |
---|
| 742 | /* displayed in the new LCD line. */ |
---|
| 743 | } reg; |
---|
| 744 | unsigned long all; |
---|
| 745 | } LCDSADDR3; |
---|
| 746 | |
---|
| 747 | /* |
---|
| 748 | * |
---|
| 749 | */ |
---|
| 750 | |
---|
| 751 | typedef union { |
---|
| 752 | struct { |
---|
| 753 | unsigned IISIFENA:1; /* IIS interface enable (start) */ |
---|
| 754 | unsigned IISPSENA:1; /* IIS prescaler enable */ |
---|
| 755 | unsigned RXCHIDLE:1; /* Receive channel idle command */ |
---|
| 756 | unsigned TXCHIDLE:1; /* Transmit channel idle command */ |
---|
| 757 | unsigned RXDMAENA:1; /* Receive DMA service request enable */ |
---|
| 758 | unsigned TXDMAENA:1; /* Transmit DMA service request enable */ |
---|
| 759 | unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */ |
---|
| 760 | unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */ |
---|
| 761 | unsigned LRINDEX:1; /* Left/right channel index (read only) */ |
---|
| 762 | } reg; |
---|
| 763 | unsigned long all; |
---|
| 764 | } IISCON; |
---|
| 765 | |
---|
| 766 | typedef union { |
---|
| 767 | struct { |
---|
| 768 | unsigned SBCLKFS:2; /* Serial bit clock frequency select */ |
---|
| 769 | unsigned MCLKFS:1; /* Master clock frequency select */ |
---|
| 770 | unsigned SDBITS:1; /* Serial data bit per channel */ |
---|
| 771 | unsigned SIFMT:1; /* Serial interface format */ |
---|
| 772 | unsigned ACTLEVCH:1; /* Active level pf left/right channel */ |
---|
| 773 | unsigned TXRXMODE:2; /* Transmit/receive mode select */ |
---|
| 774 | unsigned MODE:1; /* Master/slave mode select */ |
---|
| 775 | } reg; |
---|
| 776 | unsigned long all; |
---|
| 777 | } IISMOD; |
---|
| 778 | |
---|
| 779 | typedef union { |
---|
| 780 | struct { |
---|
| 781 | unsigned PSB:5; /* Prescaler control B */ |
---|
| 782 | unsigned PSA:5; /* Prescaler control A */ |
---|
| 783 | } reg; |
---|
| 784 | unsigned long all; |
---|
| 785 | } IISPSR; |
---|
| 786 | |
---|
| 787 | typedef union { |
---|
| 788 | struct { |
---|
| 789 | unsigned RXFIFOCNT:6; /* (read only) */ |
---|
| 790 | unsigned TXFIFOCNT:6; /* (read only) */ |
---|
| 791 | unsigned RXFIFOENA:1; /* */ |
---|
| 792 | unsigned TXFIFOENA:1; /* */ |
---|
| 793 | unsigned RXFIFOMODE:1; /* */ |
---|
| 794 | unsigned TXFIFOMODE:1; /* */ |
---|
| 795 | } reg; |
---|
| 796 | unsigned long all; |
---|
| 797 | } IISSFIFCON; |
---|
| 798 | |
---|
| 799 | typedef union { |
---|
| 800 | struct { |
---|
| 801 | unsigned FENTRY:16; /* */ |
---|
| 802 | } reg; |
---|
| 803 | unsigned long all; |
---|
| 804 | } IISSFIF; |
---|
| 805 | #endif //__asm__ |
---|
| 806 | |
---|
| 807 | #define LCD_WIDTH 240 |
---|
| 808 | #define LCD_HEIGHT 320 |
---|
| 809 | #define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT)) |
---|
| 810 | |
---|
| 811 | #define SMDK2410_KEY_SELECT 512 |
---|
| 812 | #define SMDK2410_KEY_START 256 |
---|
| 813 | #define SMDK2410_KEY_A 64 |
---|
| 814 | #define SMDK2410_KEY_B 32 |
---|
| 815 | #define SMDK2410_KEY_L 16 |
---|
| 816 | #define SMDK2410_KEY_R 128 |
---|
| 817 | #define SMDK2410_KEY_UP 8 |
---|
| 818 | #define SMDK2410_KEY_DOWN 2 |
---|
| 819 | #define SMDK2410_KEY_LEFT 1 |
---|
| 820 | #define SMDK2410_KEY_RIGHT 4 |
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| 821 | |
---|
| 822 | #endif /*S3C2410_H_*/ |
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