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source: rtems/c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h @ 5e14d89

4.104.114.84.95

Last change on this file since 5e14d89 was 5e14d89, checked in by Joel Sherrill <joel.sherrill@…>, on 09/11/06 at 21:41:56

2006-09-11 Joel Sherrill <joel@…>

at91rm9200/include/at91rm9200.h, at91rm9200/include/at91rm9200_dbgu.h, at91rm9200/include/at91rm9200_emac.h, at91rm9200/include/at91rm9200_gpio.h, at91rm9200/include/at91rm9200_mem.h, at91rm9200/include/at91rm9200_pmc.h, s3c2400/include/s3c2400.h: Convert C++ style comments to C style.

Property mode set to 100644

File size: 29.6 KB

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1	/************************************************
2	* NAME : s3c2400.h
3	* Version : 3.7.2002
4	*
5	* Based on 24x.h for the Samsung Development Board
6	************************************************/
7
8	#ifndef S3C2400_H_
9	#define S3C2400_H_
10
11	/* Memory control */
12	#define rBWSCON ((volatile unsigned )0x14000000)
13	#define rBANKCON0 ((volatile unsigned )0x14000004)
14	#define rBANKCON1 ((volatile unsigned )0x14000008)
15	#define rBANKCON2 ((volatile unsigned )0x1400000C)
16	#define rBANKCON3 ((volatile unsigned )0x14000010)
17	#define rBANKCON4 ((volatile unsigned )0x14000014)
18	#define rBANKCON5 ((volatile unsigned )0x14000018)
19	#define rBANKCON6 ((volatile unsigned )0x1400001C)
20	#define rBANKCON7 ((volatile unsigned )0x14000020)
21	#define rREFRESH ((volatile unsigned )0x14000024)
22	#define rBANKSIZE ((volatile unsigned )0x14000028)
23	#define rMRSRB6 ((volatile unsigned )0x1400002C)
24	#define rMRSRB7 ((volatile unsigned )0x14000030)
25
26
27	/* INTERRUPT */
28	#define rSRCPND ((volatile unsigned )0x14400000)
29	#define rINTMOD ((volatile unsigned )0x14400004)
30	#define rINTMSK ((volatile unsigned )0x14400008)
31	#define rPRIORITY ((volatile unsigned )0x1440000C)
32	#define rINTPND ((volatile unsigned )0x14400010)
33	#define rINTOFFSET ((volatile unsigned )0x14400014)
34
35
36	/* DMA */
37	#define rDISRC0 ((volatile unsigned )0x14600000)
38	#define rDIDST0 ((volatile unsigned )0x14600004)
39	#define rDCON0 ((volatile unsigned )0x14600008)
40	#define rDSTAT0 ((volatile unsigned )0x1460000C)
41	#define rDCSRC0 ((volatile unsigned )0x14600010)
42	#define rDCDST0 ((volatile unsigned )0x14600014)
43	#define rDMASKTRIG0 ((volatile unsigned )0x14600018)
44	#define rDISRC1 ((volatile unsigned )0x14600020)
45	#define rDIDST1 ((volatile unsigned )0x14600024)
46	#define rDCON1 ((volatile unsigned )0x14600028)
47	#define rDSTAT1 ((volatile unsigned )0x1460002C)
48	#define rDCSRC1 ((volatile unsigned )0x14600030)
49	#define rDCDST1 ((volatile unsigned )0x14600034)
50	#define rDMASKTRIG1 ((volatile unsigned )0x14600038)
51	#define rDISRC2 ((volatile unsigned )0x14600040)
52	#define rDIDST2 ((volatile unsigned )0x14600044)
53	#define rDCON2 ((volatile unsigned )0x14600048)
54	#define rDSTAT2 ((volatile unsigned )0x1460004C)
55	#define rDCSRC2 ((volatile unsigned )0x14600050)
56	#define rDCDST2 ((volatile unsigned )0x14600054)
57	#define rDMASKTRIG2 ((volatile unsigned )0x14600058)
58	#define rDISRC3 ((volatile unsigned )0x14600060)
59	#define rDIDST3 ((volatile unsigned )0x14600064)
60	#define rDCON3 ((volatile unsigned )0x14600068)
61	#define rDSTAT3 ((volatile unsigned )0x1460006C)
62	#define rDCSRC3 ((volatile unsigned )0x14600070)
63	#define rDCDST3 ((volatile unsigned )0x14600074)
64	#define rDMASKTRIG3 ((volatile unsigned )0x14600078)
65
66
67	/* CLOCK & POWER MANAGEMENT */
68	#define rLOCKTIME ((volatile unsigned )0x14800000)
69	#define rMPLLCON ((volatile unsigned )0x14800004)
70	#define rUPLLCON ((volatile unsigned )0x14800008)
71	#define rCLKCON ((volatile unsigned )0x1480000C)
72	#define rCLKSLOW ((volatile unsigned )0x14800010)
73	#define rCLKDIVN ((volatile unsigned )0x14800014)
74
75
76	/* LCD CONTROLLER */
77	#define rLCDCON1 ((volatile unsigned )0x14A00000)
78	#define rLCDCON2 ((volatile unsigned )0x14A00004)
79	#define rLCDCON3 ((volatile unsigned )0x14A00008)
80	#define rLCDCON4 ((volatile unsigned )0x14A0000C)
81	#define rLCDCON5 ((volatile unsigned )0x14A00010)
82	#define rLCDSADDR1 ((volatile unsigned )0x14A00014)
83	#define rLCDSADDR2 ((volatile unsigned )0x14A00018)
84	#define rLCDSADDR3 ((volatile unsigned )0x14A0001C)
85	#define rREDLUT ((volatile unsigned )0x14A00020)
86	#define rGREENLUT ((volatile unsigned )0x14A00024)
87	#define rBLUELUT ((volatile unsigned )0x14A00028)
88	#define rDP1_2 ((volatile unsigned )0x14A0002C)
89	#define rDP4_7 ((volatile unsigned )0x14A00030)
90	#define rDP3_5 ((volatile unsigned )0x14A00034)
91	#define rDP2_3 ((volatile unsigned )0x14A00038)
92	#define rDP5_7 ((volatile unsigned )0x14A0003c)
93	#define rDP3_4 ((volatile unsigned )0x14A00040)
94	#define rDP4_5 ((volatile unsigned )0x14A00044)
95	#define rDP6_7 ((volatile unsigned )0x14A00048)
96	#define rDITHMODE ((volatile unsigned )0x14A0004C)
97	#define rTPAL ((volatile unsigned )0x14A00050)
98	#define GP32_PALETTE ((volatile unsigned )0x14A00400) /* SJS */
99
100
101	/* UART */
102	#define rULCON0 ((volatile unsigned char )0x15000000)
103	#define rUCON0 ((volatile unsigned short )0x15000004)
104	#define rUFCON0 ((volatile unsigned char )0x15000008)
105	#define rUMCON0 ((volatile unsigned char )0x1500000C)
106	#define rUTRSTAT0 ((volatile unsigned char )0x15000010)
107	#define rUERSTAT0 ((volatile unsigned char )0x15000014)
108	#define rUFSTAT0 ((volatile unsigned short )0x15000018)
109	#define rUMSTAT0 ((volatile unsigned char )0x1500001C)
110	#define rUBRDIV0 ((volatile unsigned short )0x15000028)
111
112	#define rULCON1 ((volatile unsigned char )0x15004000)
113	#define rUCON1 ((volatile unsigned short )0x15004004)
114	#define rUFCON1 ((volatile unsigned char )0x15004008)
115	#define rUMCON1 ((volatile unsigned char )0x1500400C)
116	#define rUTRSTAT1 ((volatile unsigned char )0x15004010)
117	#define rUERSTAT1 ((volatile unsigned char )0x15004014)
118	#define rUFSTAT1 ((volatile unsigned short )0x15004018)
119	#define rUMSTAT1 ((volatile unsigned char )0x1500401C)
120	#define rUBRDIV1 ((volatile unsigned short )0x15004028)
121
122	#ifdef __BIG_ENDIAN
123	#define rUTXH0 ((volatile unsigned char )0x15000023)
124	#define rURXH0 ((volatile unsigned char )0x15000027)
125	#define rUTXH1 ((volatile unsigned char )0x15004023)
126	#define rURXH1 ((volatile unsigned char )0x15004027)
127
128	#define WrUTXH0(ch) ((volatile unsigned char )0x15000023)=(unsigned char)(ch)
129	#define RdURXH0() ((volatile unsigned char )0x15000027)
130	#define WrUTXH1(ch) ((volatile unsigned char )0x15004023)=(unsigned char)(ch)
131	#define RdURXH1() ((volatile unsigned char )0x15004027)
132
133	#define UTXH0 (0x15000020+3) /* byte_access address by DMA */
134	#define URXH0 (0x15000024+3)
135	#define UTXH1 (0x15004020+3)
136	#define URXH1 (0x15004024+3)
137
138	#else /* Little Endian */
139	#define rUTXH0 ((volatile unsigned char )0x15000020)
140	#define rURXH0 ((volatile unsigned char )0x15000024)
141	#define rUTXH1 ((volatile unsigned char )0x15004020)
142	#define rURXH1 ((volatile unsigned char )0x15004024)
143
144	#define WrUTXH0(ch) ((volatile unsigned char )0x15000020)=(unsigned char)(ch)
145	#define RdURXH0() ((volatile unsigned char )0x15000024)
146	#define WrUTXH1(ch) ((volatile unsigned char )0x15004020)=(unsigned char)(ch)
147	#define RdURXH1() ((volatile unsigned char )0x15004024)
148
149	#define UTXH0 (0x15000020) /* byte_access address by DMA */
150	#define URXH0 (0x15000024)
151	#define UTXH1 (0x15004020)
152	#define URXH1 (0x15004024)
153	#endif
154
155
156	/* PWM TIMER */
157	#define rTCFG0 ((volatile unsigned )0x15100000)
158	#define rTCFG1 ((volatile unsigned )0x15100004)
159	#define rTCON ((volatile unsigned )0x15100008)
160	#define rTCNTB0 ((volatile unsigned )0x1510000C)
161	#define rTCMPB0 ((volatile unsigned )0x15100010)
162	#define rTCNTO0 ((volatile unsigned )0x15100014)
163	#define rTCNTB1 ((volatile unsigned )0x15100018)
164	#define rTCMPB1 ((volatile unsigned )0x1510001C)
165	#define rTCNTO1 ((volatile unsigned )0x15100020)
166	#define rTCNTB2 ((volatile unsigned )0x15100024)
167	#define rTCMPB2 ((volatile unsigned )0x15100028)
168	#define rTCNTO2 ((volatile unsigned )0x1510002C)
169	#define rTCNTB3 ((volatile unsigned )0x15100030)
170	#define rTCMPB3 ((volatile unsigned )0x15100034)
171	#define rTCNTO3 ((volatile unsigned )0x15100038)
172	#define rTCNTB4 ((volatile unsigned )0x1510003C)
173	#define rTCNTO4 ((volatile unsigned )0x15100040)
174
175
176	/* USB DEVICE */
177	#define rFUNC_ADDR_REG ((volatile unsigned )0x15200140)
178	#define rPWR_REG ((volatile unsigned )0x15200144)
179	#define rINT_REG ((volatile unsigned )0x15200148)
180	#define rINT_MASK_REG ((volatile unsigned )0x1520014C)
181	#define rFRAME_NUM_REG ((volatile unsigned )0x15200150)
182	#define rRESUME_CON_REG ((volatile unsigned )0x15200154)
183	#define rEP0_CSR ((volatile unsigned )0x15200160)
184	#define rEP0_MAXP ((volatile unsigned )0x15200164)
185	#define rEP0_OUT_CNT ((volatile unsigned )0x15200168)
186	#define rEP0_FIFO ((volatile unsigned )0x1520016C)
187	#define rEP1_IN_CSR ((volatile unsigned )0x15200180)
188	#define rEP1_IN_MAXP ((volatile unsigned )0x15200184)
189	#define rEP1_FIFO ((volatile unsigned )0x15200188)
190	#define rEP2_IN_CSR ((volatile unsigned )0x15200190)
191	#define rEP2_IN_MAXP ((volatile unsigned )0x15200194)
192	#define rEP2_FIFO ((volatile unsigned )0x15200198)
193	#define rEP3_OUT_CSR ((volatile unsigned )0x152001A0)
194	#define rEP3_OUT_MAXP ((volatile unsigned )0x152001A4)
195	#define rEP3_OUT_CNT ((volatile unsigned )0x152001A8)
196	#define rEP3_FIFO ((volatile unsigned )0x152001AC)
197	#define rEP4_OUT_CSR ((volatile unsigned )0x152001B0)
198	#define rEP4_OUT_MAXP ((volatile unsigned )0x152001B4)
199	#define rEP4_OUT_CNT ((volatile unsigned )0x152001B8)
200	#define rEP4_FIFO ((volatile unsigned )0x152001BC)
201	#define rDMA_CON ((volatile unsigned )0x152001C0)
202	#define rDMA_UNIT ((volatile unsigned )0x152001C4)
203	#define rDMA_FIFO ((volatile unsigned )0x152001C8)
204	#define rDMA_TX ((volatile unsigned )0x152001CC)
205	#define rTEST_MODE ((volatile unsigned )0x152001F4)
206	#define rIN_CON_REG ((volatile unsigned )0x152001F8)
207
208
209	/* WATCH DOG TIMER */
210	#define rWTCON ((volatile unsigned )0x15300000)
211	#define rWTDAT ((volatile unsigned )0x15300004)
212	#define rWTCNT ((volatile unsigned )0x15300008)
213
214
215	/* IIC */
216	#define rIICCON ((volatile unsigned )0x15400000)
217	#define rIICSTAT ((volatile unsigned )0x15400004)
218	#define rIICADD ((volatile unsigned )0x15400008)
219	#define rIICDS ((volatile unsigned )0x1540000C)
220
221
222	/* IIS */
223	#define rIISCON ((volatile unsigned )0x15508000)
224	#define rIISMOD ((volatile unsigned )0x15508004)
225	#define rIISPSR ((volatile unsigned )0x15508008)
226	#define rIISFIFCON ((volatile unsigned )0x1550800C)
227
228	#ifdef __BIG_ENDIAN
229	#define IISFIF ((volatile unsigned short *)0x15508012)
230
231	#else /* Little Endian */
232	#define IISFIF ((volatile unsigned short *)0x15508010)
233	#endif
234
235
236	/* I/O PORT */
237	#define rPACON ((volatile unsigned )0x15600000)
238	#define rPADAT ((volatile unsigned )0x15600004)
239
240	#define rPBCON ((volatile unsigned )0x15600008)
241	#define rPBDAT ((volatile unsigned )0x1560000C)
242	#define rPBUP ((volatile unsigned )0x15600010)
243
244	#define rPCCON ((volatile unsigned )0x15600014)
245	#define rPCDAT ((volatile unsigned )0x15600018)
246	#define rPCUP ((volatile unsigned )0x1560001C)
247
248	#define rPDCON ((volatile unsigned )0x15600020)
249	#define rPDDAT ((volatile unsigned )0x15600024)
250	#define rPDUP ((volatile unsigned )0x15600028)
251
252	#define rPECON ((volatile unsigned )0x1560002C)
253	#define rPEDAT ((volatile unsigned )0x15600030)
254	#define rPEUP ((volatile unsigned )0x15600034)
255
256	#define rPFCON ((volatile unsigned )0x15600038)
257	#define rPFDAT ((volatile unsigned )0x1560003C)
258	#define rPFUP ((volatile unsigned )0x15600040)
259
260	#define rPGCON ((volatile unsigned )0x15600044)
261	#define rPGDAT ((volatile unsigned )0x15600048)
262	#define rPGUP ((volatile unsigned )0x1560004C)
263
264	#define rOPENCR ((volatile unsigned )0x15600050)
265	#define rMISCCR ((volatile unsigned )0x15600054)
266	#define rEXTINT ((volatile unsigned )0x15600058)
267
268
269	/* RTC */
270	#ifdef __BIG_ENDIAN
271	#define rRTCCON ((volatile unsigned char )0x15700043)
272	#define rRTCALM ((volatile unsigned char )0x15700053)
273	#define rALMSEC ((volatile unsigned char )0x15700057)
274	#define rALMMIN ((volatile unsigned char )0x1570005B)
275	#define rALMHOUR ((volatile unsigned char )0x1570005F)
276	#define rALMDAY ((volatile unsigned char )0x15700063)
277	#define rALMMON ((volatile unsigned char )0x15700067)
278	#define rALMYEAR ((volatile unsigned char )0x1570006B)
279	#define rRTCRST ((volatile unsigned char )0x1570006F)
280	#define rBCDSEC ((volatile unsigned char )0x15700073)
281	#define rBCDMIN ((volatile unsigned char )0x15700077)
282	#define rBCDHOUR ((volatile unsigned char )0x1570007B)
283	#define rBCDDAY ((volatile unsigned char )0x1570007F)
284	#define rBCDDATE ((volatile unsigned char )0x15700083)
285	#define rBCDMON ((volatile unsigned char )0x15700087)
286	#define rBCDYEAR ((volatile unsigned char )0x1570008B)
287	#define rTICINT ((volatile unsigned char )0x15700047)
288
289	#else /* Little Endian */
290	#define rRTCCON ((volatile unsigned char )0x15700040)
291	#define rRTCALM ((volatile unsigned char )0x15700050)
292	#define rALMSEC ((volatile unsigned char )0x15700054)
293	#define rALMMIN ((volatile unsigned char )0x15700058)
294	#define rALMHOUR ((volatile unsigned char )0x1570005C)
295	#define rALMDAY ((volatile unsigned char )0x15700060)
296	#define rALMMON ((volatile unsigned char )0x15700064)
297	#define rALMYEAR ((volatile unsigned char )0x15700068)
298	#define rRTCRST ((volatile unsigned char )0x1570006C)
299	#define rBCDSEC ((volatile unsigned char )0x15700070)
300	#define rBCDMIN ((volatile unsigned char )0x15700074)
301	#define rBCDHOUR ((volatile unsigned char )0x15700078)
302	#define rBCDDAY ((volatile unsigned char )0x1570007C)
303	#define rBCDDATE ((volatile unsigned char )0x15700080)
304	#define rBCDMON ((volatile unsigned char )0x15700084)
305	#define rBCDYEAR ((volatile unsigned char )0x15700088)
306	#define rTICINT ((volatile unsigned char )0x15700044)
307	#endif
308
309
310	/* ADC */
311	#define rADCCON ((volatile unsigned )0x15800000)
312	#define rADCDAT ((volatile unsigned )0x15800004)
313
314
315	/* SPI */
316	#define rSPCON ((volatile unsigned )0x15900000)
317	#define rSPSTA ((volatile unsigned )0x15900004)
318	#define rSPPIN ((volatile unsigned )0x15900008)
319	#define rSPPRE ((volatile unsigned )0x1590000C)
320	#define rSPTDAT ((volatile unsigned )0x15900010)
321	#define rSPRDAT ((volatile unsigned )0x15900014)
322
323
324	/* MMC INTERFACE */
325	#define rMMCON ((volatile unsigned )0x15a00000)
326	#define rMMCRR ((volatile unsigned )0x15a00004)
327	#define rMMFCON ((volatile unsigned )0x15a00008)
328	#define rMMSTA ((volatile unsigned )0x15a0000C)
329	#define rMMFSTA ((volatile unsigned )0x15a00010)
330	#define rMMPRE ((volatile unsigned )0x15a00014)
331	#define rMMLEN ((volatile unsigned )0x15a00018)
332	#define rMMCR7 ((volatile unsigned )0x15a0001C)
333	#define rMMRSP0 ((volatile unsigned )0x15a00020)
334	#define rMMRSP1 ((volatile unsigned )0x15a00024)
335	#define rMMRSP2 ((volatile unsigned )0x15a00028)
336	#define rMMRSP3 ((volatile unsigned )0x15a0002C)
337	#define rMMCMD0 ((volatile unsigned )0x15a00030)
338	#define rMMCMD1 ((volatile unsigned )0x15a00034)
339	#define rMMCR16 ((volatile unsigned )0x15a00038)
340	#define rMMDAT ((volatile unsigned )0x15a0003C)
341
342
343	#define _ISR_STARTADDRESS rtems_vector_table
344	/* ISR */
345	#define pISR_RESET ((unsigned )(_ISR_STARTADDRESS+0x0))
346	#define pISR_UNDEF ((unsigned )(_ISR_STARTADDRESS+0x4))
347	#define pISR_SWI ((unsigned )(_ISR_STARTADDRESS+0x8))
348	#define pISR_PABORT ((unsigned )(_ISR_STARTADDRESS+0xC))
349	#define pISR_DABORT ((unsigned )(_ISR_STARTADDRESS+0x10))
350	#define pISR_RESERVED ((unsigned )(_ISR_STARTADDRESS+0x14))
351	#define pISR_IRQ ((unsigned )(_ISR_STARTADDRESS+0x18))
352	#define pISR_FIQ ((unsigned )(_ISR_STARTADDRESS+0x1C))
353
354	#define pISR_EINT0 ((unsigned )(_ISR_STARTADDRESS+0x20))
355	#define pISR_EINT1 ((unsigned )(_ISR_STARTADDRESS+0x24))
356	#define pISR_EINT2 ((unsigned )(_ISR_STARTADDRESS+0x28))
357	#define pISR_EINT3 ((unsigned )(_ISR_STARTADDRESS+0x2C))
358	#define pISR_EINT4 ((unsigned )(_ISR_STARTADDRESS+0x30))
359	#define pISR_EINT5 ((unsigned )(_ISR_STARTADDRESS+0x34))
360	#define pISR_EINT6 ((unsigned )(_ISR_STARTADDRESS+0x38))
361	#define pISR_EINT7 ((unsigned )(_ISR_STARTADDRESS+0x3C))
362	#define pISR_TICK ((unsigned )(_ISR_STARTADDRESS+0x40))
363	#define pISR_WDT ((unsigned )(_ISR_STARTADDRESS+0x44))
364	#define pISR_TIMER0 ((unsigned )(_ISR_STARTADDRESS+0x48))
365	#define pISR_TIMER1 ((unsigned )(_ISR_STARTADDRESS+0x4C))
366	#define pISR_TIMER2 ((unsigned )(_ISR_STARTADDRESS+0x50))
367	#define pISR_TIMER3 ((unsigned )(_ISR_STARTADDRESS+0x54))
368	#define pISR_TIMER4 ((unsigned )(_ISR_STARTADDRESS+0x58))
369	#define pISR_UERR01 ((unsigned )(_ISR_STARTADDRESS+0x5C))
370	#define pISR_NOTUSED ((unsigned )(_ISR_STARTADDRESS+0x60))
371	#define pISR_DMA0 ((unsigned )(_ISR_STARTADDRESS+0x64))
372	#define pISR_DMA1 ((unsigned )(_ISR_STARTADDRESS+0x68))
373	#define pISR_DMA2 ((unsigned )(_ISR_STARTADDRESS+0x6C))
374	#define pISR_DMA3 ((unsigned )(_ISR_STARTADDRESS+0x70))
375	#define pISR_MMC ((unsigned )(_ISR_STARTADDRESS+0x74))
376	#define pISR_SPI ((unsigned )(_ISR_STARTADDRESS+0x78))
377	#define pISR_URXD0 ((unsigned )(_ISR_STARTADDRESS+0x7C))
378	#define pISR_URXD1 ((unsigned )(_ISR_STARTADDRESS+0x80))
379	#define pISR_USBD ((unsigned )(_ISR_STARTADDRESS+0x84))
380	#define pISR_USBH ((unsigned )(_ISR_STARTADDRESS+0x88))
381	#define pISR_IIC ((unsigned )(_ISR_STARTADDRESS+0x8C))
382	#define pISR_UTXD0 ((unsigned )(_ISR_STARTADDRESS+0x90))
383	#define pISR_UTXD1 ((unsigned )(_ISR_STARTADDRESS+0x94))
384	#define pISR_RTC ((unsigned )(_ISR_STARTADDRESS+0x98))
385	#define pISR_ADC ((unsigned )(_ISR_STARTADDRESS+0xA0))
386
387
388	/* PENDING BIT */
389	#define BIT_EINT0 (0x1)
390	#define BIT_EINT1 (0x1<<1)
391	#define BIT_EINT2 (0x1<<2)
392	#define BIT_EINT3 (0x1<<3)
393	#define BIT_EINT4 (0x1<<4)
394	#define BIT_EINT5 (0x1<<5)
395	#define BIT_EINT6 (0x1<<6)
396	#define BIT_EINT7 (0x1<<7)
397	#define BIT_TICK (0x1<<8)
398	#define BIT_WDT (0x1<<9)
399	#define BIT_TIMER0 (0x1<<10)
400	#define BIT_TIMER1 (0x1<<11)
401	#define BIT_TIMER2 (0x1<<12)
402	#define BIT_TIMER3 (0x1<<13)
403	#define BIT_TIMER4 (0x1<<14)
404	#define BIT_UERR01 (0x1<<15)
405	#define BIT_NOTUSED (0x1<<16)
406	#define BIT_DMA0 (0x1<<17)
407	#define BIT_DMA1 (0x1<<18)
408	#define BIT_DMA2 (0x1<<19)
409	#define BIT_DMA3 (0x1<<20)
410	#define BIT_MMC (0x1<<21)
411	#define BIT_SPI (0x1<<22)
412	#define BIT_URXD0 (0x1<<23)
413	#define BIT_URXD1 (0x1<<24)
414	#define BIT_USBD (0x1<<25)
415	#define BIT_USBH (0x1<<26)
416	#define BIT_IIC (0x1<<27)
417	#define BIT_UTXD0 (0x1<<28)
418	#define BIT_UTXD1 (0x1<<29)
419	#define BIT_RTC (0x1<<30)
420	#define BIT_ADC (0x1<<31)
421	#define BIT_ALLMSK (0xFFFFFFFF)
422
423	#define ClearPending(bit) {\
424	rSRCPND = bit;\
425	rINTPND = bit;\
426	rINTPND;\
427	}
428	/* Wait until rINTPND is changed for the case that the ISR is very short. */
429
430	/* Typedefs */
431	typedef union {
432	struct _reg {
433	unsigned STOP_BIT:1; /* Enters STOP mode. This bit isn't be */
434	/* cleared automatically. */
435	unsigned SL_IDLE:1; /* SL_IDLE mode option. This bit isn't cleared */
436	/* automatically. To enter SL_IDLE mode, */
437	/* CLKCON register has to be 0xe. */
438	unsigned IDLE_BIT:1; /* Enters IDLE mode. This bit isn't be cleared */
439	/* automatically. */
440	unsigned LCDC:1; /* Controls HCLK into LCDC block */
441	unsigned USB_host:1; /* Controls HCLK into USB host block */
442	unsigned USB_device:1; /* Controls PCLK into USB device block */
443	unsigned PWMTIMER:1; /* Controls PCLK into PWMTIMER block */
444	unsigned MMC:1; /* Controls PCLK into MMC interface block */
445	unsigned UART0:1; /* Controls PCLK into UART0 block */
446	unsigned UART1:1; /* Controls PCLK into UART1 block */
447	unsigned GPIO:1; /* Controls PCLK into GPIO block */
448	unsigned RTC:1; /* Controls PCLK into RTC control block. Even if */
449	/* this bit is cleared to 0, RTC timer is alive. */
450	unsigned ADC:1; /* Controls PCLK into ADC block */
451	unsigned IIC:1; /* Controls PCLK into IIC block */
452	unsigned IIS:1; /* Controls PCLK into IIS block */
453	unsigned SPI:1; /* Controls PCLK into SPI block */
454	} reg;
455	unsigned long all;
456	} CLKCON;
457
458	typedef union
459	{
460	struct {
461	unsigned ENVID:1; /* LCD video output and the logic 1=enable/0=disable. */
462	unsigned BPPMODE:4; /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */
463	/* 1110 = 16 bpp TFT skipmode */
464	unsigned PNRMODE:2; /* TFT: 3 */
465	unsigned MMODE:1; /* This bit determines the toggle rate of the VM. */
466	/* 0 = Each Frame, 1 = The rate defined by the MVAL */
467	unsigned CLKVAL:10; /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */
468	unsigned LINECNT:10; /* (read only) These bits provide the status of the */
469	/* line counter. Down count from LINEVAL to 0 */
470	} reg;
471	unsigned long all;
472	} LCDCON1;
473
474	typedef union {
475	struct {
476	unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */
477	/* VSYNC pulse's high level width by counting the */
478	/* number of inactive lines. */
479	unsigned VFPD:8; /* TFT: Vertical front porch is the number of */
480	/* inactive lines at the end of a frame, before */
481	/* vertical synchronization period. */
482	unsigned LINEVAL:10; /* TFT/STN: These bits determine the vertical size */
483	/* of LCD panel. */
484	unsigned VBPD:8; /* TFT: Vertical back porch is the number of inactive */
485	/* lines at the start of a frame, after */
486	/* vertical synchronization period. */
487	} reg;
488	unsigned long all;
489	} LCDCON2;
490
491	typedef union {
492	struct {
493	unsigned HFPD:8; /* TFT: Horizontal front porch is the number of */
494	/* VCLK periods between the end of active data */
495	/* and the rising edge of HSYNC. */
496	unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */
497	/* size of LCD panel. 2n bytes. */
498	unsigned HBPD:7; /* TFT: Horizontal back porch is the number of VCLK */
499	/* periods between the falling edge of HSYNC and */
500	/* the start of active data. */
501	} reg;
502	unsigned long all;
503	} LCDCON3;
504
505	typedef union {
506	struct {
507	unsigned HSPW:8; /* TFT: Horizontal sync pulse width determines the */
508	/* HSYNC pulse's high level width by counting the */
509	/* number of the VCLK. */
510	unsigned MVAL:8; /* STN: */
511	unsigned ADDVAL:8; /* TFT: Palette Index offset value */
512	unsigned PALADDEN:1; /* TFT: Palette Index offset enable. */
513	/* 0 = Disable 1 = Enable */
514	} reg;
515	unsigned long all;
516	} LCDCON4;
517
518	typedef union {
519	struct {
520	unsigned HWSWP:1; /* STN/TFT: Half-Word swap control bit. */
521	/* 0 = Swap Disable 1 = Swap Enable */
522	unsigned BSWP:1; /* STN/TFT: Byte swap control bit. */
523	/* 0 = Swap Disable 1 = Swap Enable */
524	unsigned ENLEND:1; /* TFT: LEND output signal enable/disable. */
525	/* 0 = Disable LEND signal. */
526	/* 1 = Enable LEND signal */
527	unsigned RESERVED1:1;
528	unsigned INVENDLINE:1;/* TFT: This bit indicates the LEND signal */
529	/* polarity. 0 = normal 1 = inverted */
530	unsigned RESERVED2:1;
531	unsigned INVVDEN:1; /* TFT: This bit indicates the VDEN signal */
532	/* polarity. */
533	/* 0 = normal 1 = inverted */
534	unsigned INVVD:1; /* STN/TFT: This bit indicates the VD (video data) */
535	/* pulse polarity. 0 = Normal. */
536	/* 1 = VD is inverted. */
537	unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */
538	/* pulse polarity. 0 = normal 1 = inverted */
539	unsigned INVVLINE:1; /* STN/TFT: This bit indicates the VLINE/HSYNC */
540	/* pulse polarity. 0 = normal 1 = inverted */
541	unsigned INVVCLK:1; /* STN/TFT: This bit controls the polarity of the */
542	/* VCLK active edge. 0 = The video data is */
543	/* fetched at VCLK falling edge. 1 = The video */
544	/* data is fetched at VCLK rising edge */
545	unsigned RESERVED3:2;
546	unsigned SELFREF:1; /* STN: */
547	unsigned SLOWCLKSYNC:1; /* STN: */
548	unsigned RESERVED4:2; /* must be 0 */
549	unsigned HSTATUS:2; /* TFT: Horizontal Status (Read only) */
550	/* 00 = HSYNC */
551	/* 01 = BACK Porch. */
552	/* 10 = ACTIVE */
553	/* 11 = FRONT Porch */
554	unsigned VSTATUS:2; /* TFT: Vertical Status (Read only). */
555	/* 00 = VSYNC */
556	/* 01 = BACK Porch. */
557	/* 10 = ACTIVE */
558	/* 11 = FRONT Porch */
559	} reg;
560	unsigned long all;
561	} LCDCON5;
562
563	typedef union {
564	struct {
565	unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */
566	/* A[21:1] of the start address of the LCD */
567	/* frame buffer. */
568	unsigned LCDBANK:7; /* A[28:22] */
569	} reg;
570	unsigned long all;
571	} LCDSADDR1;
572
573	typedef union {
574	struct {
575	unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/
576	/* of the end address of the LCD frame buffer. */
577	/* LCDBASEL = ((the fame end address) >>1) + 1 */
578	/* = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */
579	} reg;
580	unsigned long all;
581	} LCDSADDR2;
582
583	typedef union {
584	struct {
585	unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */
586	/* words) This value defines the width of the */
587	/* view port in the frame */
588	unsigned OFFSIZE:11; /* Virtual screen offset size(the number of half */
589	/* words) This value defines the difference */
590	/* between the address of the last half word */
591	/* displayed on the previous LCD line and the */
592	/* address of the first half word to be */
593	/* displayed in the new LCD line. */
594	} reg;
595	unsigned long all;
596	} LCDSADDR3;
597
598	/*
599	*
600	*/
601
602	typedef union {
603	struct {
604	unsigned IISIFENA:1; /* IIS interface enable (start) */
605	unsigned IISPSENA:1; /* IIS prescaler enable */
606	unsigned RXCHIDLE:1; /* Receive channel idle command */
607	unsigned TXCHIDLE:1; /* Transmit channel idle command */
608	unsigned RXDMAENA:1; /* Receive DMA service request enable */
609	unsigned TXDMAENA:1; /* Transmit DMA service request enable */
610	unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */
611	unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */
612	unsigned LRINDEX:1; /* Left/right channel index (read only) */
613	} reg;
614	unsigned long all;
615	} IISCON;
616
617	typedef union {
618	struct {
619	unsigned SBCLKFS:2; /* Serial bit clock frequency select */
620	unsigned MCLKFS:1; /* Master clock frequency select */
621	unsigned SDBITS:1; /* Serial data bit per channel */
622	unsigned SIFMT:1; /* Serial interface format */
623	unsigned ACTLEVCH:1; /* Active level pf left/right channel */
624	unsigned TXRXMODE:2; /* Transmit/receive mode select */
625	unsigned MODE:1; /* Master/slave mode select */
626	} reg;
627	unsigned long all;
628	} IISMOD;
629
630	typedef union {
631	struct {
632	unsigned PSB:5; /* Prescaler control B */
633	unsigned PSA:5; /* Prescaler control A */
634	} reg;
635	unsigned long all;
636	} IISPSR;
637
638	typedef union {
639	struct {
640	unsigned RXFIFOCNT:4; /* (read only) */
641	unsigned TXFIFOCNT:4; /* (read only) */
642	/signed RXFIFOENA:1; / */
643	unsigned TXFIFOENA:1; /* */
644	unsigned RXFIFOMODE:1; /* */
645	unsigned TXFIFOMODE:1; /* */
646	} reg;
647	unsigned long all;
648	} IISSFIFCON;
649
650	typedef union {
651	struct {
652	unsigned FENTRY:16; /* */
653	} reg;
654	unsigned long all;
655	} IISSFIF;
656
657
658	#define LCD_WIDTH 240
659	#define LCD_HEIGHT 320
660	#define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT))
661
662	#define GP32_KEY_SELECT 512
663	#define GP32_KEY_START 256
664	#define GP32_KEY_A 64
665	#define GP32_KEY_B 32
666	#define GP32_KEY_L 16
667	#define GP32_KEY_R 128
668	#define GP32_KEY_UP 8
669	#define GP32_KEY_DOWN 2
670	#define GP32_KEY_LEFT 1
671	#define GP32_KEY_RIGHT 4
672
673	#endif /S3C2400_H_/

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