1 | /************************************************ |
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2 | * NAME : s3c2400.h |
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3 | * Version : 3.7.2002 |
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4 | * |
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5 | * Based on 24x.h for the Samsung Development Board |
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6 | ************************************************/ |
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7 | |
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8 | #ifndef S3C2400_H_ |
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9 | #define S3C2400_H_ |
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10 | |
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11 | /* Memory control */ |
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12 | #define rBWSCON (*(volatile unsigned *)0x14000000) |
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13 | #define rBANKCON0 (*(volatile unsigned *)0x14000004) |
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14 | #define rBANKCON1 (*(volatile unsigned *)0x14000008) |
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15 | #define rBANKCON2 (*(volatile unsigned *)0x1400000C) |
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16 | #define rBANKCON3 (*(volatile unsigned *)0x14000010) |
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17 | #define rBANKCON4 (*(volatile unsigned *)0x14000014) |
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18 | #define rBANKCON5 (*(volatile unsigned *)0x14000018) |
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19 | #define rBANKCON6 (*(volatile unsigned *)0x1400001C) |
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20 | #define rBANKCON7 (*(volatile unsigned *)0x14000020) |
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21 | #define rREFRESH (*(volatile unsigned *)0x14000024) |
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22 | #define rBANKSIZE (*(volatile unsigned *)0x14000028) |
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23 | #define rMRSRB6 (*(volatile unsigned *)0x1400002C) |
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24 | #define rMRSRB7 (*(volatile unsigned *)0x14000030) |
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25 | |
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26 | |
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27 | /* INTERRUPT */ |
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28 | #define rSRCPND (*(volatile unsigned *)0x14400000) |
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29 | #define rINTMOD (*(volatile unsigned *)0x14400004) |
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30 | #define rINTMSK (*(volatile unsigned *)0x14400008) |
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31 | #define rPRIORITY (*(volatile unsigned *)0x1440000C) |
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32 | #define rINTPND (*(volatile unsigned *)0x14400010) |
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33 | #define rINTOFFSET (*(volatile unsigned *)0x14400014) |
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34 | |
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35 | |
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36 | /* DMA */ |
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37 | #define rDISRC0 (*(volatile unsigned *)0x14600000) |
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38 | #define rDIDST0 (*(volatile unsigned *)0x14600004) |
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39 | #define rDCON0 (*(volatile unsigned *)0x14600008) |
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40 | #define rDSTAT0 (*(volatile unsigned *)0x1460000C) |
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41 | #define rDCSRC0 (*(volatile unsigned *)0x14600010) |
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42 | #define rDCDST0 (*(volatile unsigned *)0x14600014) |
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43 | #define rDMASKTRIG0 (*(volatile unsigned *)0x14600018) |
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44 | #define rDISRC1 (*(volatile unsigned *)0x14600020) |
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45 | #define rDIDST1 (*(volatile unsigned *)0x14600024) |
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46 | #define rDCON1 (*(volatile unsigned *)0x14600028) |
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47 | #define rDSTAT1 (*(volatile unsigned *)0x1460002C) |
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48 | #define rDCSRC1 (*(volatile unsigned *)0x14600030) |
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49 | #define rDCDST1 (*(volatile unsigned *)0x14600034) |
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50 | #define rDMASKTRIG1 (*(volatile unsigned *)0x14600038) |
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51 | #define rDISRC2 (*(volatile unsigned *)0x14600040) |
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52 | #define rDIDST2 (*(volatile unsigned *)0x14600044) |
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53 | #define rDCON2 (*(volatile unsigned *)0x14600048) |
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54 | #define rDSTAT2 (*(volatile unsigned *)0x1460004C) |
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55 | #define rDCSRC2 (*(volatile unsigned *)0x14600050) |
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56 | #define rDCDST2 (*(volatile unsigned *)0x14600054) |
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57 | #define rDMASKTRIG2 (*(volatile unsigned *)0x14600058) |
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58 | #define rDISRC3 (*(volatile unsigned *)0x14600060) |
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59 | #define rDIDST3 (*(volatile unsigned *)0x14600064) |
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60 | #define rDCON3 (*(volatile unsigned *)0x14600068) |
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61 | #define rDSTAT3 (*(volatile unsigned *)0x1460006C) |
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62 | #define rDCSRC3 (*(volatile unsigned *)0x14600070) |
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63 | #define rDCDST3 (*(volatile unsigned *)0x14600074) |
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64 | #define rDMASKTRIG3 (*(volatile unsigned *)0x14600078) |
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65 | |
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66 | |
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67 | /* CLOCK & POWER MANAGEMENT */ |
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68 | #define rLOCKTIME (*(volatile unsigned *)0x14800000) |
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69 | #define rMPLLCON (*(volatile unsigned *)0x14800004) |
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70 | #define rUPLLCON (*(volatile unsigned *)0x14800008) |
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71 | #define rCLKCON (*(volatile unsigned *)0x1480000C) |
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72 | #define rCLKSLOW (*(volatile unsigned *)0x14800010) |
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73 | #define rCLKDIVN (*(volatile unsigned *)0x14800014) |
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74 | |
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75 | |
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76 | /* LCD CONTROLLER */ |
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77 | #define rLCDCON1 (*(volatile unsigned *)0x14A00000) |
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78 | #define rLCDCON2 (*(volatile unsigned *)0x14A00004) |
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79 | #define rLCDCON3 (*(volatile unsigned *)0x14A00008) |
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80 | #define rLCDCON4 (*(volatile unsigned *)0x14A0000C) |
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81 | #define rLCDCON5 (*(volatile unsigned *)0x14A00010) |
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82 | #define rLCDSADDR1 (*(volatile unsigned *)0x14A00014) |
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83 | #define rLCDSADDR2 (*(volatile unsigned *)0x14A00018) |
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84 | #define rLCDSADDR3 (*(volatile unsigned *)0x14A0001C) |
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85 | #define rREDLUT (*(volatile unsigned *)0x14A00020) |
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86 | #define rGREENLUT (*(volatile unsigned *)0x14A00024) |
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87 | #define rBLUELUT (*(volatile unsigned *)0x14A00028) |
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88 | #define rDP1_2 (*(volatile unsigned *)0x14A0002C) |
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89 | #define rDP4_7 (*(volatile unsigned *)0x14A00030) |
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90 | #define rDP3_5 (*(volatile unsigned *)0x14A00034) |
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91 | #define rDP2_3 (*(volatile unsigned *)0x14A00038) |
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92 | #define rDP5_7 (*(volatile unsigned *)0x14A0003c) |
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93 | #define rDP3_4 (*(volatile unsigned *)0x14A00040) |
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94 | #define rDP4_5 (*(volatile unsigned *)0x14A00044) |
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95 | #define rDP6_7 (*(volatile unsigned *)0x14A00048) |
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96 | #define rDITHMODE (*(volatile unsigned *)0x14A0004C) |
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97 | #define rTPAL (*(volatile unsigned *)0x14A00050) |
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98 | #define GP32_PALETTE (*(volatile unsigned *)0x14A00400) /* SJS */ |
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99 | |
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100 | |
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101 | /* UART */ |
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102 | #define rULCON0 (*(volatile unsigned char *)0x15000000) |
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103 | #define rUCON0 (*(volatile unsigned short *)0x15000004) |
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104 | #define rUFCON0 (*(volatile unsigned char *)0x15000008) |
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105 | #define rUMCON0 (*(volatile unsigned char *)0x1500000C) |
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106 | #define rUTRSTAT0 (*(volatile unsigned char *)0x15000010) |
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107 | #define rUERSTAT0 (*(volatile unsigned char *)0x15000014) |
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108 | #define rUFSTAT0 (*(volatile unsigned short *)0x15000018) |
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109 | #define rUMSTAT0 (*(volatile unsigned char *)0x1500001C) |
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110 | #define rUBRDIV0 (*(volatile unsigned short *)0x15000028) |
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111 | |
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112 | #define rULCON1 (*(volatile unsigned char *)0x15004000) |
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113 | #define rUCON1 (*(volatile unsigned short *)0x15004004) |
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114 | #define rUFCON1 (*(volatile unsigned char *)0x15004008) |
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115 | #define rUMCON1 (*(volatile unsigned char *)0x1500400C) |
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116 | #define rUTRSTAT1 (*(volatile unsigned char *)0x15004010) |
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117 | #define rUERSTAT1 (*(volatile unsigned char *)0x15004014) |
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118 | #define rUFSTAT1 (*(volatile unsigned short *)0x15004018) |
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119 | #define rUMSTAT1 (*(volatile unsigned char *)0x1500401C) |
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120 | #define rUBRDIV1 (*(volatile unsigned short *)0x15004028) |
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121 | |
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122 | #ifdef __BIG_ENDIAN |
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123 | #define rUTXH0 (*(volatile unsigned char *)0x15000023) |
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124 | #define rURXH0 (*(volatile unsigned char *)0x15000027) |
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125 | #define rUTXH1 (*(volatile unsigned char *)0x15004023) |
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126 | #define rURXH1 (*(volatile unsigned char *)0x15004027) |
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127 | |
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128 | #define WrUTXH0(ch) (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch) |
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129 | #define RdURXH0() (*(volatile unsigned char *)0x15000027) |
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130 | #define WrUTXH1(ch) (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch) |
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131 | #define RdURXH1() (*(volatile unsigned char *)0x15004027) |
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132 | |
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133 | #define UTXH0 (0x15000020+3) /* byte_access address by DMA */ |
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134 | #define URXH0 (0x15000024+3) |
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135 | #define UTXH1 (0x15004020+3) |
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136 | #define URXH1 (0x15004024+3) |
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137 | |
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138 | #else /* Little Endian */ |
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139 | #define rUTXH0 (*(volatile unsigned char *)0x15000020) |
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140 | #define rURXH0 (*(volatile unsigned char *)0x15000024) |
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141 | #define rUTXH1 (*(volatile unsigned char *)0x15004020) |
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142 | #define rURXH1 (*(volatile unsigned char *)0x15004024) |
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143 | |
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144 | #define WrUTXH0(ch) (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch) |
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145 | #define RdURXH0() (*(volatile unsigned char *)0x15000024) |
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146 | #define WrUTXH1(ch) (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch) |
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147 | #define RdURXH1() (*(volatile unsigned char *)0x15004024) |
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148 | |
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149 | #define UTXH0 (0x15000020) /* byte_access address by DMA */ |
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150 | #define URXH0 (0x15000024) |
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151 | #define UTXH1 (0x15004020) |
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152 | #define URXH1 (0x15004024) |
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153 | #endif |
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154 | |
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155 | |
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156 | /* PWM TIMER */ |
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157 | #define rTCFG0 (*(volatile unsigned *)0x15100000) |
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158 | #define rTCFG1 (*(volatile unsigned *)0x15100004) |
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159 | #define rTCON (*(volatile unsigned *)0x15100008) |
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160 | #define rTCNTB0 (*(volatile unsigned *)0x1510000C) |
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161 | #define rTCMPB0 (*(volatile unsigned *)0x15100010) |
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162 | #define rTCNTO0 (*(volatile unsigned *)0x15100014) |
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163 | #define rTCNTB1 (*(volatile unsigned *)0x15100018) |
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164 | #define rTCMPB1 (*(volatile unsigned *)0x1510001C) |
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165 | #define rTCNTO1 (*(volatile unsigned *)0x15100020) |
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166 | #define rTCNTB2 (*(volatile unsigned *)0x15100024) |
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167 | #define rTCMPB2 (*(volatile unsigned *)0x15100028) |
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168 | #define rTCNTO2 (*(volatile unsigned *)0x1510002C) |
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169 | #define rTCNTB3 (*(volatile unsigned *)0x15100030) |
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170 | #define rTCMPB3 (*(volatile unsigned *)0x15100034) |
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171 | #define rTCNTO3 (*(volatile unsigned *)0x15100038) |
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172 | #define rTCNTB4 (*(volatile unsigned *)0x1510003C) |
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173 | #define rTCNTO4 (*(volatile unsigned *)0x15100040) |
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174 | |
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175 | |
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176 | /* USB DEVICE */ |
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177 | #define rFUNC_ADDR_REG (*(volatile unsigned *)0x15200140) |
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178 | #define rPWR_REG (*(volatile unsigned *)0x15200144) |
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179 | #define rINT_REG (*(volatile unsigned *)0x15200148) |
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180 | #define rINT_MASK_REG (*(volatile unsigned *)0x1520014C) |
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181 | #define rFRAME_NUM_REG (*(volatile unsigned *)0x15200150) |
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182 | #define rRESUME_CON_REG (*(volatile unsigned *)0x15200154) |
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183 | #define rEP0_CSR (*(volatile unsigned *)0x15200160) |
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184 | #define rEP0_MAXP (*(volatile unsigned *)0x15200164) |
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185 | #define rEP0_OUT_CNT (*(volatile unsigned *)0x15200168) |
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186 | #define rEP0_FIFO (*(volatile unsigned *)0x1520016C) |
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187 | #define rEP1_IN_CSR (*(volatile unsigned *)0x15200180) |
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188 | #define rEP1_IN_MAXP (*(volatile unsigned *)0x15200184) |
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189 | #define rEP1_FIFO (*(volatile unsigned *)0x15200188) |
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190 | #define rEP2_IN_CSR (*(volatile unsigned *)0x15200190) |
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191 | #define rEP2_IN_MAXP (*(volatile unsigned *)0x15200194) |
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192 | #define rEP2_FIFO (*(volatile unsigned *)0x15200198) |
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193 | #define rEP3_OUT_CSR (*(volatile unsigned *)0x152001A0) |
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194 | #define rEP3_OUT_MAXP (*(volatile unsigned *)0x152001A4) |
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195 | #define rEP3_OUT_CNT (*(volatile unsigned *)0x152001A8) |
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196 | #define rEP3_FIFO (*(volatile unsigned *)0x152001AC) |
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197 | #define rEP4_OUT_CSR (*(volatile unsigned *)0x152001B0) |
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198 | #define rEP4_OUT_MAXP (*(volatile unsigned *)0x152001B4) |
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199 | #define rEP4_OUT_CNT (*(volatile unsigned *)0x152001B8) |
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200 | #define rEP4_FIFO (*(volatile unsigned *)0x152001BC) |
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201 | #define rDMA_CON (*(volatile unsigned *)0x152001C0) |
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202 | #define rDMA_UNIT (*(volatile unsigned *)0x152001C4) |
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203 | #define rDMA_FIFO (*(volatile unsigned *)0x152001C8) |
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204 | #define rDMA_TX (*(volatile unsigned *)0x152001CC) |
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205 | #define rTEST_MODE (*(volatile unsigned *)0x152001F4) |
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206 | #define rIN_CON_REG (*(volatile unsigned *)0x152001F8) |
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207 | |
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208 | |
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209 | /* WATCH DOG TIMER */ |
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210 | #define rWTCON (*(volatile unsigned *)0x15300000) |
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211 | #define rWTDAT (*(volatile unsigned *)0x15300004) |
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212 | #define rWTCNT (*(volatile unsigned *)0x15300008) |
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213 | |
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214 | |
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215 | /* IIC */ |
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216 | #define rIICCON (*(volatile unsigned *)0x15400000) |
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217 | #define rIICSTAT (*(volatile unsigned *)0x15400004) |
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218 | #define rIICADD (*(volatile unsigned *)0x15400008) |
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219 | #define rIICDS (*(volatile unsigned *)0x1540000C) |
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220 | |
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221 | |
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222 | /* IIS */ |
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223 | #define rIISCON (*(volatile unsigned *)0x15508000) |
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224 | #define rIISMOD (*(volatile unsigned *)0x15508004) |
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225 | #define rIISPSR (*(volatile unsigned *)0x15508008) |
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226 | #define rIISFIFCON (*(volatile unsigned *)0x1550800C) |
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227 | |
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228 | #ifdef __BIG_ENDIAN |
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229 | #define IISFIF ((volatile unsigned short *)0x15508012) |
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230 | |
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231 | #else /* Little Endian */ |
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232 | #define IISFIF ((volatile unsigned short *)0x15508010) |
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233 | #endif |
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234 | |
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235 | |
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236 | /* I/O PORT */ |
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237 | #define rPACON (*(volatile unsigned *)0x15600000) |
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238 | #define rPADAT (*(volatile unsigned *)0x15600004) |
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239 | |
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240 | #define rPBCON (*(volatile unsigned *)0x15600008) |
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241 | #define rPBDAT (*(volatile unsigned *)0x1560000C) |
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242 | #define rPBUP (*(volatile unsigned *)0x15600010) |
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243 | |
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244 | #define rPCCON (*(volatile unsigned *)0x15600014) |
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245 | #define rPCDAT (*(volatile unsigned *)0x15600018) |
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246 | #define rPCUP (*(volatile unsigned *)0x1560001C) |
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247 | |
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248 | #define rPDCON (*(volatile unsigned *)0x15600020) |
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249 | #define rPDDAT (*(volatile unsigned *)0x15600024) |
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250 | #define rPDUP (*(volatile unsigned *)0x15600028) |
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251 | |
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252 | #define rPECON (*(volatile unsigned *)0x1560002C) |
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253 | #define rPEDAT (*(volatile unsigned *)0x15600030) |
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254 | #define rPEUP (*(volatile unsigned *)0x15600034) |
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255 | |
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256 | #define rPFCON (*(volatile unsigned *)0x15600038) |
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257 | #define rPFDAT (*(volatile unsigned *)0x1560003C) |
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258 | #define rPFUP (*(volatile unsigned *)0x15600040) |
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259 | |
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260 | #define rPGCON (*(volatile unsigned *)0x15600044) |
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261 | #define rPGDAT (*(volatile unsigned *)0x15600048) |
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262 | #define rPGUP (*(volatile unsigned *)0x1560004C) |
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263 | |
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264 | #define rOPENCR (*(volatile unsigned *)0x15600050) |
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265 | #define rMISCCR (*(volatile unsigned *)0x15600054) |
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266 | #define rEXTINT (*(volatile unsigned *)0x15600058) |
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267 | |
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268 | |
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269 | /* RTC */ |
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270 | #ifdef __BIG_ENDIAN |
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271 | #define rRTCCON (*(volatile unsigned char *)0x15700043) |
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272 | #define rRTCALM (*(volatile unsigned char *)0x15700053) |
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273 | #define rALMSEC (*(volatile unsigned char *)0x15700057) |
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274 | #define rALMMIN (*(volatile unsigned char *)0x1570005B) |
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275 | #define rALMHOUR (*(volatile unsigned char *)0x1570005F) |
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276 | #define rALMDAY (*(volatile unsigned char *)0x15700063) |
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277 | #define rALMMON (*(volatile unsigned char *)0x15700067) |
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278 | #define rALMYEAR (*(volatile unsigned char *)0x1570006B) |
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279 | #define rRTCRST (*(volatile unsigned char *)0x1570006F) |
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280 | #define rBCDSEC (*(volatile unsigned char *)0x15700073) |
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281 | #define rBCDMIN (*(volatile unsigned char *)0x15700077) |
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282 | #define rBCDHOUR (*(volatile unsigned char *)0x1570007B) |
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283 | #define rBCDDAY (*(volatile unsigned char *)0x1570007F) |
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284 | #define rBCDDATE (*(volatile unsigned char *)0x15700083) |
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285 | #define rBCDMON (*(volatile unsigned char *)0x15700087) |
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286 | #define rBCDYEAR (*(volatile unsigned char *)0x1570008B) |
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287 | #define rTICINT (*(volatile unsigned char *)0x15700047) |
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288 | |
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289 | #else /* Little Endian */ |
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290 | #define rRTCCON (*(volatile unsigned char *)0x15700040) |
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291 | #define rRTCALM (*(volatile unsigned char *)0x15700050) |
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292 | #define rALMSEC (*(volatile unsigned char *)0x15700054) |
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293 | #define rALMMIN (*(volatile unsigned char *)0x15700058) |
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294 | #define rALMHOUR (*(volatile unsigned char *)0x1570005C) |
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295 | #define rALMDAY (*(volatile unsigned char *)0x15700060) |
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296 | #define rALMMON (*(volatile unsigned char *)0x15700064) |
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297 | #define rALMYEAR (*(volatile unsigned char *)0x15700068) |
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298 | #define rRTCRST (*(volatile unsigned char *)0x1570006C) |
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299 | #define rBCDSEC (*(volatile unsigned char *)0x15700070) |
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300 | #define rBCDMIN (*(volatile unsigned char *)0x15700074) |
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301 | #define rBCDHOUR (*(volatile unsigned char *)0x15700078) |
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302 | #define rBCDDAY (*(volatile unsigned char *)0x1570007C) |
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303 | #define rBCDDATE (*(volatile unsigned char *)0x15700080) |
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304 | #define rBCDMON (*(volatile unsigned char *)0x15700084) |
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305 | #define rBCDYEAR (*(volatile unsigned char *)0x15700088) |
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306 | #define rTICINT (*(volatile unsigned char *)0x15700044) |
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307 | #endif |
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308 | |
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309 | |
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310 | /* ADC */ |
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311 | #define rADCCON (*(volatile unsigned *)0x15800000) |
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312 | #define rADCDAT (*(volatile unsigned *)0x15800004) |
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313 | |
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314 | |
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315 | /* SPI */ |
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316 | #define rSPCON (*(volatile unsigned *)0x15900000) |
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317 | #define rSPSTA (*(volatile unsigned *)0x15900004) |
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318 | #define rSPPIN (*(volatile unsigned *)0x15900008) |
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319 | #define rSPPRE (*(volatile unsigned *)0x1590000C) |
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320 | #define rSPTDAT (*(volatile unsigned *)0x15900010) |
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321 | #define rSPRDAT (*(volatile unsigned *)0x15900014) |
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322 | |
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323 | |
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324 | /* MMC INTERFACE */ |
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325 | #define rMMCON (*(volatile unsigned *)0x15a00000) |
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326 | #define rMMCRR (*(volatile unsigned *)0x15a00004) |
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327 | #define rMMFCON (*(volatile unsigned *)0x15a00008) |
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328 | #define rMMSTA (*(volatile unsigned *)0x15a0000C) |
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329 | #define rMMFSTA (*(volatile unsigned *)0x15a00010) |
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330 | #define rMMPRE (*(volatile unsigned *)0x15a00014) |
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331 | #define rMMLEN (*(volatile unsigned *)0x15a00018) |
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332 | #define rMMCR7 (*(volatile unsigned *)0x15a0001C) |
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333 | #define rMMRSP0 (*(volatile unsigned *)0x15a00020) |
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334 | #define rMMRSP1 (*(volatile unsigned *)0x15a00024) |
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335 | #define rMMRSP2 (*(volatile unsigned *)0x15a00028) |
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336 | #define rMMRSP3 (*(volatile unsigned *)0x15a0002C) |
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337 | #define rMMCMD0 (*(volatile unsigned *)0x15a00030) |
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338 | #define rMMCMD1 (*(volatile unsigned *)0x15a00034) |
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339 | #define rMMCR16 (*(volatile unsigned *)0x15a00038) |
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340 | #define rMMDAT (*(volatile unsigned *)0x15a0003C) |
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341 | |
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342 | |
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343 | #define _ISR_STARTADDRESS rtems_vector_table |
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344 | /* ISR */ |
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345 | #define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) |
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346 | #define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) |
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347 | #define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) |
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348 | #define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC)) |
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349 | #define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) |
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350 | #define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) |
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351 | #define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) |
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352 | #define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C)) |
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353 | |
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354 | #define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) |
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355 | #define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) |
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356 | #define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28)) |
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357 | #define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C)) |
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358 | #define pISR_EINT4 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) |
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359 | #define pISR_EINT5 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) |
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360 | #define pISR_EINT6 (*(unsigned *)(_ISR_STARTADDRESS+0x38)) |
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361 | #define pISR_EINT7 (*(unsigned *)(_ISR_STARTADDRESS+0x3C)) |
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362 | #define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) |
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363 | #define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44)) |
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364 | #define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) |
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365 | #define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C)) |
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366 | #define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) |
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367 | #define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) |
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368 | #define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) |
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369 | #define pISR_UERR01 (*(unsigned *)(_ISR_STARTADDRESS+0x5C)) |
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370 | #define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60)) |
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371 | #define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) |
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372 | #define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) |
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373 | #define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C)) |
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374 | #define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) |
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375 | #define pISR_MMC (*(unsigned *)(_ISR_STARTADDRESS+0x74)) |
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376 | #define pISR_SPI (*(unsigned *)(_ISR_STARTADDRESS+0x78)) |
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377 | #define pISR_URXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x7C)) |
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378 | #define pISR_URXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x80)) |
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379 | #define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84)) |
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380 | #define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88)) |
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381 | #define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C)) |
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382 | #define pISR_UTXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x90)) |
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383 | #define pISR_UTXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x94)) |
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384 | #define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98)) |
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385 | #define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0)) |
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386 | |
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387 | |
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388 | /* PENDING BIT */ |
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389 | #define BIT_EINT0 (0x1) |
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390 | #define BIT_EINT1 (0x1<<1) |
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391 | #define BIT_EINT2 (0x1<<2) |
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392 | #define BIT_EINT3 (0x1<<3) |
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393 | #define BIT_EINT4 (0x1<<4) |
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394 | #define BIT_EINT5 (0x1<<5) |
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395 | #define BIT_EINT6 (0x1<<6) |
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396 | #define BIT_EINT7 (0x1<<7) |
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397 | #define BIT_TICK (0x1<<8) |
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398 | #define BIT_WDT (0x1<<9) |
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399 | #define BIT_TIMER0 (0x1<<10) |
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400 | #define BIT_TIMER1 (0x1<<11) |
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401 | #define BIT_TIMER2 (0x1<<12) |
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402 | #define BIT_TIMER3 (0x1<<13) |
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403 | #define BIT_TIMER4 (0x1<<14) |
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404 | #define BIT_UERR01 (0x1<<15) |
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405 | #define BIT_NOTUSED (0x1<<16) |
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406 | #define BIT_DMA0 (0x1<<17) |
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407 | #define BIT_DMA1 (0x1<<18) |
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408 | #define BIT_DMA2 (0x1<<19) |
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409 | #define BIT_DMA3 (0x1<<20) |
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410 | #define BIT_MMC (0x1<<21) |
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411 | #define BIT_SPI (0x1<<22) |
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412 | #define BIT_URXD0 (0x1<<23) |
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413 | #define BIT_URXD1 (0x1<<24) |
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414 | #define BIT_USBD (0x1<<25) |
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415 | #define BIT_USBH (0x1<<26) |
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416 | #define BIT_IIC (0x1<<27) |
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417 | #define BIT_UTXD0 (0x1<<28) |
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418 | #define BIT_UTXD1 (0x1<<29) |
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419 | #define BIT_RTC (0x1<<30) |
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420 | #define BIT_ADC (0x1<<31) |
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421 | #define BIT_ALLMSK (0xFFFFFFFF) |
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422 | |
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423 | #define ClearPending(bit) {\ |
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424 | rSRCPND = bit;\ |
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425 | rINTPND = bit;\ |
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426 | rINTPND;\ |
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427 | } |
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428 | /* Wait until rINTPND is changed for the case that the ISR is very short. */ |
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429 | |
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430 | /* Typedefs */ |
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431 | typedef union { |
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432 | struct _reg { |
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433 | unsigned STOP_BIT:1; /* Enters STOP mode. This bit isn't be */ |
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434 | /* cleared automatically. */ |
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435 | unsigned SL_IDLE:1; /* SL_IDLE mode option. This bit isn't cleared */ |
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436 | /* automatically. To enter SL_IDLE mode, */ |
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437 | /* CLKCON register has to be 0xe. */ |
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438 | unsigned IDLE_BIT:1; /* Enters IDLE mode. This bit isn't be cleared */ |
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439 | /* automatically. */ |
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440 | unsigned LCDC:1; /* Controls HCLK into LCDC block */ |
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441 | unsigned USB_host:1; /* Controls HCLK into USB host block */ |
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442 | unsigned USB_device:1; /* Controls PCLK into USB device block */ |
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443 | unsigned PWMTIMER:1; /* Controls PCLK into PWMTIMER block */ |
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444 | unsigned MMC:1; /* Controls PCLK into MMC interface block */ |
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445 | unsigned UART0:1; /* Controls PCLK into UART0 block */ |
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446 | unsigned UART1:1; /* Controls PCLK into UART1 block */ |
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447 | unsigned GPIO:1; /* Controls PCLK into GPIO block */ |
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448 | unsigned RTC:1; /* Controls PCLK into RTC control block. Even if */ |
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449 | /* this bit is cleared to 0, RTC timer is alive. */ |
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450 | unsigned ADC:1; /* Controls PCLK into ADC block */ |
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451 | unsigned IIC:1; /* Controls PCLK into IIC block */ |
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452 | unsigned IIS:1; /* Controls PCLK into IIS block */ |
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453 | unsigned SPI:1; /* Controls PCLK into SPI block */ |
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454 | } reg; |
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455 | unsigned long all; |
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456 | } CLKCON; |
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457 | |
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458 | typedef union |
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459 | { |
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460 | struct { |
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461 | unsigned ENVID:1; /* LCD video output and the logic 1=enable/0=disable. */ |
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462 | unsigned BPPMODE:4; /* 1011 = 8 bpp for TFT, 1100 = 16 bpp for TFT, */ |
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463 | /* 1110 = 16 bpp TFT skipmode */ |
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464 | unsigned PNRMODE:2; /* TFT: 3 */ |
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465 | unsigned MMODE:1; /* This bit determines the toggle rate of the VM. */ |
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466 | /* 0 = Each Frame, 1 = The rate defined by the MVAL */ |
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467 | unsigned CLKVAL:10; /* TFT: VCLK = HCLK / [(CLKVAL+1) x 2] (CLKVAL >= 1) */ |
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468 | unsigned LINECNT:10; /* (read only) These bits provide the status of the */ |
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469 | /* line counter. Down count from LINEVAL to 0 */ |
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470 | } reg; |
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471 | unsigned long all; |
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472 | } LCDCON1; |
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473 | |
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474 | typedef union { |
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475 | struct { |
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476 | unsigned VSPW:6; /* TFT: Vertical sync pulse width determines the */ |
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477 | /* VSYNC pulse's high level width by counting the */ |
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478 | /* number of inactive lines. */ |
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479 | unsigned VFPD:8; /* TFT: Vertical front porch is the number of */ |
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480 | /* inactive lines at the end of a frame, before */ |
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481 | /* vertical synchronization period. */ |
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482 | unsigned LINEVAL:10; /* TFT/STN: These bits determine the vertical size */ |
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483 | /* of LCD panel. */ |
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484 | unsigned VBPD:8; /* TFT: Vertical back porch is the number of inactive */ |
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485 | /* lines at the start of a frame, after */ |
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486 | /* vertical synchronization period. */ |
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487 | } reg; |
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488 | unsigned long all; |
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489 | } LCDCON2; |
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490 | |
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491 | typedef union { |
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492 | struct { |
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493 | unsigned HFPD:8; /* TFT: Horizontal front porch is the number of */ |
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494 | /* VCLK periods between the end of active data */ |
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495 | /* and the rising edge of HSYNC. */ |
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496 | unsigned HOZVAL:11; /* TFT/STN: These bits determine the horizontal */ |
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497 | /* size of LCD panel. 2n bytes. */ |
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498 | unsigned HBPD:7; /* TFT: Horizontal back porch is the number of VCLK */ |
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499 | /* periods between the falling edge of HSYNC and */ |
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500 | /* the start of active data. */ |
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501 | } reg; |
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502 | unsigned long all; |
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503 | } LCDCON3; |
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504 | |
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505 | typedef union { |
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506 | struct { |
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507 | unsigned HSPW:8; /* TFT: Horizontal sync pulse width determines the */ |
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508 | /* HSYNC pulse's high level width by counting the */ |
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509 | /* number of the VCLK. */ |
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510 | unsigned MVAL:8; /* STN: */ |
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511 | unsigned ADDVAL:8; /* TFT: Palette Index offset value */ |
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512 | unsigned PALADDEN:1; /* TFT: Palette Index offset enable. */ |
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513 | /* 0 = Disable 1 = Enable */ |
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514 | } reg; |
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515 | unsigned long all; |
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516 | } LCDCON4; |
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517 | |
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518 | typedef union { |
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519 | struct { |
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520 | unsigned HWSWP:1; /* STN/TFT: Half-Word swap control bit. */ |
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521 | /* 0 = Swap Disable 1 = Swap Enable */ |
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522 | unsigned BSWP:1; /* STN/TFT: Byte swap control bit. */ |
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523 | /* 0 = Swap Disable 1 = Swap Enable */ |
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524 | unsigned ENLEND:1; /* TFT: LEND output signal enable/disable. */ |
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525 | /* 0 = Disable LEND signal. */ |
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526 | /* 1 = Enable LEND signal */ |
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527 | unsigned RESERVED1:1; |
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528 | unsigned INVENDLINE:1;/* TFT: This bit indicates the LEND signal */ |
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529 | /* polarity. 0 = normal 1 = inverted */ |
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530 | unsigned RESERVED2:1; |
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531 | unsigned INVVDEN:1; /* TFT: This bit indicates the VDEN signal */ |
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532 | /* polarity. */ |
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533 | /* 0 = normal 1 = inverted */ |
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534 | unsigned INVVD:1; /* STN/TFT: This bit indicates the VD (video data) */ |
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535 | /* pulse polarity. 0 = Normal. */ |
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536 | /* 1 = VD is inverted. */ |
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537 | unsigned INVVFRAME:1; /* STN/TFT: This bit indicates the VFRAME/VSYNC */ |
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538 | /* pulse polarity. 0 = normal 1 = inverted */ |
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539 | unsigned INVVLINE:1; /* STN/TFT: This bit indicates the VLINE/HSYNC */ |
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540 | /* pulse polarity. 0 = normal 1 = inverted */ |
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541 | unsigned INVVCLK:1; /* STN/TFT: This bit controls the polarity of the */ |
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542 | /* VCLK active edge. 0 = The video data is */ |
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543 | /* fetched at VCLK falling edge. 1 = The video */ |
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544 | /* data is fetched at VCLK rising edge */ |
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545 | unsigned RESERVED3:2; |
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546 | unsigned SELFREF:1; /* STN: */ |
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547 | unsigned SLOWCLKSYNC:1; /* STN: */ |
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548 | unsigned RESERVED4:2; /* must be 0 */ |
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549 | unsigned HSTATUS:2; /* TFT: Horizontal Status (Read only) */ |
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550 | /* 00 = HSYNC */ |
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551 | /* 01 = BACK Porch. */ |
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552 | /* 10 = ACTIVE */ |
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553 | /* 11 = FRONT Porch */ |
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554 | unsigned VSTATUS:2; /* TFT: Vertical Status (Read only). */ |
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555 | /* 00 = VSYNC */ |
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556 | /* 01 = BACK Porch. */ |
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557 | /* 10 = ACTIVE */ |
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558 | /* 11 = FRONT Porch */ |
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559 | } reg; |
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560 | unsigned long all; |
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561 | } LCDCON5; |
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562 | |
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563 | typedef union { |
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564 | struct { |
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565 | unsigned LCDBASEU:21; /* For single-scan LCD: These bits indicate */ |
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566 | /* A[21:1] of the start address of the LCD */ |
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567 | /* frame buffer. */ |
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568 | unsigned LCDBANK:7; /* A[28:22] */ |
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569 | } reg; |
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570 | unsigned long all; |
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571 | } LCDSADDR1; |
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572 | |
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573 | typedef union { |
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574 | struct { |
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575 | unsigned LCDBASEL:21; /* For single scan LCD: These bits indicate A[21:1]*/ |
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576 | /* of the end address of the LCD frame buffer. */ |
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577 | /* LCDBASEL = ((the fame end address) >>1) + 1 */ |
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578 | /* = LCDBASEU + (PAGEWIDTH+OFFSIZE)x(LINEVAL+1) */ |
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579 | } reg; |
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580 | unsigned long all; |
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581 | } LCDSADDR2; |
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582 | |
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583 | typedef union { |
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584 | struct { |
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585 | unsigned PAGEWIDTH:11; /* Virtual screen page width(the number of half */ |
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586 | /* words) This value defines the width of the */ |
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587 | /* view port in the frame */ |
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588 | unsigned OFFSIZE:11; /* Virtual screen offset size(the number of half */ |
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589 | /* words) This value defines the difference */ |
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590 | /* between the address of the last half word */ |
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591 | /* displayed on the previous LCD line and the */ |
---|
592 | /* address of the first half word to be */ |
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593 | /* displayed in the new LCD line. */ |
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594 | } reg; |
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595 | unsigned long all; |
---|
596 | } LCDSADDR3; |
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597 | |
---|
598 | /* |
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599 | * |
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600 | */ |
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601 | |
---|
602 | typedef union { |
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603 | struct { |
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604 | unsigned IISIFENA:1; /* IIS interface enable (start) */ |
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605 | unsigned IISPSENA:1; /* IIS prescaler enable */ |
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606 | unsigned RXCHIDLE:1; /* Receive channel idle command */ |
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607 | unsigned TXCHIDLE:1; /* Transmit channel idle command */ |
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608 | unsigned RXDMAENA:1; /* Receive DMA service request enable */ |
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609 | unsigned TXDMAENA:1; /* Transmit DMA service request enable */ |
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610 | unsigned RXFIFORDY:1; /* Receive FIFO ready flag (read only) */ |
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611 | unsigned TXFIFORDY:1; /* Transmit FIFO ready flag (read only) */ |
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612 | unsigned LRINDEX:1; /* Left/right channel index (read only) */ |
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613 | } reg; |
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614 | unsigned long all; |
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615 | } IISCON; |
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616 | |
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617 | typedef union { |
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618 | struct { |
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619 | unsigned SBCLKFS:2; /* Serial bit clock frequency select */ |
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620 | unsigned MCLKFS:1; /* Master clock frequency select */ |
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621 | unsigned SDBITS:1; /* Serial data bit per channel */ |
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622 | unsigned SIFMT:1; /* Serial interface format */ |
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623 | unsigned ACTLEVCH:1; /* Active level pf left/right channel */ |
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624 | unsigned TXRXMODE:2; /* Transmit/receive mode select */ |
---|
625 | unsigned MODE:1; /* Master/slave mode select */ |
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626 | } reg; |
---|
627 | unsigned long all; |
---|
628 | } IISMOD; |
---|
629 | |
---|
630 | typedef union { |
---|
631 | struct { |
---|
632 | unsigned PSB:5; /* Prescaler control B */ |
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633 | unsigned PSA:5; /* Prescaler control A */ |
---|
634 | } reg; |
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635 | unsigned long all; |
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636 | } IISPSR; |
---|
637 | |
---|
638 | typedef union { |
---|
639 | struct { |
---|
640 | unsigned RXFIFOCNT:4; /* (read only) */ |
---|
641 | unsigned TXFIFOCNT:4; /* (read only) */ |
---|
642 | /*signed RXFIFOENA:1; /* */ |
---|
643 | unsigned TXFIFOENA:1; /* */ |
---|
644 | unsigned RXFIFOMODE:1; /* */ |
---|
645 | unsigned TXFIFOMODE:1; /* */ |
---|
646 | } reg; |
---|
647 | unsigned long all; |
---|
648 | } IISSFIFCON; |
---|
649 | |
---|
650 | typedef union { |
---|
651 | struct { |
---|
652 | unsigned FENTRY:16; /* */ |
---|
653 | } reg; |
---|
654 | unsigned long all; |
---|
655 | } IISSFIF; |
---|
656 | |
---|
657 | |
---|
658 | #define LCD_WIDTH 240 |
---|
659 | #define LCD_HEIGHT 320 |
---|
660 | #define LCD_ASPECT ((float)(LCD_WIDTH/LCD_HEIGHT)) |
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661 | |
---|
662 | #define GP32_KEY_SELECT 512 |
---|
663 | #define GP32_KEY_START 256 |
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664 | #define GP32_KEY_A 64 |
---|
665 | #define GP32_KEY_B 32 |
---|
666 | #define GP32_KEY_L 16 |
---|
667 | #define GP32_KEY_R 128 |
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668 | #define GP32_KEY_UP 8 |
---|
669 | #define GP32_KEY_DOWN 2 |
---|
670 | #define GP32_KEY_LEFT 1 |
---|
671 | #define GP32_KEY_RIGHT 4 |
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672 | |
---|
673 | #endif /*S3C2400_H_*/ |
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