source: rtems/c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_asm.S @ 1cfcfd3

4.104.114.84.95
Last change on this file since 1cfcfd3 was 1cfcfd3, checked in by Jay Monkman <jtm@…>, on Jul 15, 2004 at 6:25:44 AM

2004-07-15 Jay Monkman

  • ChangeLog?, Makefile.am, clock/.cvsignore, clock/clockdrv.c, include/mc9328mxl.h, irq/.cvsignore, irq/bsp_irq_asm.S, irq/bsp_irq_init.c, irq/irq.c, irq/irq.h, timer/.cvsignore, timer/timer.c: New files.
  • Property mode set to 100644
File size: 1.1 KB
Line 
1/*
2 * MC9328MXL Intererrupt handler
3 *
4 * Copyright (c) 2002 by Jay Monkman <jtm@lopingdog.com>
5 *
6 *  The license and distribution terms for this file may be
7 *  found in the file LICENSE in this distribution or at
8 *
9 *  http://www.OARcorp.com/rtems/license.html.
10 *
11 *
12 *  bsp_irq_asm.S,v 1.1 2002/11/13 17:55:06 joel Exp
13 */
14#define __asm__
15       
16/*
17 * BSP specific interrupt handler for INT or FIQ. In here
18 * you do determine which interrupt happened and call its
19 * handler.
20 */
21        .globl ExecuteITHandler
22ExecuteITHandler :
23/*
24 * Look at interrupt status register to determine source.
25 * From source, determine offset into expanded vector table
26 * and load handler address into r0.
27 */
28  ldr   r0, =0x00223040  /* Read the vector number */
29  ldr   r1, [r0]
30  mov   r1, r1, LSR #16         /* get the NIVECTOR into 16 LSbits */
31
32  /* find the ISR's address based on the vector */     
33  ldr   r0, =bsp_vector_table
34  ldr   r0, [r0, r1, LSL #2]    /* Read the address */
35
36
37  stmdb   sp!,{lr}
38  ldr     lr, =IRQ_return         /* prepare the return from handler  */
39
40  mov     pc, r0                /* EXECUTE INT HANDLER */
41
42IRQ_return:
43  ldmia sp!,{lr}
44
45  mov pc, lr
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