[1cfcfd3] | 1 | /* |
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| 2 | * MC9328MXL Intererrupt handler |
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| 3 | * |
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| 4 | * Copyright (c) 2002 by Jay Monkman <jtm@lopingdog.com> |
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| 5 | * |
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| 6 | * The license and distribution terms for this file may be |
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| 7 | * found in the file LICENSE in this distribution or at |
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| 8 | * |
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[93f4a906] | 9 | * http://www.rtems.com/license/LICENSE. |
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[1cfcfd3] | 10 | * |
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| 11 | * |
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| 12 | * bsp_irq_asm.S,v 1.1 2002/11/13 17:55:06 joel Exp |
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| 13 | */ |
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| 14 | #define __asm__ |
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| 15 | |
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| 16 | /* |
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| 17 | * BSP specific interrupt handler for INT or FIQ. In here |
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| 18 | * you do determine which interrupt happened and call its |
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| 19 | * handler. |
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| 20 | */ |
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| 21 | .globl ExecuteITHandler |
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| 22 | ExecuteITHandler : |
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| 23 | /* |
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| 24 | * Look at interrupt status register to determine source. |
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| 25 | * From source, determine offset into expanded vector table |
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| 26 | * and load handler address into r0. |
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| 27 | */ |
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| 28 | ldr r0, =0x00223040 /* Read the vector number */ |
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| 29 | ldr r1, [r0] |
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| 30 | mov r1, r1, LSR #16 /* get the NIVECTOR into 16 LSbits */ |
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| 31 | |
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| 32 | /* find the ISR's address based on the vector */ |
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| 33 | ldr r0, =bsp_vector_table |
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[7afe5a2] | 34 | mov r1, r1, LSL #3 /* Shift vector to get offset into table */ |
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| 35 | add r1, r0, r1 /* r1 has address of vector entry */ |
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| 36 | ldr r0, [r1, #4] /* Get the data pointer */ |
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| 37 | ldr r1, [r1] /* Get the vector */ |
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[1cfcfd3] | 38 | |
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| 39 | stmdb sp!,{lr} |
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| 40 | ldr lr, =IRQ_return /* prepare the return from handler */ |
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| 41 | |
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[7afe5a2] | 42 | mov pc, r1 /* EXECUTE INT HANDLER */ |
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[1cfcfd3] | 43 | |
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| 44 | IRQ_return: |
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| 45 | ldmia sp!,{lr} |
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| 46 | |
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| 47 | mov pc, lr |
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