source: rtems/c/src/lib/libcpu/arm/lpc22xx/irq/irq.c @ 0f31fddc

4.115
Last change on this file since 0f31fddc was 0f31fddc, checked in by Sebastian Huber <sebastian.huber@…>, on 03/24/12 at 21:01:08

bsps: Add shared default IRQ handler

  • Property mode set to 100644
File size: 1.5 KB
Line 
1/*
2 * Philps LPC22XX Interrupt handler
3 *
4 * Copyright (c) 2010 embedded brains GmbH.
5 *
6 * Copyright (c)  2006 by Ray<rayx.cn@gmail.com>  to support LPC ARM
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id$
13 */
14
15#include <bsp.h>
16#include <bsp/irq.h>
17#include <bsp/irq-generic.h>
18
19#include <lpc22xx.h>
20
21void bsp_interrupt_dispatch(void)
22{
23  rtems_vector_number vector = 31 - __builtin_clz(VICIRQStatus);
24
25  bsp_interrupt_handler_dispatch(vector);
26
27  VICVectAddr = 0;
28}
29
30rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
31{
32  VICIntEnable |= 1 << vector;
33
34  return RTEMS_SUCCESSFUL;
35}
36
37rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
38{
39  VICIntEnClr = 1 << vector;
40
41  return RTEMS_SUCCESSFUL;
42}
43
44rtems_status_code bsp_interrupt_facility_initialize(void)
45{
46  volatile uint32_t *ctrl = (volatile uint32_t *) VICVectCntlBase;
47  size_t i = 0;
48
49  /* Disable all interrupts */
50  VICIntEnClr = 0xffffffff;
51
52  /* Use IRQ category */
53  VICIntSelect = 0;
54
55  /* Enable access in USER mode */
56  VICProtection = 0;
57
58  for (i = 0; i < 16; ++i) {
59    /* Disable vector mode */
60    ctrl [i] = 0;
61
62    /* Acknowledge interrupts for all priorities */
63    VICVectAddr = 0;
64  }
65
66  /* Acknowledge interrupts for all priorities */
67  VICVectAddr = 0;
68
69  /* Install the IRQ exception handler */
70  _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
71
72  return RTEMS_SUCCESSFUL;
73}
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