source: rtems/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_usart.h @ c499856

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Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47

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1/*
2 * Atmel AT91RM9200_USART Register definitions, used in KIT637_V6 (CSB637)
3 *
4 * Copyright (c) 2003 by Cogent Computer Systems
5 * Written by Mike Kelly <mike@cogcomp.com>
6 *
7 * Modified by Fernando Nicodemos <fgnicodemos@terra.com.br>
8 * from NCB - Sistemas Embarcados Ltda. (Brazil)
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.org/license/LICENSE.
13*/
14
15#ifndef __AT91RM9200_USART_H__
16#define __AT91RM9200_USART_H__
17
18#include <bits.h>
19
20/* Register Offsets */
21#define US_CR         0x00            /* Control Register */
22#define US_MR         0x04            /* Mode Register */
23#define US_IER        0x08            /* Interrupt Enable Register */
24#define US_IDR        0x0C            /* Interrupt Disable Register */
25#define US_IMR        0x10            /* Interrupt Mask Register */
26#define US_SR         0x14            /* Channel Status Register */
27#define US_RHR        0x18            /* Receiver Holding Register */
28#define US_THR        0x1C            /* Transmitter Holding Register */
29#define US_BRGR       0x20            /* Baud Rate Generator Register */
30#define US_RTOR       0x24            /* Receiver Time-out Register */
31#define US_TTGR       0x28            /* Transmitter Timeguard Register */
32#define US_C1R        0x40            /* Chip ID1 Register - FI DI Ratio Register */
33#define US_C2R        0x44            /* Chip ID2 Register - Number of Erros Register */
34#define US_FNTR       0x48            /* Force NTRST Register */
35#define US_IF         0x4C            /* IrDA Filter Register  */
36
37/* Bit Defines */
38/* Control Register, US_CR, Offset 0x00 */
39#define US_CR_RSTRX    BIT2            /* 1 = Reset and disable receiver */
40#define US_CR_RSTTX    BIT3            /* 1 = Reset and disable transmitter */
41#define US_CR_RXEN     BIT4            /* 1 = Receiver enable */
42#define US_CR_RXDIS    BIT5            /* 1 = Receiver disable */
43#define US_CR_TXEN     BIT6            /* 1 = Transmitter enable */
44#define US_CR_TXDIS    BIT7            /* 1 = Transmitter disable */
45#define US_CR_RSTSTA   BIT8            /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */
46#define US_CR_STTBRK   BIT9            /* 1 = Start transmission of a Break */
47#define US_CR_STPBRK   BIT10           /* 1 = Stop transmission of a Break */
48#define US_CR_STTTO    BIT11           /* 1 = Start Time-out */
49#define US_CR_SENDA    BIT12           /* 1 = Send Address - MDROP mode only */
50#define US_CR_RSTIT    BIT13           /* 1 = Reset Iteration */
51#define US_CR_RSTNACK  BIT14           /* 1 = Reset Non Acknowledge */
52#define US_CR_RETTO    BIT15           /* 1 = Restart Time-out */
53#define US_CR_DTREN    BIT16           /* 1 = Data Terminal Ready Enable - AT91RM9200 only */
54#define US_CR_DTRDIS   BIT17           /* 1 = Data Terminal Ready Disable - AT91RM9200 only */
55#define US_CR_RTSEN    BIT18           /* 1 = Request To Send Enable */
56#define US_CR_RTSDIS   BIT19           /* 1 = Request To Send Disable */
57
58
59/* Mode Register. US_MR. Offset 0x04 */
60#define US_MR_USMODE            (0xF <<  0)             /* Mode of the USART */
61#define US_MR_USMODE_NORMAL             0
62#define US_MR_USMODE_RS485              1
63#define US_MR_USMODE_HWHS               2
64#define US_MR_USMODE_MODEM              3
65#define US_MR_USMODE_ISO7816_T0         4
66#define US_MR_USMODE_ISO7816_T1         6
67#define US_MR_USMODE_IRDA               8
68#define US_MR_USCLKS            (3 <<  4)               /* Clock Selection */
69#define US_MR_USCLKS_MCK        (0 <<  4)
70#define US_MR_USCLKS_MCK_DIV8   (1 <<  4)
71#define US_MR_USCLKS_SCK        (3 <<  4)
72#define US_MR_CHRL              (3 <<  6)               /* Character Length */
73#define US_MR_CHRL_5            (0 <<  6)
74#define US_MR_CHRL_6            (1 <<  6)
75#define US_MR_CHRL_7            (2 <<  6)
76#define US_MR_CHRL_8            (3 <<  6)
77#define US_MR_SYNC              (1 <<  8)               /* Synchronous Mode Select */
78#define US_MR_PAR               (7 <<  9)               /* Parity Type */
79#define US_MR_PAR_EVEN          (0 <<  9)               /* Even Parity */
80#define US_MR_PAR_ODD           (1 <<  9)               /* Odd Parity */
81#define US_MR_PAR_SPACE         (2 <<  9)               /* Parity forced to 0 (Space) */
82#define US_MR_PAR_MARK          (3 <<  9)               /* Parity forced to 1 (Mark) */
83#define US_MR_PAR_NONE          (4 <<  9)               /* No Parity */
84#define US_MR_PAR_MDROP         (6 <<  9)               /* Multi-drop mode */
85#define US_MR_NBSTOP            (3 << 12)               /* Number of Stop Bits */
86#define US_MR_NBSTOP_1          (0 << 12)
87#define US_MR_NBSTOP_1_5        (1 << 12)
88#define US_MR_NBSTOP_2          (2 << 12)
89#define US_MR_CHMODE            (3 << 14)               /* Channel Mode */
90#define US_MR_CHMODE_NORM       (0 << 14)               /* Normal Mode */
91#define US_MR_CHMODE_AUTO       (1 << 14)               /* Auto Echo: RXD drives TXD */
92#define US_MR_CHMODE_LOC        (2 << 14)               /* Local Loopback: TXD drives RXD */
93#define US_MR_CHMODE_REM        (3 << 14)               /* Remote Loopback: RXD pin connected to TXD pin. */
94#define US_MR_MSBF              (1 << 16)               /* Bit Order */
95#define US_MR_MODE9             (1 << 17)               /* 9-bit Character Length */
96#define US_MR_CLKO              (1 << 18)               /* Clock Output Select */
97#define US_MR_OVER              (1 << 19)               /* Oversampling Mode */
98#define US_MR_INACK             (1 << 20)               /* Inhibit Non Acknowledge */
99#define US_MR_DSNACK            (1 << 21)               /* Disable Successive NACK */
100#define US_MR_MAX_ITER          (7 << 24)               /* Max Iterations */
101#define US_MR_FILTER            (1 << 28)               /* Infrared Receive Line Filter */
102
103/* Interrupt Enable Register, US_IER, Offset 0x08 */
104/* Interrupt Disable Register, US_IDR, Offset 0x0C */
105/* Interrupt Mask Register, US_IMR, Offset 0x10 */
106/* Channel Status Register, US_SR, Offset 0x14 */
107#define US_IER_RXRDY      BIT0  /* RXRDY Interrupt */
108#define US_IER_TXRDY      BIT1  /* TXRDY Interrupt */
109#define US_IER_RXBRK      BIT2  /* End of Receive Transfer Interrupt */
110#define US_IER_ENDRX      BIT3  /* End of Receiver Transfer */
111//#define       US_IER_ENDTX      BIT4  /* End of Transmit Interrupt */
112#define US_IER_OVRE       BIT5  /* Overrun Interrupt */
113#define US_IER_FRAME      BIT6  /* Framing Error Interrupt */
114#define US_IER_PARE       BIT7  /* Parity Error */
115#define US_IER_TIMEOUT    BIT8  /* Receiver Time-out */
116#define US_IER_TXEMPTY    BIT9  /* Transmitter Empty */
117#define US_IER_ITERATION  BIT10 /* Max number of Repetitions Reached */
118#define US_IER_TXBUFE     BIT11 /* Transmission Buffer Empty */
119#define US_IER_RXBUFF     BIT12 /* Reception Buffer Full */
120#define US_IER_NACK       BIT13 /* Non Acknowledge */
121#define US_IER_RIIC       BIT16 /* Ring Indicator Input Change [AT91RM9200 only] */
122#define US_IER_DSRIC      BIT17 /* Data Set Ready Input Change [AT91RM9200 only] */
123#define US_IER_DCDIC      BIT18 /* Data Carrier Detect Input Change [AT91RM9200 only] */
124#define US_IER_CTSIC      BIT19 /* Clear to Send Input Change */
125#define US_IER_ALL        0xC0001AFB  /* all assigned bits */
126
127/* FORCE_NTRST Register, US_FNTR, Offset 0x48 */
128#define US_FNTR_NTRST         BIT0    /* 1 = Force NTRST low in JTAG */
129
130typedef struct {
131    volatile uint32_t cr;
132    volatile uint32_t mr;
133    volatile uint32_t ier;
134    volatile uint32_t idr;
135    volatile uint32_t imr;
136    volatile uint32_t sr;
137    volatile uint32_t rhr;
138    volatile uint32_t thr;
139    volatile uint32_t brgr;
140    volatile uint32_t _res0[7];
141    volatile uint32_t cidr;
142    volatile uint32_t exid;
143    volatile uint32_t fnr;
144} at91rm9200_usart_regs_t;
145
146#endif /* __AT91RM9200_USART_H__ */
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