source: rtems/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h @ 5e14d89

4.104.114.84.95
Last change on this file since 5e14d89 was 5e14d89, checked in by Joel Sherrill <joel.sherrill@…>, on 09/11/06 at 21:41:56

2006-09-11 Joel Sherrill <joel@…>

  • at91rm9200/include/at91rm9200.h, at91rm9200/include/at91rm9200_dbgu.h, at91rm9200/include/at91rm9200_emac.h, at91rm9200/include/at91rm9200_gpio.h, at91rm9200/include/at91rm9200_mem.h, at91rm9200/include/at91rm9200_pmc.h, s3c2400/include/s3c2400.h: Convert C++ style comments to C style.
  • Property mode set to 100644
File size: 8.6 KB
Line 
1/*
2 * AT91RM9200 Power Management and Clock definitions
3 *
4 * Copyright (c) 2002 by Cogent Computer Systems
5 * Written by Mike Kelly <mike@cogcomp.com>
6 *     
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  $Id$
13 */
14#ifndef __AT91RM9200_PMC_H__
15#define __AT91RM9200_PMC_H__
16
17#include <bits.h>
18
19/***********************************************************************
20 *       Power Management and Clock Control Register Offsets
21 ***********************************************************************/
22int at91rm9200_get_mainclk(void);
23int at91rm9200_get_slck(void);
24int at91rm9200_get_mck(void);
25
26
27#define PMC_SCER  0x00    /* System Clock Enable Register */
28#define PMC_SCDR  0x04    /* System Clock Disable Register */
29#define PMC_SCSR  0x08    /* System Clock Status Register */
30#define PMC_PCER  0x10    /* Peripheral Clock Enable Register */
31#define PMC_PCDR  0x14    /* Peripheral Clock Disable Register */
32#define PMC_PCSR  0x18    /* Peripheral Clock Status Register */
33#define PMC_MOR   0x20    /* Main Oscillator Register */
34#define PMC_MCFR  0x24    /* Main Clock  Frequency Register */
35#define PMC_PLLAR       0x28    /* PLL A Register */
36#define PMC_PLLBR       0x2C    /* PLL B Register */
37#define PMC_MCKR  0x30    /* Master Clock Register */
38#define PMC_PCKR0       0x40    /* Programmable Clock Register 0 */
39#define PMC_PCKR1       0x44    /* Programmable Clock Register 1 */
40#define PMC_PCKR2       0x48    /* Programmable Clock Register 2 */
41#define PMC_PCKR3       0x4C    /* Programmable Clock Register 3 */
42#define PMC_PCKR4       0x50    /* Programmable Clock Register 4 */
43#define PMC_PCKR5       0x54    /* Programmable Clock Register 5 */
44#define PMC_PCKR6       0x58    /* Programmable Clock Register 6 */
45#define PMC_PCKR7       0x5C    /* Programmable Clock Register 7 */
46#define PMC_IER   0x60    /* Interrupt Enable Register */
47#define PMC_IDR   0x64    /* Interrupt Disable Register */
48#define PMC_SR    0x68    /* Status Register */
49#define PMC_IMR   0x6C    /* Interrupt Mask Register */
50
51/* Bit Defines */
52
53/* PMC_SCDR - System Clock Disable Register */
54/* PMC_SCSR - System Clock Status Register */
55/* PMC_SCER - System Clock Enable Register */
56#define PMC_SCR_PCK7        BIT15
57#define PMC_SCR_PCK6        BIT14
58#define PMC_SCR_PCK5        BIT13
59#define PMC_SCR_PCK4        BIT12
60#define PMC_SCR_PCK3        BIT11
61#define PMC_SCR_PCK2        BIT10
62#define PMC_SCR_PCK1        BIT9
63#define PMC_SCR_PCK0        BIT8
64#define PMC_SCR_UHP           BIT4
65#define PMC_SCR_MCKUDP      BIT2
66#define PMC_SCR_UDP         BIT1
67#define PMC_SCR_PCK         BIT0
68
69/* PMC_PCER - Peripheral Clock Enable Register */
70/* PMC_PCDR - Peripheral Clock Disable Register */
71/* PMC_PCSR - Peripheral Clock Status Register */
72#define PMC_PCR_PID_EMAC    BIT24     /* Ethernet Peripheral Clock */
73#define PMC_PCR_PID_UHP     BIT23     /* USB Host Ports Peripheral Clock */
74#define PMC_PCR_PID_TC5     BIT22     /* Timer/Counter 5 Peripheral Clock */
75#define PMC_PCR_PID_TC4     BIT21     /* Timer/Counter 4 Peripheral Clock */
76#define PMC_PCR_PID_TC3     BIT20     /* Timer/Counter 3 Peripheral Clock */
77#define PMC_PCR_PID_TC2     BIT19     /* Timer/Counter 2 Peripheral Clock */
78#define PMC_PCR_PID_TC1     BIT18     /* Timer/Counter 1 Peripheral Clock */
79#define PMC_PCR_PID_TC0     BIT17     /* Timer/Counter 0 Peripheral Clock */
80#define PMC_PCR_PID_SSC2    BIT16     /* Synchronous Serial 2 Peripheral Clock */
81#define PMC_PCR_PID_SSC1    BIT15     /* Synchronous Serial 1 Peripheral Clock */
82#define PMC_PCR_PID_SSC0    BIT14     /* Synchronous Serial 0 Peripheral Clock */
83#define PMC_PCR_PID_SPI     BIT13     /* Serial Peripheral Interface Peripheral Clock */
84#define PMC_PCR_PID_TWI     BIT12     /* Two-Wire Interface Peripheral Clock */
85#define PMC_PCR_PID_UDP     BIT11     /* USB Device Port Peripheral Clock */
86#define PMC_PCR_PID_MCI     BIT10     /* MMC/SD Card Peripheral Clock */
87#define PMC_PCR_PID_US3     BIT9      /* USART 3 Peripheral Clock */
88#define PMC_PCR_PID_US2     BIT8      /* USART 2 Peripheral Clock */
89#define PMC_PCR_PID_US1     BIT7      /* USART 1 Peripheral Clock */
90#define PMC_PCR_PID_US0     BIT6      /* USART 0 Peripheral Clock */
91#define PMC_PCR_PID_PIOD    BIT5      /* Parallel I/O D Peripheral Clock */
92#define PMC_PCR_PID_PIOC    BIT4      /* Parallel I/O C Peripheral Clock */
93#define PMC_PCR_PID_PIOB    BIT3      /* Parallel I/O B Peripheral Clock */
94#define PMC_PCR_PID_PIOA    BIT2      /* Parallel I/O A Peripheral Clock */
95
96/* PMC_MOR - Main Oscillator Register */
97#define PMC_MOR_MOSCEN      BIT0
98
99/* PMC_MCFR - Main Clock  Frequency Register */
100#define PMC_MCFR_MAINRDY    BIT16
101
102/* PMC_PLLAR - PLL A Register */
103#define PMC_PLLAR_MUST_SET        BIT29           /* This bit must be set according to the docs */
104#define PMC_PLLAR_MUL(_x_)        ((_x_ & 0x7ff) << 16)   /* Multiplier    */
105#define PMC_PLLAR_MUL_MASK        (0x7ff << 16)   /* Multiplier mask */
106
107#define PMC_PLLAR_OUT_80_160    (0 << 14)             /* select when PLL frequency is 80-160 Mhz */
108#define PMC_PLLAR_OUT_150_240   (2 << 14)             /* select when PLL frequency is 150-240 Mhz */
109#define PMC_PLLAR_DIV(_x_)        ((_x_ & 0xff) << 0)       /* Divider */
110#define PMC_PLLAR_DIV_MASK        (0xff)    /* Divider mask */
111
112/* PMC_PLLBR - PLL B Register */
113#define PMC_PLLBR_USB_96M         BIT28           /* Set when PLL is 96Mhz to divide it by 2 for USB */
114#define PMC_PLLBR_MUL(_x_)        ((_x_ & 0x7ff) << 16)   /* Multiplier    */
115#define PMC_PLLBR_MUL_MASK      (0x7ff << 16)   /* Multiplier mask */
116#define PMC_PLLBR_OUT_80_160    (0 << 14)         /* select when PLL frequency is 80-160 Mhz */
117#define PMC_PLLBR_OUT_150_240   (2 << 14)        /* select when PLL frequency is 150-240 Mhz */
118#define PMC_PLLBR_DIV(_x_)      ((_x_ & 0xff) << 0)       /* Divider */
119#define PMC_PLLBR_DIV_MASK      (0xff)    /* Divider mask */
120
121/* PMC_MCKR - Master Clock Register */
122#define PMC_MCKR_MDIV_MASK      (3 << 8)        /* for masking out the MDIV field */
123#define PMC_MCKR_MDIV_1     (0 << 8)        /* MCK = Core/1 */
124#define PMC_MCKR_MDIV_2     (1 << 8)        /* MCK = Core/2 */
125#define PMC_MCKR_MDIV_3     (2 << 8)        /* MCK = Core/3 */
126#define PMC_MCKR_MDIV_4     (3 << 8)        /* MCK = Core/4 */
127#define PMC_MCKR_PRES_MASK        (7 << 2)        /* for masking out the PRES field */
128#define PMC_MCKR_PRES_1     (0 << 2)        /* Core = CSS/1 */
129#define PMC_MCKR_PRES_2     (1 << 2)        /* Core = CSS/2 */
130#define PMC_MCKR_PRES_4     (2 << 2)        /* Core = CSS/4 */
131#define PMC_MCKR_PRES_8     (3 << 2)        /* Core = CSS/8 */
132#define PMC_MCKR_PRES_16    (4 << 2)        /* Core = CSS/16 */
133#define PMC_MCKR_PRES_32    (5 << 2)        /* Core = CSS/32 */
134#define PMC_MCKR_PRES_64    (6 << 2)        /* Core = CSS/64 */
135#define PMC_MCKR_CSS_MASK         (3 << 0)        /* for masking out the CSS field */
136#define PMC_MCKR_CSS_SLOW         (0 << 0)        /* Core Source = Slow Clock */
137#define PMC_MCKR_CSS_MAIN         (1 << 0)        /* Core Source = Main Oscillator */
138#define PMC_MCKR_CSS_PLLA         (2 << 0)        /* Core Source = PLL A */
139#define PMC_MCKR_CSS_PLLB         (3 << 0)        /* Core Source = PLL B */
140
141/* PMC_PCKR0 - 7 - Programmable Clock Register 0 */
142#define PMC_PCKR_PRES_1     (0 << 2)        /* Peripheral Clock = CSS/1 */
143#define PMC_PCKR_PRES_2     (1 << 2)        /* Peripheral Clock = CSS/2 */
144#define PMC_PCKR_PRES_4     (2 << 2)        /* Peripheral Clock = CSS/4 */
145#define PMC_PCKR_PRES_8     (3 << 2)        /* Peripheral Clock = CSS/8 */
146#define PMC_PCKR_PRES_16    (4 << 2)        /* Peripheral Clock = CSS/16 */
147#define PMC_PCKR_PRES_32    (5 << 2)        /* Peripheral Clock = CSS/32 */
148#define PMC_PCKR_PRES_64    (6 << 2)        /* Peripheral Clock = CSS/64 */
149#define PMC_PCKR_CSS_SLOW         (0 << 0)        /* Peripheral Clock Source = Slow Clock */
150#define PMC_PCKR_CSS_MAIN         (1 << 0)        /* Peripheral Clock Source = Main Oscillator */
151#define PMC_PCKR_CSS_PLLA         (2 << 0)        /* Peripheral Clock Source = PLL A */
152#define PMC_PCKR_CSS_PLLB         (3 << 0)        /* Peripheral Clock Source = PLL B */
153
154/* PMC_IER - Interrupt Enable Register */
155/* PMC_IDR - Interrupt Disable Register */
156/* PMC_SR - Status Register */
157/* PMC_IMR - Interrupt Mask Register */
158#define PMC_INT_PCK7_RDY    BIT15
159#define PMC_INT_PCK6_RDY    BIT14
160#define PMC_INT_PCK5_RDY    BIT13
161#define PMC_INT_PCK4_RDY    BIT12
162#define PMC_INT_PCK3_RDY    BIT11
163#define PMC_INT_PCK2_RDY    BIT10
164#define PMC_INT_PCK1_RDY    BIT9
165#define PMC_INT_PCK0_RDY    BIT8
166#define PMC_INT_MCK_RDY     BIT3
167#define PMC_INT_LOCKB       BIT2
168#define PMC_INT_LCKA        BIT1
169#define PMC_INT_MOSCS       BIT0
170
171
172#endif
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