1 | /* |
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2 | * AT91RM9200 Memory Controller definitions |
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3 | * |
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4 | * Copyright (c) 2002 by Cogent Computer Systems |
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5 | * Written by Mike Kelly <mike@cogcomp.com> |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * |
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10 | * http://www.OARcorp.com/rtems/license.html. |
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11 | * |
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12 | * $Id$ |
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13 | */ |
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14 | #ifndef AT91RM9200_MEM_H |
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15 | #define AT91RM9200_MEM_H |
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16 | |
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17 | // ***************************************************************************** |
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18 | // External Bus Interface Unit |
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19 | // ***************************************************************************** |
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20 | #define EBI_CSA 0x00 // Chip Select Assignment Register |
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21 | #define EBI_CFGR 0x04 // Configuration Register |
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22 | |
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23 | // Bit Defines |
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24 | // EBI_CSA - Chip Select Assignment Register |
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25 | #define EBI_CSA_CS4_CF BIT4 // 1 = CS4-6 are assigned to Compact Flash, 0 = Chip Selects |
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26 | #define EBI_CSA_CS3_SMM BIT3 // 1 = CS3 is assigned to SmartMedia, 0 = Chip Select |
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27 | #define EBI_CSA_CS1_SDRAM BIT1 // 1 = CS1 is assigned to SDRAM, 0 = Chip Select |
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28 | #define EBI_CSA_CS0_BF BIT0 // 1 = CS0 is assigned to Burst Flash, 0 = Chip Select |
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29 | |
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30 | // EBI_CFGR - Configuration Register |
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31 | #define EBI_CFGR_DBPU BIT0 // 1 = Disable D0-15 pullups |
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32 | |
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33 | // ***************************************************************************** |
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34 | // Static Memory Interface Unit |
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35 | // ***************************************************************************** |
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36 | #define SMC_CSR0 0x00 // Chip Select Register 0 |
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37 | #define SMC_CSR1 0x04 // Chip Select Register 1 |
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38 | #define SMC_CSR2 0x08 // Chip Select Register 2 |
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39 | #define SMC_CSR3 0x0C // Chip Select Register 3 |
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40 | #define SMC_CSR4 0x10 // Chip Select Register 4 |
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41 | #define SMC_CSR5 0x14 // Chip Select Register 5 |
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42 | #define SMC_CSR6 0x18 // Chip Select Register 6 |
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43 | #define SMC_CSR7 0x1C // Chip Select Register 7 |
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44 | |
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45 | // Bit Defines |
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46 | // SMC_CSR0 -7 - Chip Selects 0 - 7 Register |
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47 | #define SMC_CSR_RWHOLD(_x_) ((_x_ & 0x3) << 28) // Hold CS after R/W strobes |
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48 | #define SMC_CSR_RWSETUP(_x_) ((_x_ & 0x3) << 24) // Setup CS before R/W strobes |
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49 | #define SMC_CSR_ACSS_0 (0 << 16) // Setup/Hold Address 0 clocks before/after CS |
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50 | #define SMC_CSR_ACSS_1 (1 << 16) // Setup/Hold Address 1 clock before/after CS |
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51 | #define SMC_CSR_ACSS_2 (2 << 16) // Setup/Hold Address 2 clocks before/after CS |
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52 | #define SMC_CSR_ACSS_3 (3 << 16) // Setup/Hold Address 3 clocks before/after CS |
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53 | #define SMC_CSR_DRP_NORMAL 0 // 0 = normal read protocol |
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54 | #define SMC_CSR_DRP_EARLY BIT15 // 1 = early read protocol |
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55 | #define SMC_CSR_DBW_16 (1 << 13) // CS DataBus Width = 16-Bits |
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56 | #define SMC_CSR_DBW_8 (2 << 13) // CS DataBus Width = 8 Bits |
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57 | #define SMC_CSR_BAT_16_1 0 // Single 16-Bit device (when DBW is 16) |
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58 | #define SMC_CSR_BAT_16_2 BIT12 // Dual 8-Bit devices (when DBW is 16) |
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59 | #define SMC_CSR_TDF(_x_) ((_x_ & 0xf) << 8) // Intercycle Data Float Time |
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60 | #define SMC_CSR_WSEN BIT7 // 1 = wait states are enabled |
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61 | #define SMC_CSR_NWS(_x_) ((_x_ & 0x7f) << 0) // Wait States + 1 |
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62 | |
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63 | // ***************************************************************************** |
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64 | // SDRAM Memory Interface Unit |
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65 | // ***************************************************************************** |
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66 | #define SDRC_MR 0x00 // Mode Register |
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67 | #define SDRC_TR 0x04 // Refresh Timer Register |
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68 | #define SDRC_CR 0x08 // Configuration Register |
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69 | #define SDRC_SRR 0x0C // Self Refresh Register |
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70 | #define SDRC_LPR 0x10 // Low Power Register |
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71 | #define SDRC_IER 0x14 // Interrupt Enable Register |
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72 | #define SDRC_IDR 0x18 // Interrupt Disable Register |
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73 | #define SDRC_IMR 0x1C // Interrupt Mask Register |
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74 | #define SDRC_ISR 0x20 // Interrupt Status Register |
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75 | |
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76 | // Bit Defines |
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77 | // SDRC_MR - Mode Register |
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78 | #define SDRC_MR_DBW_16 BIT4 // 1 = SDRAM is 16-bits wide, 0 = 32-bits |
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79 | #define SDRC_MR_NORM (0 << 0) // Normal Mode - All accesses to SDRAM are decoded normally |
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80 | #define SDRC_MR_NOP (1 << 0) // NOP Command is sent to SDRAM |
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81 | #define SDRC_MR_PRE (2 << 0) // Precharge All Command is sent to SDRAM |
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82 | #define SDRC_MR_MRS (3 << 0) // Mode Register Set Command is sent to SDRAM |
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83 | #define SDRC_MR_REF (4 << 0) // Refresh Command is sent to SDRAM |
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84 | |
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85 | // SDRC_TR - Refresh Timer Register |
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86 | #define SDRC_TR_COUNT(_x_) ((_x_ & 0xfff) << 0) |
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87 | |
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88 | // SDRC_CR - Configuration Register |
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89 | #define SDRC_CR_TXSR(_x_) ((_x_ & 0xf) << 27) // CKE to ACT Time |
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90 | #define SDRC_CR_TRAS(_x_) ((_x_ & 0xf) << 23) // ACT to PRE Time |
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91 | #define SDRC_CR_TRCD(_x_) ((_x_ & 0xf) << 19) // RAS to CAS Time |
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92 | #define SDRC_CR_TRP(_x_) ((_x_ & 0xf) << 15) // PRE to ACT Time |
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93 | #define SDRC_CR_TRC(_x_) ((_x_ & 0xf) << 11) // REF to ACT Time |
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94 | #define SDRC_CR_TWR(_x_) ((_x_ & 0xf) << 7) // Write Recovery Time |
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95 | #define SDRC_CR_CAS_2 (2 << 5) // Cas Delay = 2, this is the only supported value |
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96 | #define SDRC_CR_NB_2 0 // 2 Banks per device |
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97 | #define SDRC_CR_NB_4 BIT4 // 4 Banks per device |
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98 | #define SDRC_CR_NR_11 (0 << 2) // Number of rows = 11 |
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99 | #define SDRC_CR_NR_12 (1 << 2) // Number of rows = 12 |
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100 | #define SDRC_CR_NR_13 (2 << 2) // Number of rows = 13 |
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101 | #define SDRC_CR_NC_8 (0 << 0) // Number of columns = 8 |
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102 | #define SDRC_CR_NC_9 (1 << 0) // Number of columns = 9 |
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103 | #define SDRC_CR_NC_10 (2 << 0) // Number of columns = 10 |
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104 | #define SDRC_CR_NC_11 (3 << 0) // Number of columns = 11 |
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105 | |
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106 | // SDRC_SRR - Self Refresh Register |
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107 | #define SDRC_SRR_SRCB BIT0 // 1 = Enter Self Refresh |
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108 | |
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109 | // SDRC_LPR - Low Power Register |
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110 | #define SDRC_LPR_LPCB BIT0 // 1 = De-assert CKE between accesses |
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111 | |
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112 | // SDRC_IER - Interrupt Enable Register |
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113 | // SDRC_IDR - Interrupt Disable Register |
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114 | // SDRC_ISR - Interrupt Mask Register |
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115 | // SDRC_IMR - Interrupt Mask Register |
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116 | #define SDRC_INT_RES BIT0 // Refresh Error Status |
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117 | |
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118 | #endif |
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