1 | /* |
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2 | * AT91RM9200 GPIO definitions |
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3 | * |
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4 | * Copyright (c) 2002 by Cogent Computer Systems |
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5 | * Written by Mike Kelly <mike@cogcomp.com> |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * |
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10 | * http://www.rtems.com/license/LICENSE. |
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11 | * |
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12 | * $Id$ |
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13 | */ |
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14 | #ifndef AT91RM9200_GPIO_H |
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15 | #define AT91RM9200_GPIO_H |
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16 | |
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17 | #include <bits.h> |
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18 | |
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19 | /* Register Offsets */ |
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20 | #define PIO_PER 0x00 /* PIO Enable Register */ |
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21 | #define PIO_PDR 0x04 /* PIO Disable Register */ |
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22 | #define PIO_PSR 0x08 /* PIO Status Register */ |
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23 | #define PIO_OER 0x10 /* Output Enable Register */ |
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24 | #define PIO_ODR 0x14 /* Output Disable Registerr */ |
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25 | #define PIO_OSR 0x18 /* Output Status Register */ |
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26 | #define PIO_IFER 0x20 /* Input Filter Enable Register */ |
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27 | #define PIO_IFDR 0x24 /* Input Filter Disable Register */ |
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28 | #define PIO_IFSR 0x28 /* Input Filter Status Register */ |
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29 | #define PIO_SODR 0x30 /* Set Output Data Register */ |
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30 | #define PIO_CODR 0x34 /* Clear Output Data Register */ |
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31 | #define PIO_ODSR 0x38 /* Output Data Status Register */ |
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32 | #define PIO_PDSR 0x3c /* Pin Data Status Register */ |
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33 | #define PIO_IER 0x40 /* Interrupt Enable Register */ |
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34 | #define PIO_IDR 0x44 /* Interrupt Disable Register */ |
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35 | #define PIO_IMR 0x48 /* Interrupt Mask Register */ |
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36 | #define PIO_ISR 0x4c /* Interrupt Status Register */ |
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37 | #define PIO_MDER 0x50 /* Multi-driver Enable Register */ |
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38 | #define PIO_MDDR 0x54 /* Multi-driver Disable Register */ |
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39 | #define PIO_MDSR 0x58 /* Multi-driver Status Register */ |
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40 | #define PIO_PUDR 0x60 /* Pull-up Disable Register */ |
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41 | #define PIO_PUER 0x64 /* Pull-up Enable Register */ |
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42 | #define PIO_PUSR 0x68 /* Pad Pull-up Status Register */ |
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43 | #define PIO_ASR 0x70 /* Select A Register */ |
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44 | #define PIO_BSR 0x74 /* Select B Register */ |
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45 | #define PIO_ABSR 0x78 /* AB Select Status Register */ |
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46 | #define PIO_OWER 0xA0 /* Output Write Enable Register */ |
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47 | #define PIO_OWDR 0xA4 /* Output Write Disable Register */ |
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48 | #define PIO_OWSR 0xA8 /* Output Write Status Register */ |
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49 | |
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50 | |
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51 | /* |
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52 | * The AT91RM9200 GPIO's are spread across four 32-bit ports A-D. |
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53 | * To make it easier to interface with them and to eliminate the need |
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54 | * to track which GPIO is in which port, we convert the Port x, Bit y |
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55 | * into a single GPIO number 0 - 127. |
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56 | * |
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57 | * Board specific defines will assign the board level signal to a |
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58 | * virutal GPIO. |
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59 | * |
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60 | * PORT A |
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61 | */ |
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62 | #define GPIO_0 BIT0 |
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63 | #define GPIO_1 BIT1 |
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64 | #define GPIO_2 BIT2 |
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65 | #define GPIO_3 BIT3 |
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66 | #define GPIO_4 BIT4 |
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67 | #define GPIO_5 BIT5 |
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68 | #define GPIO_6 BIT6 |
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69 | #define GPIO_7 BIT7 |
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70 | #define GPIO_8 BIT8 |
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71 | #define GPIO_9 BIT9 |
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72 | #define GPIO_10 BIT10 |
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73 | #define GPIO_11 BIT11 |
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74 | #define GPIO_12 BIT12 |
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75 | #define GPIO_13 BIT13 |
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76 | #define GPIO_14 BIT14 |
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77 | #define GPIO_15 BIT15 |
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78 | #define GPIO_16 BIT16 |
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79 | #define GPIO_17 BIT17 |
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80 | #define GPIO_18 BIT18 |
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81 | #define GPIO_19 BIT19 |
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82 | #define GPIO_20 BIT20 |
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83 | #define GPIO_21 BIT21 |
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84 | #define GPIO_22 BIT22 |
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85 | #define GPIO_23 BIT23 |
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86 | #define GPIO_24 BIT24 |
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87 | #define GPIO_25 BIT25 |
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88 | #define GPIO_26 BIT26 |
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89 | #define GPIO_27 BIT27 |
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90 | #define GPIO_28 BIT28 |
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91 | #define GPIO_29 BIT29 |
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92 | #define GPIO_30 BIT30 |
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93 | #define GPIO_31 BIT31 |
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94 | /* PORT B */ |
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95 | #define GPIO_32 BIT0 |
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96 | #define GPIO_33 BIT1 |
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97 | #define GPIO_34 BIT2 |
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98 | #define GPIO_35 BIT3 |
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99 | #define GPIO_36 BIT4 |
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100 | #define GPIO_37 BIT5 |
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101 | #define GPIO_38 BIT6 |
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102 | #define GPIO_39 BIT7 |
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103 | #define GPIO_40 BIT8 |
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104 | #define GPIO_41 BIT9 |
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105 | #define GPIO_42 BIT10 |
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106 | #define GPIO_43 BIT11 |
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107 | #define GPIO_44 BIT12 |
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108 | #define GPIO_45 BIT13 |
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109 | #define GPIO_46 BIT14 |
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110 | #define GPIO_47 BIT15 |
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111 | #define GPIO_48 BIT16 |
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112 | #define GPIO_49 BIT17 |
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113 | #define GPIO_50 BIT18 |
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114 | #define GPIO_51 BIT19 |
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115 | #define GPIO_52 BIT20 |
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116 | #define GPIO_53 BIT21 |
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117 | #define GPIO_54 BIT22 |
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118 | #define GPIO_55 BIT23 |
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119 | #define GPIO_56 BIT24 |
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120 | #define GPIO_57 BIT25 |
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121 | #define GPIO_58 BIT26 |
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122 | #define GPIO_59 BIT27 |
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123 | #define GPIO_60 BIT28 |
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124 | #define GPIO_61 BIT29 |
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125 | #define GPIO_62 BIT30 |
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126 | #define GPIO_63 BIT31 |
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127 | /* PORT C */ |
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128 | #define GPIO_64 BIT0 |
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129 | #define GPIO_65 BIT1 |
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130 | #define GPIO_66 BIT2 |
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131 | #define GPIO_67 BIT3 |
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132 | #define GPIO_68 BIT4 |
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133 | #define GPIO_69 BIT5 |
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134 | #define GPIO_70 BIT6 |
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135 | #define GPIO_71 BIT7 |
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136 | #define GPIO_72 BIT8 |
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137 | #define GPIO_73 BIT9 |
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138 | #define GPIO_74 BIT10 |
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139 | #define GPIO_75 BIT11 |
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140 | #define GPIO_76 BIT12 |
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141 | #define GPIO_77 BIT13 |
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142 | #define GPIO_78 BIT14 |
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143 | #define GPIO_79 BIT15 |
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144 | #define GPIO_80 BIT16 |
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145 | #define GPIO_81 BIT17 |
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146 | #define GPIO_82 BIT18 |
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147 | #define GPIO_83 BIT19 |
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148 | #define GPIO_84 BIT20 |
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149 | #define GPIO_85 BIT21 |
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150 | #define GPIO_86 BIT22 |
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151 | #define GPIO_87 BIT23 |
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152 | #define GPIO_88 BIT24 |
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153 | #define GPIO_89 BIT25 |
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154 | #define GPIO_90 BIT26 |
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155 | #define GPIO_91 BIT27 |
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156 | #define GPIO_92 BIT28 |
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157 | #define GPIO_93 BIT29 |
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158 | #define GPIO_94 BIT30 |
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159 | #define GPIO_95 BIT31 |
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160 | /* PORT D */ |
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161 | #define GPIO_96 BIT0 |
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162 | #define GPIO_97 BIT1 |
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163 | #define GPIO_98 BIT2 |
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164 | #define GPIO_99 BIT3 |
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165 | #define GPIO_100 BIT4 |
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166 | #define GPIO_101 BIT5 |
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167 | #define GPIO_102 BIT6 |
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168 | #define GPIO_103 BIT7 |
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169 | #define GPIO_104 BIT8 |
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170 | #define GPIO_105 BIT9 |
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171 | #define GPIO_106 BIT10 |
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172 | #define GPIO_107 BIT11 |
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173 | #define GPIO_108 BIT12 |
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174 | #define GPIO_109 BIT13 |
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175 | #define GPIO_110 BIT14 |
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176 | #define GPIO_111 BIT15 |
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177 | #define GPIO_112 BIT16 |
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178 | #define GPIO_113 BIT17 |
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179 | #define GPIO_114 BIT18 |
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180 | #define GPIO_115 BIT19 |
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181 | #define GPIO_116 BIT20 |
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182 | #define GPIO_117 BIT21 |
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183 | #define GPIO_118 BIT22 |
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184 | #define GPIO_119 BIT23 |
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185 | #define GPIO_120 BIT24 |
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186 | #define GPIO_121 BIT25 |
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187 | #define GPIO_122 BIT26 |
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188 | #define GPIO_123 BIT27 |
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189 | #define GPIO_124 BIT28 |
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190 | #define GPIO_125 BIT29 |
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191 | #define GPIO_126 BIT30 |
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192 | #define GPIO_127 BIT31 |
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193 | |
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194 | /* |
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195 | * Most of the GPIO pins can have one of two alternate functions |
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196 | * in addition to being GPIO |
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197 | * |
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198 | * Port A, Alternate Function A |
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199 | */ |
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200 | #define PIOA_ASR_MISO BIT0 /* SPI Master In (RX), Slave out */ |
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201 | #define PIOA_ASR_MOSI BIT1 /* SPI Master Out (TX), Slave In */ |
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202 | #define PIOA_ASR_SPCK BIT2 /* SPI Clock */ |
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203 | #define PIOA_ASR_NPCS0 BIT3 /* SPI Chip Select 0 */ |
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204 | #define PIOA_ASR_NPCS1 BIT4 /* SPI Chip Select 1 */ |
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205 | #define PIOA_ASR_NPCS2 BIT5 /* SPI Chip Select 2 */ |
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206 | #define PIOA_ASR_NPCS3 BIT6 /* SPI Chip Select 3 */ |
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207 | #define PIOA_ASR_ETXCK BIT7 /* EMAC TX Clock */ |
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208 | #define PIOA_ASR_ETXEN BIT8 /* EMAC TXEN */ |
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209 | #define PIOA_ASR_ETX0 BIT9 /* EMAC TXD0 */ |
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210 | #define PIOA_ASR_ETX1 BIT10 /* EMAC TXD1 */ |
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211 | #define PIOA_ASR_ECRS BIT11 /* EMAC CRS */ |
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212 | #define PIOA_ASR_ERX0 BIT12 /* EMAC RXD0 */ |
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213 | #define PIOA_ASR_ERX1 BIT13 /* EMAC RXD1 */ |
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214 | #define PIOA_ASR_ERXER BIT14 /* EMAC RXER */ |
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215 | #define PIOA_ASR_EMDC BIT15 /* EMAC MDC */ |
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216 | #define PIOA_ASR_EMDIO BIT16 /* EMAC MDIO */ |
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217 | #define PIOA_ASR_TXD0 BIT17 /* USART 0 Receive */ |
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218 | #define PIOA_ASR_RXD0 BIT18 /* USART 0 Transmit */ |
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219 | #define PIOA_ASR_SCK0 BIT19 /* USART 0 Clock */ |
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220 | #define PIOA_ASR_CTS0 BIT20 /* USART 0 CTS */ |
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221 | #define PIOA_ASR_RTS0 BIT21 /* USART 0 RTS */ |
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222 | #define PIOA_ASR_RXD2 BIT22 /* USART 2 Receive */ |
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223 | #define PIOA_ASR_TXD2 BIT23 /* USART 2 Transmit */ |
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224 | #define PIOA_ASR_SCK2 BIT24 /* USART 2 Clock */ |
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225 | #define PIOA_ASR_TWD BIT25 /* Two-Wire (I2C) Data */ |
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226 | #define PIOA_ASR_TWCK BIT26 /* Two-Wire (I2C) Clock */ |
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227 | #define PIOA_ASR_MCCK BIT27 /* MMC/SD Card Clock */ |
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228 | #define PIOA_ASR_MCCDA BIT28 /* MMC/SD Card A Command */ |
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229 | #define PIOA_ASR_MCDA0 BIT29 /* MMC/SD Card A Data 0 */ |
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230 | #define PIOA_ASR_DRXD BIT30 /* Debug Uart Receive */ |
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231 | #define PIOA_ASR_DTXD BIT31 /* Debug Uart Transmit */ |
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232 | |
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233 | /* Port A, Alternate Function B */ |
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234 | #define PIOA_BSR_PCK3 BIT0 /* Peripheral Clock 3 */ |
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235 | #define PIOA_BSR_PCK0 BIT1 /* Peripheral Clock 0 */ |
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236 | #define PIOA_BSR_IRQ4 BIT2 /* IRQ4 */ |
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237 | #define PIOA_BSR_IRQ5 BIT3 /* IRQ5 */ |
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238 | /*#define PIOA_BSR_PCK1 BIT4 Peripheral Clock 1 ***DUPLICATED at BIT24 ??? */ |
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239 | #define PIOA_BSR_TXD3 BIT5 /* USART 3 Transmit */ |
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240 | #define PIOA_BSR_RXD3 BIT6 /* USART 3 Receive */ |
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241 | #define PIOA_BSR_PCK2 BIT7 /* Peripheral Clock 2 */ |
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242 | #define PIOA_BSR_MCCDB BIT8 /* MMC/SD Card B Command */ |
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243 | #define PIOA_BSR_MCDB0 BIT9 /* MMC/SD Card B Data 0 */ |
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244 | #define PIOA_BSR_MCDB1 BIT10 /* MMC/SD Card B Data 1 */ |
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245 | #define PIOA_BSR_MCDB2 BIT11 /* MMC/SD Card B Data 2 */ |
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246 | #define PIOA_BSR_MCDB3 BIT12 /* MMC/SD C ard B Data 3 */ |
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247 | #define PIOA_BSR_TCLK0 BIT13 /* Timer 0 Clock */ |
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248 | #define PIOA_BSR_TCLK1 BIT14 /* Timer 1 Clck */ |
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249 | #define PIOA_BSR_TCLK2 BIT15 /* Timer 2 Clock */ |
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250 | #define PIOA_BSR_IRQ6 BIT16 /* IRQ6 */ |
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251 | #define PIOA_BSR_TIOA0 BIT17 /* Timer 0 I/O A */ |
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252 | #define PIOA_BSR_TIOB0 BIT18 /* Timer 0 I/O B */ |
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253 | #define PIOA_BSR_TIOA1 BIT19 /* Timer 1 I/O A */ |
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254 | #define PIOA_BSR_TIOB1 BIT20 /* Timer 1 I/O B */ |
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255 | #define PIOA_BSR_TIOA2 BIT21 /* Timer 2 I/O A */ |
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256 | #define PIOA_BSR_TIOB2 BIT22 /* Timer 2 I/O B */ |
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257 | #define PIOA_BSR_IRQ3 BIT23 /* IRQ3 */ |
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258 | #define PIOA_BSR_PCK1 BIT24 /* Peripheral Clock 1 */ |
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259 | #define PIOA_BSR_IRQ2 BIT25 /* IRQ2 */ |
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260 | #define PIOA_BSR_IRQ1 BIT26 /* IRQ1 */ |
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261 | #define PIOA_BSR_TCLK3 BIT27 /* Timer Block Clock 3 (docs only show 0-2?) */ |
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262 | #define PIOA_BSR_TCLK4 BIT28 /* Timer Block Clock 4 */ |
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263 | #define PIOA_BSR_TCLK5 BIT29 /* Timer Block Clock 5 */ |
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264 | #define PIOA_BSR_CTS2 BIT30 /* USART 2 CTS */ |
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265 | #define PIOA_BSR_RTS2 BIT31 /* USART 2 RTS */ |
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266 | |
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267 | /* Port B, Function A */ |
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268 | #define PIOB_ASR_TF0 BIT0 /* AC'97/I2S 0 Transmit Frame */ |
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269 | #define PIOB_ASR_TK0 BIT1 /* AC'97/I2S 0 Transmit Clock */ |
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270 | #define PIOB_ASR_TD0 BIT2 /* AC'97/I2S 0 Transmit Data */ |
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271 | #define PIOB_ASR_RD0 BIT3 /* AC'97/I2S 0 Receive Data */ |
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272 | #define PIOB_ASR_RK0 BIT4 /* AC'97/I2S 0 Receive Clock */ |
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273 | #define PIOB_ASR_RF0 BIT5 /* AC'97/I2S 0 Receive Frame */ |
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274 | #define PIOB_ASR_TF1 BIT6 /* AC'97/I2S 1 Transmit Frame */ |
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275 | #define PIOB_ASR_TK1 BIT7 /* AC'97/I2S 1 Transmit Clock */ |
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276 | #define PIOB_ASR_TD1 BIT8 /* AC'97/I2S 1 Transmit Data */ |
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277 | #define PIOB_ASR_RD1 BIT9 /* AC'97/I2S 1 Receive Data */ |
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278 | #define PIOB_ASR_RK1 BIT10 /* AC'97/I2S 1 Receive Clock */ |
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279 | #define PIOB_ASR_RF1 BIT11 /* AC'97/I2S 1 Receive Frame */ |
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280 | #define PIOB_ASR_TF2 BIT12 /* AC'97/I2S 1 Transmit Frame */ |
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281 | #define PIOB_ASR_TK2 BIT13 /* AC'97/I2S 1 Transmit Clock */ |
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282 | #define PIOB_ASR_TD2 BIT14 /* AC'97/I2S 1 Transmit Data */ |
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283 | #define PIOB_ASR_RD2 BIT15 /* AC'97/I2S 1 Receive Data */ |
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284 | #define PIOB_ASR_RK2 BIT16 /* AC'97/I2S 1 Receive Clock */ |
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285 | #define PIOB_ASR_RF2 BIT17 /* AC'97/I2S 1 Receive Frame */ |
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286 | #define PIOB_ASR_RI1 BIT18 /* USART 1 RI */ |
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287 | #define PIOB_ASR_DTR1 BIT19 /* USART 1 DTR */ |
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288 | #define PIOB_ASR_TXD1 BIT20 /* USART 1 TXD */ |
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289 | #define PIOB_ASR_RXD1 BIT21 /* USART 1 RXD */ |
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290 | #define PIOB_ASR_SCK1 BIT22 /* USART 1 SCK */ |
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291 | #define PIOB_ASR_DCD1 BIT23 /* USART 1 DCD */ |
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292 | #define PIOB_ASR_CTS1 BIT24 /* USART 1 CTS */ |
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293 | #define PIOB_ASR_DSR1 BIT25 /* USART 1 DSR */ |
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294 | #define PIOB_ASR_RTS1 BIT26 /* USART 1 RTS */ |
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295 | #define PIOB_ASR_PCK0 BIT27 /* Peripheral Clock 0 */ |
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296 | #define PIOB_ASR_FIQ BIT28 /* FIQ */ |
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297 | #define PIOB_ASR_IRQ0 BIT29 /* IRQ0 */ |
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298 | |
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299 | /* Port B, Function B */ |
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300 | #define PIOB_BSR_RTS3 BIT0 /* USART 3 */ |
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301 | #define PIOB_BSR_CTS3 BIT1 /* USART 3 */ |
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302 | #define PIOB_BSR_SCK3 BIT2 /* USART 3 */ |
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303 | #define PIOB_BSR_MCDA1 BIT3 /* MMC/SD Card A, Data 1 */ |
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304 | #define PIOB_BSR_MCDA2 BIT4 /* MMC/SD Card A, Data 2 */ |
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305 | #define PIOB_BSR_MCDA3 BIT5 /* MMC/SD Card A, Data 3 */ |
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306 | #define PIOB_BSR_TIOA3 BIT6 /* Timer 3 IO A */ |
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307 | #define PIOB_BSR_TIOB3 BIT7 /* Timer 3 IO B */ |
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308 | #define PIOB_BSR_TIOA4 BIT8 /* Timer 4 IO A */ |
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309 | #define PIOB_BSR_TIOB4 BIT9 /* Timer 4 IO B */ |
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310 | #define PIOB_BSR_TIOA5 BIT10 /* Timer 5 IO A */ |
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311 | #define PIOB_BSR_TIOB5 BIT11 /* Timer 5 IO B */ |
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312 | #define PIOB_BSR_ETX2 BIT12 /* EMAC TXD2 */ |
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313 | #define PIOB_BSR_ETX3 BIT13 /* EMAC TXD3 */ |
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314 | #define PIOB_BSR_ETXER BIT14 /* EMAC TXER */ |
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315 | #define PIOB_BSR_ERX2 BIT15 /* EMAC RXD2 */ |
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316 | #define PIOB_BSR_ERX3 BIT16 /* EMAC RXD3 */ |
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317 | #define PIOB_BSR_ERXDV BIT17 /* EMAC RXDV */ |
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318 | #define PIOB_BSR_ECOL BIT18 /* EMAC COL */ |
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319 | #define PIOB_BSR_ERXCK BIT19 /* EMAC RX Clock */ |
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320 | #define PIOB_BSR_EF100 BIT25 /* EMAC Speed 100 (RMII Only) */ |
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321 | |
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322 | /* Port C, Alternate Function A */ |
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323 | #define PIOC_ASR_BFCK BIT0 /* Burst Flash Clock */ |
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324 | #define PIOC_ASR_BFRDY BIT1 /* Burst Flash Ready or SMC Card OE */ |
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325 | #define PIOC_ASR_BFAVD BIT2 /* Burst Flash Address Valid */ |
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326 | #define PIOC_ASR_BFBAA BIT3 /* Burst Flash Address Advance or SMC Card WE */ |
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327 | #define PIOC_ASR_BFOE BIT4 /* Burst Flash OE */ |
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328 | #define PIOC_ASR_BFWE BIT5 /* Burst Flash WE */ |
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329 | #define PIOC_ASR_NWAIT BIT6 /* WAIT Input */ |
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330 | #define PIOC_ASR_A23 BIT7 /* A23 */ |
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331 | #define PIOC_ASR_A24 BIT8 /* A24 */ |
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332 | #define PIOC_ASR_A25 BIT9 /* A25 or Compact Flash R/W */ |
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333 | #define PIOC_ASR_NCS4 BIT10 /* CS4 or Compact Flash CS */ |
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334 | #define PIOC_ASR_NCS5 BIT11 /* CS5 or Compact Flash CE1 */ |
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335 | #define PIOC_ASR_NCS6 BIT12 /* CS6 or Compact Flash CE2 */ |
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336 | #define PIOC_ASR_NCS7 BIT13 /* CS7 */ |
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337 | #define PIOC_ASR_D16 BIT16 /* Databus Bit 16 */ |
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338 | #define PIOC_ASR_D17 BIT17 /* Databus Bit 17 */ |
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339 | #define PIOC_ASR_D18 BIT18 /* Databus Bit 18 */ |
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340 | #define PIOC_ASR_D19 BIT19 /* Databus Bit 19 */ |
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341 | #define PIOC_ASR_D20 BIT20 /* Databus Bit 20 */ |
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342 | #define PIOC_ASR_D21 BIT21 /* Databus Bit 21 */ |
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343 | #define PIOC_ASR_D22 BIT22 /* Databus Bit 22 */ |
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344 | #define PIOC_ASR_D23 BIT23 /* Databus Bit 23 */ |
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345 | #define PIOC_ASR_D24 BIT24 /* Databus Bit 24 */ |
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346 | #define PIOC_ASR_D25 BIT25 /* Databus Bit 25 */ |
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347 | #define PIOC_ASR_D26 BIT26 /* Databus Bit 26 */ |
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348 | #define PIOC_ASR_D27 BIT27 /* Databus Bit 27 */ |
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349 | #define PIOC_ASR_D28 BIT28 /* Databus Bit 28 */ |
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350 | #define PIOC_ASR_D29 BIT29 /* Databus Bit 29 */ |
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351 | #define PIOC_ASR_D30 BIT30 /* Databus Bit 30 */ |
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352 | #define PIOC_ASR_D31 BIT31 /* Databus Bit 31 */ |
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353 | |
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354 | /* Port C, Alternate Function B - None */ |
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355 | |
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356 | /* Port D, Alternate Function A */ |
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357 | #define PIOD_ASR_ETX0 BIT0 /* EMAC TXD0 */ |
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358 | #define PIOD_ASR_ETX1 BIT1 /* EMAC TXD1 */ |
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359 | #define PIOD_ASR_ETX2 BIT2 /* EMAC TXD2 */ |
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360 | #define PIOD_ASR_ETX3 BIT3 /* EMAC TXD3 */ |
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361 | #define PIOD_ASR_ETXEN BIT4 /* EMAC TXEN */ |
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362 | #define PIOD_ASR_ETXER BIT5 /* EMAC TXER */ |
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363 | #define PIOD_ASR_DTXD BIT6 /* Debug UART Transmit */ |
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364 | #define PIOD_ASR_PCK0 BIT7 /* Peripheral Clock 0 */ |
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365 | #define PIOD_ASR_PCK1 BIT8 /* Peripheral Clock 1 */ |
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366 | #define PIOD_ASR_PCK2 BIT9 /* Peripheral Clock 2 */ |
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367 | #define PIOD_ASR_PCK3 BIT10 /* Peripheral Clock 3 */ |
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368 | #define PIOD_ASR_TD0 BIT15 /* AC'97/I2S 0 Transmit Data */ |
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369 | #define PIOD_ASR_TD1 BIT16 /* AC'97/I2S 1 Transmit Data */ |
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370 | #define PIOD_ASR_TD2 BIT17 /* AC'97/I2S 2 Transmit Data */ |
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371 | #define PIOD_ASR_NPCS1 BIT18 /* SPI Chip Select 1 */ |
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372 | #define PIOD_ASR_NPCS2 BIT19 /* SPI Chip Select 2 */ |
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373 | #define PIOD_ASR_NPCS3 BIT20 /* SPI Chip Select 3 */ |
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374 | #define PIOD_ASR_RTS0 BIT21 /* USART 0 RTS */ |
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375 | #define PIOD_ASR_RTS1 BIT22 /* USART 1 RTS */ |
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376 | #define PIOD_ASR_RTS2 BIT23 /* USART 2 RTS */ |
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377 | #define PIOD_ASR_RTS3 BIT24 /* USART 3 RTS */ |
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378 | #define PIOD_ASR_DTR1 BIT25 /* USART 1 DTR */ |
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379 | |
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380 | /* Port D, Alternate Function B */ |
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381 | |
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382 | #define PIOC_ASR_TSYNC BIT7 /* ETM Sync */ |
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383 | #define PIOC_ASR_TCLK BIT8 /* ETM Clock */ |
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384 | #define PIOC_ASR_TPS0 BIT9 /* ETM Processor Status 0 */ |
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385 | #define PIOC_ASR_TPS1 BIT10 /* ETM Processor Status 1 */ |
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386 | #define PIOC_ASR_TPS2 BIT11 /* ETM Processor Status 2 */ |
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387 | #define PIOC_ASR_TPK0 BIT12 /* ETM Packet Data 0 */ |
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388 | #define PIOC_ASR_TPK1 BIT13 /* ETM Packet Data 1 */ |
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389 | #define PIOC_ASR_TPK2 BIT14 /* ETM Packet Data 2 */ |
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390 | #define PIOC_ASR_TPK3 BIT15 /* ETM Packet Data 3 */ |
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391 | #define PIOC_ASR_TPK4 BIT16 /* ETM Packet Data 4 */ |
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392 | #define PIOC_ASR_TPK5 BIT17 /* ETM Packet Data 5 */ |
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393 | #define PIOC_ASR_TPK6 BIT18 /* ETM Packet Data 6 */ |
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394 | #define PIOC_ASR_TPK7 BIT19 /* ETM Packet Data 7 */ |
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395 | #define PIOC_ASR_TPK8 BIT20 /* ETM Packet Data 8 */ |
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396 | #define PIOC_ASR_TPK9 BIT21 /* ETM Packet Data 9 */ |
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397 | #define PIOC_ASR_TPK10 BIT22 /* ETM Packet Data 10 */ |
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398 | #define PIOC_ASR_TPK11 BIT23 /* ETM Packet Data 11 */ |
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399 | #define PIOC_ASR_TPK12 BIT24 /* ETM Packet Data 12 */ |
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400 | #define PIOC_ASR_TPK13 BIT25 /* ETM Packet Data 13 */ |
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401 | #define PIOC_ASR_TPK14 BIT26 /* ETM Packet Data 14 */ |
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402 | #define PIOC_ASR_TPK15 BIT27 /* ETM Packet Data 15 */ |
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403 | |
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404 | #endif |
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