source: rtems/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h @ af85485

4.104.114.84.95
Last change on this file since af85485 was af85485, checked in by Jay Monkman <jtm@…>, on 07/15/04 at 06:24:14

2004-07-15 Jay Monkman

  • ChangeLog?, Makefile.am, clock/.cvsignore, clock/clock.c, dbgu/.cvsignore, dbgu/dbgu.c, include/at91rm9200.h, include/at91rm9200_dbgu.h, include/at91rm9200_emac.h, include/at91rm9200_gpio.h, include/at91rm9200_mem.h, include/at91rm9200_pmc.h, include/bits.h, irq/.cvsignore, irq/bsp_irq_asm.S, irq/bsp_irq_init.c, irq/irq.c, irq/irq.h, pmc/pmc.c, timer/.cvsignore, timer/timer.c: New files.
  • Property mode set to 100644
File size: 8.8 KB
Line 
1/*
2 * Atmel AT91RM9200 EMAC Register definitions
3 *
4 * Copyright (c) 2003 by Cogent Computer Systems
5 * Written by Mike Kelly <mike@cogcomp.com>
6 *     
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  $Id$
13 */
14#ifndef __AT91RM9200_EMAC_H__
15#define __AT91RM9200_EMAC_H__
16
17#include <bits.h>
18
19//Register offsets
20#define EMAC_CTL        0x00            // Network Control Register
21#define EMAC_CFG        0x04            // Network Configuration Register
22#define EMAC_SR         0x08            // Network Status Register
23#define EMAC_TAR        0x0C            // Transmit Address Register
24#define EMAC_TCR        0x10            // Transmit Control Register
25#define EMAC_TSR        0x14            // Transmit Status Register
26#define EMAC_RBQP       0x18            // Receive Buffer Queue Pointer
27#define EMAC_RSR        0x20            // Receive Status Register
28#define EMAC_ISR        0x24            // Interrupt Enable Register
29#define EMAC_IER        0x28            // Interrupt Enable Register
30#define EMAC_IDR        0x2C            // Interrupt Disable Register
31#define EMAC_IMR        0x30            // Interrupt Mask Register
32#define EMAC_MAN        0x34            // PHY Maintenance Register
33#define EMAC_FRA        0x40            // Frames Transmitted OK Register
34#define EMAC_SCOL       0x44            // Single Collision Frame Register
35#define EMAC_MCOL       0x48            // Multiple Collision Frame Register
36#define EMAC_OK         0x4C            // Frames Received OK Register
37#define EMAC_SEQE       0x50            // Frame Check Sequence Error Register
38#define EMAC_ALE        0x54            // Alignment Error Register
39#define EMAC_DTE        0x58            // Deferred Transmission Frame Register
40#define EMAC_LCOL       0x5C            // Late Collision Register
41#define EMAC_ECOL       0x60            // Excessive Collision Register
42#define EMAC_CSE        0x64            // Carrier Sense Error Register
43#define EMAC_TUE        0x68            // Transmit Underrun Error Register
44#define EMAC_CDE        0x6C            // Code Error Register
45#define EMAC_ELR        0x70            // Excessive Length Error Register
46#define EMAC_RJB        0x74            // Receive Jabber Register
47#define EMAC_USF        0x78            // Undersize Frame Register
48#define EMAC_SQEE       0x7C            // SQE Test Error Register
49#define EMAC_DRFC       0x80            // Discarded RX Frame Register
50#define EMAC_HSH        0x90            // Hash Address High[63:32]
51#define EMAC_HSL        0x94            // Hash Address Low[31:0]
52#define EMAC_SA1L       0x98            // Specific Addr 1 Low, First 4 bytes
53#define EMAC_SA1H       0x9C            // Specific Addr 1 High, Last 2 bytes
54#define EMAC_SA2L       0xA0            // Specific Addr 2 Low, First 4 bytes
55#define EMAC_SA2H       0xA4            // Specific Addr 2 High, Last 2 bytes
56#define EMAC_SA3L       0xA8            // Specific Addr 3 Low, First 4 bytes
57#define EMAC_SA3H       0xAC            // Specific Addr 3 High, Last 2 bytes
58#define EMAC_SA4L       0xB0            // Specific Addr 4 Low, First 4 bytes
59#define EMAC_SA4H       0xB4            // Specific Addr 4 High, Last 2 bytesr
60
61// Control Register, EMAC_CTL, Offset 0x0
62#define EMAC_CTL_LB     BIT0            // 1 = Set Loopback output signal
63#define EMAC_CTL_LBL    BIT1            // 1 = Loopback local.
64#define EMAC_CTL_RE     BIT2            // 1 = Receive enable.
65#define EMAC_CTL_TE     BIT3            // 1 = Transmit enable.
66#define EMAC_CTL_MPE    BIT4            // 1 = Management port enable.
67#define EMAC_CTL_CSR    BIT5            // Write 1 to clear stats registers.
68#define EMAC_CTL_ISR    BIT6            // Write to increment stats registers
69#define EMAC_CTL_WES    BIT7            // 1 = Enable writing to stats regs
70#define EMAC_CTL_BP     BIT8            // 1 = Force collision on all RX frames
71
72// Configuration Register, EMAC_CFG, Offset 0x4
73#define EMAC_CFG_SPD    BIT0            // 1 = 10/100 Speed (not functional?)
74#define EMAC_CFG_FD     BIT1            // 1 = Full duplex.
75#define EMAC_CFG_BR     BIT2            // write 0
76#define EMAC_CFG_CAF    BIT4            // 1 = accept all frames
77#define EMAC_CFG_NBC    BIT5            // 1 = disable reception of bcast frms
78#define EMAC_CFG_MTI    BIT6            // 1 = Multicast hash enable
79#define EMAC_CFG_UNI    BIT7            // 1 = Unicast hash enable.
80#define EMAC_CFG_BIG    BIT8            // 1 = enable reception 1522 byte frms
81#define EMAC_CFG_EAE    BIT9            // write 0
82#define EMAC_CFG_CLK_8  (0 << 10)       // MII Clock = HCLK divided by 8
83#define EMAC_CFG_CLK_16 (1 << 10)       // MII Clock = HCLK divided by 16
84#define EMAC_CFG_CLK_32 (2 << 10)       // MII Clock = HCLK divided by 32
85#define EMAC_CFG_CLK_64 (3 << 10)       // MII Clock = HCLK divided by 64
86#define EMAC_CFG_RTY    BIT12           // Retry Test Mode - Must be 0
87#define EMAC_CFG_RMII   BIT13           // Reduced MII Mode Enable
88
89// Status Register, EMAC_SR, Offset 0x8
90#define EMAC_LINK       BIT0            // Link pin
91#define EMAC_MDIO       BIT1            // Real Time state of MDIO pin
92#define EMAC_IDLE       BIT2            // 0 = PHY Logic is idle
93
94// Transmit Control Register, EMAC_TCR, Offset 0x10
95#define EMAC_TCR_LEN(_x_)  ((_x_ & 0x7FF) <<  0)   // Tx frame len minus CRC
96#define EMAC_TCR_NCRC   BIT15                      // Do'nt append CRC on Tx
97
98// Transmit Status Register, EMAC_TSR, Offset 0x14
99#define EMAC_TSR_OVR    BIT0            // 1 = Transmit buffer overrun
100#define EMAC_TSR_COL    BIT1            // 1 = Collision occured
101#define EMAC_TSR_RLE    BIT2            // 1 = Retry lmimt exceeded
102#define EMAC_TSR_TXIDLE BIT3            // 1 = Transmitter is idle
103#define EMAC_TSR_BNQ    BIT4            // 1 = Transmit buffer not queued
104#define EMAC_TSR_COMP   BIT5            // 1 = Transmit complete
105#define EMAC_TSR_UND    BIT6            // 1 = Transmit underrun
106 
107// Receive Status Register, EMAC_RSR, Offset 0x20
108#define EMAC_RSR_BNA    BIT0            // 1 = Buffer not available
109#define EMAC_RSR_REC    BIT1            // 1 = Frame received
110#define EMAC_RSR_OVR    BIT2            // 1 = Receive overrun
111
112// Interrupt Status Register, EMAC_ISR, Offsen 0x24
113// Interrupt Enable Register, EMAC_IER, Offset 0x28
114// Interrupt Disable Register, EMAC_IDR, Offset 0x2c
115// Interrupt Mask Register, EMAC_IMR, Offset 0x30
116#define EMAC_INT_DONE   BIT0            // Phy management done
117#define EMAC_INT_RCOM   BIT1            // Receive complete
118#define EMAC_INT_RBNA   BIT2            // Receive buffer not available
119#define EMAC_INT_TOVR   BIT3            // Transmit buffer overrun
120#define EMAC_INT_TUND   BIT4            // Transmit buffer underrun
121#define EMAC_INT_RTRY   BIT5            // Transmit Retry limt
122#define EMAC_INT_TBRE   BIT6            // Transmit buffer register empty
123#define EMAC_INT_TCOM   BIT7            // Transmit complete
124#define EMAC_INT_TIDLE  BIT8            // Transmit idle
125#define EMAC_INT_LINK   BIT9            // Link pin changed value
126#define EMAC_INT_ROVR   BIT10           // Receive overrun
127#define EMAC_INT_ABT    BIT11           // Abort on DMA transfer
128
129// PHY Maintenance Register, EMAC_MAN, Offset 0x34
130#define EMAC_MAN_DATA(_x_)      ((_x_ & 0xFFFF) <<  0)  // PHY data register
131#define EMAC_MAN_CODE           (0x3 << 6)              // IEEE Code
132#define EMAC_MAN_REGA(_x_)      ((_x_ & 0x1F) << 18)    // PHY register address
133#define EMAC_MAN_PHYA(_x_)      ((_x_ & 0x1F) << 23)    // PHY address
134#define EMAC_MAN_WRITE          (0x1 << 28)             // Transfer is a write
135#define EMAC_MAN_READ           (0x2 << 28)             // Transfer is a read
136#define EMAC_MAN_HIGH           BIT30                   // Must be set
137
138// Bit assignments for Receive Buffer Descriptor
139// Address - Word 0
140#define RXBUF_ADD_BASE_MASK     0xfffffffc      // Base addr of the rx buf
141#define RXBUF_ADD_WRAP          BIT1            // set indicates last buf
142#define RXBUF_ADD_OWNED         BIT0            // 1 = SW owns the pointer
143
144// Status - Word 1
145#define RXBUF_STAT_BCAST        BIT31           // Global bcast addr detected
146#define RXBUF_STAT_MULTI        BIT30           // Multicast hash match
147#define RXBUF_STAT_UNI          BIT29           // Unicast hash match
148#define RXBUF_STAT_EXT          BIT28           // External address (optional)
149#define RXBUF_STAT_UNK          BIT27           // Unknown source address
150#define RXBUF_STAT_LOC1         BIT26           // Local address 1 match
151#define RXBUF_STAT_LOC2         BIT25           // Local address 2 match
152#define RXBUF_STAT_LOC3         BIT24           // Local address 3 match
153#define RXBUF_STAT_LOC4         BIT23           // Local address 4 match
154#define RXBUF_STAT_LEN_MASK     0x7ff           // Len of frame including FCS
155
156#endif /* __AT91RM9200_EMAC_H__ */
157
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