| 1 | /* |
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| 2 | * Atmel AT91RM9200 EMAC Register definitions |
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| 3 | * |
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| 4 | * Copyright (c) 2003 by Cogent Computer Systems |
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| 5 | * Written by Mike Kelly <mike@cogcomp.com> |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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| 9 | * |
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| 10 | * http://www.rtems.com/license/LICENSE. |
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| 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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| 14 | #ifndef __AT91RM9200_EMAC_H__ |
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| 15 | #define __AT91RM9200_EMAC_H__ |
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| 16 | |
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| 17 | #include <bits.h> |
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| 18 | |
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| 19 | /*Register offsets */ |
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| 20 | #define EMAC_CTL 0x00 /* Network Control Register */ |
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| 21 | #define EMAC_CFG 0x04 /* Network Configuration Register */ |
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| 22 | #define EMAC_SR 0x08 /* Network Status Register */ |
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| 23 | #define EMAC_TAR 0x0C /* Transmit Address Register */ |
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| 24 | #define EMAC_TCR 0x10 /* Transmit Control Register */ |
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| 25 | #define EMAC_TSR 0x14 /* Transmit Status Register */ |
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| 26 | #define EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */ |
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| 27 | #define EMAC_RSR 0x20 /* Receive Status Register */ |
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| 28 | #define EMAC_ISR 0x24 /* Interrupt Enable Register */ |
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| 29 | #define EMAC_IER 0x28 /* Interrupt Enable Register */ |
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| 30 | #define EMAC_IDR 0x2C /* Interrupt Disable Register */ |
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| 31 | #define EMAC_IMR 0x30 /* Interrupt Mask Register */ |
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| 32 | #define EMAC_MAN 0x34 /* PHY Maintenance Register */ |
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| 33 | #define EMAC_FRA 0x40 /* Frames Transmitted OK Register */ |
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| 34 | #define EMAC_SCOL 0x44 /* Single Collision Frame Register */ |
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| 35 | #define EMAC_MCOL 0x48 /* Multiple Collision Frame Register */ |
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| 36 | #define EMAC_OK 0x4C /* Frames Received OK Register */ |
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| 37 | #define EMAC_SEQE 0x50 /* Frame Check Sequence Error Register */ |
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| 38 | #define EMAC_ALE 0x54 /* Alignment Error Register */ |
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| 39 | #define EMAC_DTE 0x58 /* Deferred Transmission Frame Register */ |
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| 40 | #define EMAC_LCOL 0x5C /* Late Collision Register */ |
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| 41 | #define EMAC_ECOL 0x60 /* Excessive Collision Register */ |
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| 42 | #define EMAC_CSE 0x64 /* Carrier Sense Error Register */ |
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| 43 | #define EMAC_TUE 0x68 /* Transmit Underrun Error Register */ |
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| 44 | #define EMAC_CDE 0x6C /* Code Error Register */ |
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| 45 | #define EMAC_ELR 0x70 /* Excessive Length Error Register */ |
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| 46 | #define EMAC_RJB 0x74 /* Receive Jabber Register */ |
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| 47 | #define EMAC_USF 0x78 /* Undersize Frame Register */ |
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| 48 | #define EMAC_SQEE 0x7C /* SQE Test Error Register */ |
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| 49 | #define EMAC_DRFC 0x80 /* Discarded RX Frame Register */ |
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| 50 | #define EMAC_HSH 0x90 /* Hash Address High[63:32] */ |
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| 51 | #define EMAC_HSL 0x94 /* Hash Address Low[31:0] */ |
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| 52 | #define EMAC_SA1L 0x98 /* Specific Addr 1 Low, First 4 bytes */ |
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| 53 | #define EMAC_SA1H 0x9C /* Specific Addr 1 High, Last 2 bytes */ |
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| 54 | #define EMAC_SA2L 0xA0 /* Specific Addr 2 Low, First 4 bytes */ |
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| 55 | #define EMAC_SA2H 0xA4 /* Specific Addr 2 High, Last 2 bytes */ |
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| 56 | #define EMAC_SA3L 0xA8 /* Specific Addr 3 Low, First 4 bytes */ |
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| 57 | #define EMAC_SA3H 0xAC /* Specific Addr 3 High, Last 2 bytes */ |
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| 58 | #define EMAC_SA4L 0xB0 /* Specific Addr 4 Low, First 4 bytes */ |
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| 59 | #define EMAC_SA4H 0xB4 /* Specific Addr 4 High, Last 2 bytesr */ |
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| 60 | |
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| 61 | /* Control Register, EMAC_CTL, Offset 0x0 */ |
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| 62 | #define EMAC_CTL_LB BIT0 /* 1 = Set Loopback output signal */ |
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| 63 | #define EMAC_CTL_LBL BIT1 /* 1 = Loopback local. */ |
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| 64 | #define EMAC_CTL_RE BIT2 /* 1 = Receive enable. */ |
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| 65 | #define EMAC_CTL_TE BIT3 /* 1 = Transmit enable. */ |
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| 66 | #define EMAC_CTL_MPE BIT4 /* 1 = Management port enable. */ |
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| 67 | #define EMAC_CTL_CSR BIT5 /* Write 1 to clear stats registers. */ |
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| 68 | #define EMAC_CTL_ISR BIT6 /* Write to increment stats registers */ |
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| 69 | #define EMAC_CTL_WES BIT7 /* 1 = Enable writing to stats regs */ |
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| 70 | #define EMAC_CTL_BP BIT8 /* 1 = Force collision on all RX frames */ |
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| 71 | |
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| 72 | /* Configuration Register, EMAC_CFG, Offset 0x4 */ |
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| 73 | #define EMAC_CFG_SPD BIT0 /* 1 = 10/100 Speed (not functional?) */ |
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| 74 | #define EMAC_CFG_FD BIT1 /* 1 = Full duplex. */ |
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| 75 | #define EMAC_CFG_BR BIT2 /* write 0 */ |
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| 76 | #define EMAC_CFG_CAF BIT4 /* 1 = accept all frames */ |
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| 77 | #define EMAC_CFG_NBC BIT5 /* 1 = disable reception of bcast frms */ |
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| 78 | #define EMAC_CFG_MTI BIT6 /* 1 = Multicast hash enable */ |
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| 79 | #define EMAC_CFG_UNI BIT7 /* 1 = Unicast hash enable. */ |
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| 80 | #define EMAC_CFG_BIG BIT8 /* 1 = enable reception 1522 byte frms */ |
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| 81 | #define EMAC_CFG_EAE BIT9 /* write 0 */ |
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| 82 | #define EMAC_CFG_CLK_8 (0 << 10) /* MII Clock = HCLK divided by 8 */ |
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| 83 | #define EMAC_CFG_CLK_16 (1 << 10) /* MII Clock = HCLK divided by 16 */ |
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| 84 | #define EMAC_CFG_CLK_32 (2 << 10) /* MII Clock = HCLK divided by 32 */ |
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| 85 | #define EMAC_CFG_CLK_64 (3 << 10) /* MII Clock = HCLK divided by 64 */ |
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| 86 | #define EMAC_CFG_CLK_MASK (3 << 10) /* MII Clock mask */ |
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| 87 | #define EMAC_CFG_RTY BIT12 /* Retry Test Mode - Must be 0 */ |
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| 88 | #define EMAC_CFG_RMII BIT13 /* Reduced MII Mode Enable */ |
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| 89 | |
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| 90 | /* Status Register, EMAC_SR, Offset 0x8 */ |
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| 91 | #define EMAC_LINK BIT0 /* Link pin */ |
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| 92 | #define EMAC_MDIO BIT1 /* Real Time state of MDIO pin */ |
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| 93 | #define EMAC_IDLE BIT2 /* 0 = PHY Logic is idle */ |
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| 94 | |
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| 95 | /* Transmit Control Register, EMAC_TCR, Offset 0x10 */ |
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| 96 | #define EMAC_TCR_LEN(_x_) ((_x_ & 0x7FF) << 0) /* Tx frame len minus CRC */ |
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| 97 | #define EMAC_TCR_NCRC BIT15 /* Do'nt append CRC on Tx */ |
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| 98 | |
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| 99 | /* Transmit Status Register, EMAC_TSR, Offset 0x14 */ |
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| 100 | #define EMAC_TSR_OVR BIT0 /* 1 = Transmit buffer overrun */ |
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| 101 | #define EMAC_TSR_COL BIT1 /* 1 = Collision occured */ |
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| 102 | #define EMAC_TSR_RLE BIT2 /* 1 = Retry lmimt exceeded */ |
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| 103 | #define EMAC_TSR_TXIDLE BIT3 /* 1 = Transmitter is idle */ |
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| 104 | #define EMAC_TSR_BNQ BIT4 /* 1 = Transmit buffer not queued */ |
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| 105 | #define EMAC_TSR_COMP BIT5 /* 1 = Transmit complete */ |
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| 106 | #define EMAC_TSR_UND BIT6 /* 1 = Transmit underrun */ |
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| 107 | |
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| 108 | /* Receive Status Register, EMAC_RSR, Offset 0x20 */ |
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| 109 | #define EMAC_RSR_BNA BIT0 /* 1 = Buffer not available */ |
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| 110 | #define EMAC_RSR_REC BIT1 /* 1 = Frame received */ |
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| 111 | #define EMAC_RSR_OVR BIT2 /* 1 = Receive overrun */ |
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| 112 | |
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| 113 | /* |
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| 114 | * Interrupt Status Register, EMAC_ISR, Offsen 0x24 |
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| 115 | * Interrupt Enable Register, EMAC_IER, Offset 0x28 |
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| 116 | * Interrupt Disable Register, EMAC_IDR, Offset 0x2c |
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| 117 | * Interrupt Mask Register, EMAC_IMR, Offset 0x30 |
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| 118 | */ |
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| 119 | #define EMAC_INT_DONE BIT0 /* Phy management done */ |
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| 120 | #define EMAC_INT_RCOM BIT1 /* Receive complete */ |
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| 121 | #define EMAC_INT_RBNA BIT2 /* Receive buffer not available */ |
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| 122 | #define EMAC_INT_TOVR BIT3 /* Transmit buffer overrun */ |
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| 123 | #define EMAC_INT_TUND BIT4 /* Transmit buffer underrun */ |
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| 124 | #define EMAC_INT_RTRY BIT5 /* Transmit Retry limt */ |
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| 125 | #define EMAC_INT_TBRE BIT6 /* Transmit buffer register empty */ |
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| 126 | #define EMAC_INT_TCOM BIT7 /* Transmit complete */ |
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| 127 | #define EMAC_INT_TIDLE BIT8 /* Transmit idle */ |
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| 128 | #define EMAC_INT_LINK BIT9 /* Link pin changed value */ |
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| 129 | #define EMAC_INT_ROVR BIT10 /* Receive overrun */ |
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| 130 | #define EMAC_INT_ABT BIT11 /* Abort on DMA transfer */ |
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| 131 | |
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| 132 | /* PHY Maintenance Register, EMAC_MAN, Offset 0x34 */ |
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| 133 | #define EMAC_MAN_DATA(_x_) ((_x_ & 0xFFFF) << 0)/* PHY data register */ |
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| 134 | #define EMAC_MAN_CODE (0x2 << 16) /* IEEE Code */ |
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| 135 | #define EMAC_MAN_REGA(_x_) ((_x_ & 0x1F) << 18) /* PHY register address */ |
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| 136 | #define EMAC_MAN_PHYA(_x_) ((_x_ & 0x1F) << 23) /* PHY address */ |
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| 137 | #define EMAC_MAN_WRITE (0x1 << 28) /* Transfer is a write */ |
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| 138 | #define EMAC_MAN_READ (0x2 << 28) /* Transfer is a read */ |
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| 139 | #define EMAC_MAN_HIGH BIT30 /* Must be set */ |
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| 140 | #define EMAC_MAN_LOW BIT31 |
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| 141 | |
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| 142 | /* |
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| 143 | * Bit assignments for Receive Buffer Descriptor |
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| 144 | * Address - Word 0 |
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| 145 | */ |
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| 146 | #define RXBUF_ADD_BASE_MASK 0xfffffffc /* Base addr of the rx buf */ |
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| 147 | #define RXBUF_ADD_WRAP BIT1 /* set indicates last buf */ |
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| 148 | #define RXBUF_ADD_OWNED BIT0 /* 1 = SW owns the pointer */ |
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| 149 | |
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| 150 | /* Status - Word 1 */ |
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| 151 | #define RXBUF_STAT_BCAST BIT31 /* Global bcast addr detected */ |
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| 152 | #define RXBUF_STAT_MULTI BIT30 /* Multicast hash match */ |
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| 153 | #define RXBUF_STAT_UNI BIT29 /* Unicast hash match */ |
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| 154 | #define RXBUF_STAT_EXT BIT28 /* External address (optional) */ |
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| 155 | #define RXBUF_STAT_UNK BIT27 /* Unknown source address */ |
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| 156 | #define RXBUF_STAT_LOC1 BIT26 /* Local address 1 match */ |
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| 157 | #define RXBUF_STAT_LOC2 BIT25 /* Local address 2 match */ |
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| 158 | #define RXBUF_STAT_LOC3 BIT24 /* Local address 3 match */ |
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| 159 | #define RXBUF_STAT_LOC4 BIT23 /* Local address 4 match */ |
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| 160 | #define RXBUF_STAT_LEN_MASK 0x7ff /* Len of frame including FCS */ |
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| 161 | |
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| 162 | #endif /* __AT91RM9200_EMAC_H__ */ |
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| 163 | |
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