1 | /* |
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2 | * Atmel AT91RM9200_DBGU Register definitions |
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3 | * |
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4 | * Copyright (c) 2003 by Cogent Computer Systems |
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5 | * Written by Mike Kelly <mike@cogcomp.com> |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | */ |
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11 | #ifndef __AT91RM9200_DBGU_H__ |
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12 | #define __AT91RM9200_DBGU_H__ |
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13 | |
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14 | #include "bits.h" |
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15 | |
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16 | /* Register Offsets */ |
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17 | #define DBGU_CR 0x00 /* Control Register */ |
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18 | #define DBGU_MR 0x04 /* Mode Register */ |
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19 | #define DBGU_IER 0x08 /* Interrupt Enable Register */ |
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20 | #define DBGU_IDR 0x0C /* Interrupt Disable Register */ |
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21 | #define DBGU_IMR 0x10 /* Interrupt Mask Register */ |
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22 | #define DBGU_SR 0x14 /* Channel Status Register */ |
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23 | #define DBGU_RHR 0x18 /* Receiver Holding Register */ |
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24 | #define DBGU_THR 0x1C /* Transmitter Holding Register */ |
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25 | #define DBGU_BRGR 0x20 /* Baud Rate Generator Register */ |
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26 | #define DBGU_C1R 0x40 /* Chip ID1 Register */ |
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27 | #define DBGU_C2R 0x44 /* Chip ID2 Register */ |
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28 | #define DBGU_FNTR 0x48 /* Force NTRST Register */ |
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29 | |
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30 | /* Bit Defines */ |
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31 | /* Control Register, DBGU_CR, Offset 0x00 */ |
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32 | #define DBGU_CR_RSTRX BIT2 /* 1 = Reset and disable receiver */ |
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33 | #define DBGU_CR_RSTTX BIT3 /* 1 = Reset and disable transmitter */ |
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34 | #define DBGU_CR_RXEN BIT4 /* 1 = Receiver enable */ |
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35 | #define DBGU_CR_RXDIS BIT5 /* 1 = Receiver disable */ |
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36 | #define DBGU_CR_TXEN BIT6 /* 1 = Transmitter enable */ |
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37 | #define DBGU_CR_TXDIS BIT7 /* 1 = Transmitter disable */ |
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38 | #define DBGU_CR_RSTSTA BIT8 /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */ |
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39 | |
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40 | /* Mode Register. DBGU_MR. Offset 0x04 */ |
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41 | #define DBGU_MR_PAR_EVEN (0x0 << 9) /* Even Parity */ |
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42 | #define DBGU_MR_PAR_ODD (0x1 << 9) /* Odd Parity */ |
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43 | #define DBGU_MR_PAR_SPACE (0x2 << 9) /* Parity forced to 0 (Space) */ |
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44 | #define DBGU_MR_PAR_MARK (0x3 << 9) /* Parity forced to 1 (Mark) */ |
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45 | #define DBGU_MR_PAR_NONE (0x4 << 9) /* No Parity */ |
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46 | #define DBGU_MR_PAR_MDROP (0x6 << 9) /* Multi-drop mode */ |
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47 | #define DBGU_MR_CHMODE_NORM (0x0 << 14) /* Normal Mode */ |
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48 | #define DBGU_MR_CHMODE_AUTO (0x1 << 14) /* Auto Echo: RXD drives TXD */ |
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49 | #define DBGU_MR_CHMODE_LOC (0x2 << 14) /* Local Loopback: TXD drives RXD */ |
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50 | #define DBGU_MR_CHMODE_REM (0x3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */ |
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51 | |
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52 | /* Interrupt Enable Register, DBGU_IER, Offset 0x08 */ |
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53 | /* Interrupt Disable Register, DBGU_IDR, Offset 0x0C */ |
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54 | /* Interrupt Mask Register, DBGU_IMR, Offset 0x10 */ |
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55 | /* Channel Status Register, DBGU_SR, Offset 0x14 */ |
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56 | #define DBGU_INT_RXRDY BIT0 /* RXRDY Interrupt */ |
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57 | #define DBGU_INT_TXRDY BIT1 /* TXRDY Interrupt */ |
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58 | #define DBGU_INT_ENDRX BIT3 /* End of Receive Transfer Interrupt */ |
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59 | /*efine DBGU_INT_ENDTX BIT4 /* End of Transmit Interrupt */ |
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60 | #define DBGU_INT_OVRE BIT5 /* Overrun Interrupt */ |
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61 | #define DBGU_INT_FRAME BIT6 /* Framing Error Interrupt */ |
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62 | #define DBGU_INT_PARE BIT7 /* Parity Error Interrupt */ |
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63 | #define DBGU_INT_TXEMPTY BIT9 /* TXEMPTY Interrupt */ |
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64 | #define DBGU_INT_TXBUFE BIT11 /* TXBUFE Interrupt */ |
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65 | #define DBGU_INT_RXBUFF BIT12 /* RXBUFF Interrupt */ |
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66 | #define DBGU_INT_COMM_TX BIT30 /* COMM_TX Interrupt */ |
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67 | #define DBGU_INT_COMM_RX BIT31 /* COMM_RX Interrupt */ |
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68 | #define DBGU_INT_ALL 0xC0001AFB /* all assigned bits */ |
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69 | |
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70 | /* FORCE_NTRST Register, DBGU_FNTR, Offset 0x48 */ |
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71 | #define DBGU_FNTR_NTRST BIT0 /* 1 = Force NTRST low in JTAG */ |
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72 | |
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73 | typedef struct { |
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74 | volatile uint32_t cr; |
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75 | volatile uint32_t mr; |
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76 | volatile uint32_t ier; |
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77 | volatile uint32_t idr; |
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78 | volatile uint32_t imr; |
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79 | volatile uint32_t sr; |
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80 | volatile uint32_t rhr; |
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81 | volatile uint32_t thr; |
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82 | volatile uint32_t brgr; |
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83 | volatile uint32_t _res0[7]; |
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84 | volatile uint32_t cidr; |
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85 | volatile uint32_t exid; |
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86 | volatile uint32_t fnr; |
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87 | } at91rm9200_dbgu_regs_t; |
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88 | |
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89 | #endif /* __AT91RM9200_DBGU_H__ */ |
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