source: rtems/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h @ 359e537

4.104.115
Last change on this file since 359e537 was 359e537, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/30/09 at 05:09:41

Whitespace removal.
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1/*
2 * Atmel AT91RM9200_DBGU Register definitions
3 *
4 * Copyright (c) 2003 by Cogent Computer Systems
5 * Written by Mike Kelly <mike@cogcomp.com>
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id$
13 */
14#ifndef __AT91RM9200_DBGU_H__
15#define __AT91RM9200_DBGU_H__
16
17#include "bits.h"
18
19/* Register Offsets */
20#define DBGU_CR         0x00            /* Control Register */
21#define DBGU_MR         0x04            /* Mode Register */
22#define DBGU_IER        0x08            /* Interrupt Enable Register */
23#define DBGU_IDR        0x0C            /* Interrupt Disable Register */
24#define DBGU_IMR        0x10            /* Interrupt Mask Register */
25#define DBGU_SR         0x14            /* Channel Status Register */
26#define DBGU_RHR        0x18            /* Receiver Holding Register */
27#define DBGU_THR        0x1C            /* Transmitter Holding Register */
28#define DBGU_BRGR       0x20            /* Baud Rate Generator Register */
29#define DBGU_C1R        0x40            /* Chip ID1 Register */
30#define DBGU_C2R        0x44            /* Chip ID2 Register */
31#define DBGU_FNTR       0x48            /* Force NTRST Register */
32
33/* Bit Defines */
34/* Control Register, DBGU_CR, Offset 0x00 */
35#define DBGU_CR_RSTRX   BIT2            /* 1 = Reset and disable receiver */
36#define DBGU_CR_RSTTX   BIT3            /* 1 = Reset and disable transmitter */
37#define DBGU_CR_RXEN    BIT4            /* 1 = Receiver enable */
38#define DBGU_CR_RXDIS   BIT5            /* 1 = Receiver disable */
39#define DBGU_CR_TXEN    BIT6            /* 1 = Transmitter enable */
40#define DBGU_CR_TXDIS   BIT7            /* 1 = Transmitter disable */
41#define DBGU_CR_RSTSTA  BIT8            /* 1 = Reset PARE, FRAME and OVRE in DBGU_SR. */
42
43/* Mode Register. DBGU_MR. Offset 0x04 */
44#define DBGU_MR_PAR_EVEN    (0x0 <<  9) /* Even Parity */
45#define DBGU_MR_PAR_ODD     (0x1 <<  9) /* Odd Parity */
46#define DBGU_MR_PAR_SPACE   (0x2 <<  9) /* Parity forced to 0 (Space) */
47#define DBGU_MR_PAR_MARK    (0x3 <<  9) /* Parity forced to 1 (Mark) */
48#define DBGU_MR_PAR_NONE    (0x4 <<  9) /* No Parity */
49#define DBGU_MR_PAR_MDROP   (0x6 <<  9) /* Multi-drop mode */
50#define DBGU_MR_CHMODE_NORM (0x0 << 14) /* Normal Mode */
51#define DBGU_MR_CHMODE_AUTO (0x1 << 14) /* Auto Echo: RXD drives TXD */
52#define DBGU_MR_CHMODE_LOC  (0x2 << 14) /* Local Loopback: TXD drives RXD */
53#define DBGU_MR_CHMODE_REM  (0x3 << 14) /* Remote Loopback: RXD pin connected to TXD pin. */
54
55/* Interrupt Enable Register, DBGU_IER, Offset 0x08 */
56/* Interrupt Disable Register, DBGU_IDR, Offset 0x0C */
57/* Interrupt Mask Register, DBGU_IMR, Offset 0x10 */
58/* Channel Status Register, DBGU_SR, Offset 0x14 */
59#define DBGU_INT_RXRDY      BIT0        /* RXRDY Interrupt */
60#define DBGU_INT_TXRDY      BIT1        /* TXRDY Interrupt */
61#define DBGU_INT_ENDRX      BIT3        /* End of Receive Transfer Interrupt */
62/*efine DBGU_INT_ENDTX      BIT4        /* End of Transmit Interrupt */
63#define DBGU_INT_OVRE       BIT5        /* Overrun Interrupt */
64#define DBGU_INT_FRAME      BIT6        /* Framing Error Interrupt */
65#define DBGU_INT_PARE       BIT7        /* Parity Error Interrupt */
66#define DBGU_INT_TXEMPTY    BIT9        /* TXEMPTY Interrupt */
67#define DBGU_INT_TXBUFE     BIT11       /* TXBUFE Interrupt */
68#define DBGU_INT_RXBUFF     BIT12       /* RXBUFF Interrupt */
69#define DBGU_INT_COMM_TX    BIT30       /* COMM_TX Interrupt */
70#define DBGU_INT_COMM_RX    BIT31       /* COMM_RX Interrupt */
71#define DBGU_INT_ALL        0xC0001AFB  /* all assigned bits */
72
73/* FORCE_NTRST Register, DBGU_FNTR, Offset 0x48 */
74#define DBGU_FNTR_NTRST         BIT0    /* 1 = Force NTRST low in JTAG */
75
76typedef struct {
77    volatile uint32_t cr;
78    volatile uint32_t mr;
79    volatile uint32_t ier;
80    volatile uint32_t idr;
81    volatile uint32_t imr;
82    volatile uint32_t sr;
83    volatile uint32_t rhr;
84    volatile uint32_t thr;
85    volatile uint32_t brgr;
86    volatile uint32_t _res0[7];
87    volatile uint32_t cidr;
88    volatile uint32_t exid;
89    volatile uint32_t fnr;
90} at91rm9200_dbgu_regs_t;
91
92#endif /* __AT91RM9200_DBGU_H__ */
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