| 1 | /* |
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| 2 | * Atmel AT91RM9200 Register definitions, used in KIT637_V6 (CSB637) |
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| 3 | * |
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| 4 | * Copyright (c) 2003 by Cogent Computer Systems |
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| 5 | * Written by Mike Kelly <mike@cogcomp.com> |
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| 6 | * |
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| 7 | * Modified by Fernando Nicodemos <fgnicodemos@terra.com.br> |
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| 8 | * from NCB - Sistemas Embarcados Ltda. (Brazil) |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * |
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| 13 | * http://www.rtems.com/license/LICENSE. |
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| 14 | * |
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| 15 | * $Id$ |
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| 16 | */ |
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| 17 | |
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| 18 | |
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| 19 | #ifndef __AT91RM9200_H__ |
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| 20 | #define __AT91RM9200_H__ |
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| 21 | |
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| 22 | #include "bits.h" |
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| 23 | |
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| 24 | typedef volatile unsigned long vulong; |
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| 25 | |
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| 26 | /* Source Mode Register - 32 of them */ |
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| 27 | #define AIC_SMR_BASE 0xFFFFF000 |
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| 28 | #define AIC_SMR_REG(_x_) *(vulong *)(AIC_SMR_BASE + (_x_ & 0x7c)) |
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| 29 | |
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| 30 | /* Source Vector Register - 32 of them */ |
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| 31 | #define AIC_SVR_BASE 0xFFFFF080 |
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| 32 | #define AIC_SVR_REG(_x_) *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c)) |
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| 33 | |
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| 34 | /* Control Register - 32 of them */ |
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| 35 | #define AIC_CTL_BASE 0xFFFFF100 |
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| 36 | #define AIC_CTL_REG(_x_) *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f)) |
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| 37 | |
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| 38 | /* Register Offsets */ |
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| 39 | /* offsets from AIC_SMR_BASE and AIC_SVR_BASE */ |
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| 40 | #define AIC_SMR_FIQ 0x00 /* Advanced Interrupt Controller FIQ */ |
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| 41 | #define AIC_SMR_SYSIRQ 0x04 /* Advanced Interrupt Controller SYSIRQ */ |
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| 42 | #define AIC_SMR_PIOA 0x08 /* Parallel I/O Controller A */ |
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| 43 | #define AIC_SMR_PIOB 0x0c /* Parallel I/O Controller B */ |
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| 44 | #define AIC_SMR_PIOC 0x10 /* Parallel I/O Controller C */ |
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| 45 | #define AIC_SMR_PIOD 0x14 /* Parallel I/O Controller D */ |
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| 46 | #define AIC_SMR_US0 0x18 /* USART 0 */ |
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| 47 | #define AIC_SMR_US1 0x1c /* USART 1 */ |
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| 48 | #define AIC_SMR_US2 0x20 /* USART 2 */ |
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| 49 | #define AIC_SMR_US3 0x24 /* USART 3 */ |
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| 50 | #define AIC_SMR_MCI 0x28 /* Multimedia Card Interface */ |
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| 51 | #define AIC_SMR_UDP 0x2c /* USB Device Port */ |
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| 52 | #define AIC_SMR_TWI 0x30 /* Two-wire Interface */ |
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| 53 | #define AIC_SMR_SPI 0x34 /* Serial Peripheral Interface */ |
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| 54 | #define AIC_SMR_SSC0 0x38 /* Synchronous Serial Controller 0 */ |
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| 55 | #define AIC_SMR_SSC1 0x3c /* Synchronous Serial Controller 1 */ |
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| 56 | #define AIC_SMR_SSC2 0x40 /* Synchronous Serial Controller 2 */ |
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| 57 | #define AIC_SMR_TC0 0x44 /* Timer/Counter 0 */ |
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| 58 | #define AIC_SMR_TC1 0x48 /* Timer/Counter 1 */ |
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| 59 | #define AIC_SMR_TC2 0x4c /* Timer/Counter 2 */ |
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| 60 | #define AIC_SMR_TC3 0x50 /* Timer/Counter 3 */ |
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| 61 | #define AIC_SMR_TC4 0x54 /* Timer/Counter 4 */ |
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| 62 | #define AIC_SMR_TC5 0x58 /* Timer/Counter 5 */ |
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| 63 | #define AIC_SMR_UHP 0x5c /* USB Host Port */ |
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| 64 | #define AIC_SMR_EMAC 0x60 /* Ethernet MAC */ |
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| 65 | #define AIC_SMR_IRQ0 0x64 /* Advanced Interrupt Controller IRQ0 */ |
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| 66 | #define AIC_SMR_IRQ1 0x68 /* Advanced Interrupt Controller IRQ1 */ |
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| 67 | #define AIC_SMR_IRQ2 0x6c /* Advanced Interrupt Controller IRQ2 */ |
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| 68 | #define AIC_SMR_IRQ3 0x70 /* Advanced Interrupt Controller IRQ3 */ |
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| 69 | #define AIC_SMR_IRQ4 0x74 /* Advanced Interrupt Controller IRQ4 */ |
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| 70 | #define AIC_SMR_IRQ5 0x78 /* Advanced Interrupt Controller IRQ5 */ |
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| 71 | #define AIC_SMR_IRQ6 0x7c /* Advanced Interrupt Controller IRQ6 */ |
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| 72 | |
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| 73 | /* from AIC_CTL_BASE */ |
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| 74 | #define AIC_IVR 0x00 /* IRQ Vector Register */ |
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| 75 | #define AIC_FVR 0x04 /* FIQ Vector Register */ |
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| 76 | #define AIC_ISR 0x08 /* Interrupt Status Register */ |
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| 77 | #define AIC_IPR 0x0C /* Interrupt Pending Register */ |
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| 78 | #define AIC_IMR 0x10 /* Interrupt Mask Register */ |
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| 79 | #define AIC_CISR 0x14 /* Core Interrupt Status Register */ |
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| 80 | #define AIC_IECR 0x20 /* Interrupt Enable Command Register */ |
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| 81 | #define AIC_IDCR 0x24 /* Interrupt Disable Command Register */ |
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| 82 | #define AIC_ICCR 0x28 /* Interrupt Clear Command Register */ |
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| 83 | #define AIC_ISCR 0x2C /* Interrupt Set Command Register */ |
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| 84 | #define AIC_EOICR 0x30 /* End of Interrupt Command Register */ |
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| 85 | #define AIC_SPU 0x34 /* Spurious Vector Register */ |
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| 86 | #define AIC_DCR 0x38 /* Debug Control Register (Protect) */ |
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| 87 | #define AIC_FFER 0x40 /* Fast Forcing Enable Register */ |
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| 88 | #define AIC_FFDR 0x44 /* Fast Forcing Disable Register */ |
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| 89 | #define AIC_FFSR 0x48 /* Fast Forcing Status Register */ |
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| 90 | |
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| 91 | /* Bit Defines */ |
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| 92 | /* AIC_ISR - Interrupt Status Register */ |
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| 93 | #define AIC_ISR_IRQID_MASK 0x1f /* current interrupt ID */ |
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| 94 | |
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| 95 | /* AIC_CISR - Core Interrupt Status Register */ |
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| 96 | #define AIC_CISR_IRQ BIT1 /* 1 = Core IRQ is active */ |
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| 97 | #define AIC_CISR_FIQ BIT0 /* 1 = Core FIQ is active */ |
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| 98 | |
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| 99 | /* AIC_DCR - Debug Control Register (Protect) */ |
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| 100 | #define AIC_DCR_GMSK BIT1 /* 0 = AIC controls IRQ and FIQ */ |
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| 101 | #define AIC_DCR_PROT BIT0 /* 1 = enable protection mode */ |
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| 102 | |
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| 103 | /* AIC_SMR */ |
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| 104 | #define AIC_SMR_PRIOR(_x_) ((_x_ & 0x07) << 0) |
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| 105 | #define AIC_SMR_SRC_LVL_LOW (0 << 5) /* Are these right? docs don't say which is high/low */ |
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| 106 | #define AIC_SMR_SRC_EDGE_LOW (1 << 5) |
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| 107 | #define AIC_SMR_SRC_LVL_HI (2 << 5) |
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| 108 | #define AIC_SMR_SRC_EDGE_HI (3 << 5) |
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| 109 | |
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| 110 | /**************************************************************************/ |
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| 111 | /* Debug Unit */ |
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| 112 | /**************************************************************************/ |
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| 113 | #define DBGU_BASE 0xFFFFF200 |
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| 114 | #define DBGU_REG(_x_) *(vulong *)(DBGU_BASE + _x_) |
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| 115 | |
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| 116 | /* Register Offsets */ |
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| 117 | #define DBGU_CR 0x00 /* Control Register */ |
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| 118 | #define DBGU_MR 0x04 /* Mode Register */ |
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| 119 | #define DBGU_IER 0x08 /* Interrupt Enable Register */ |
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| 120 | #define DBGU_IDR 0x0C /* Interrupt Disable Register */ |
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| 121 | #define DBGU_IMR 0x10 /* Interrupt Mask Register */ |
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| 122 | #define DBGU_CSR 0x14 /* Channel Status Register */ |
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| 123 | #define DBGU_RHR 0x18 /* Receiver Holding Register */ |
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| 124 | #define DBGU_THR 0x1C /* Transmitter Holding Register */ |
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| 125 | #define DBGU_BRGR 0x20 /* Baud Rate Generator Register */ |
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| 126 | #define DBGU_C1R 0x40 /* Chip ID1 Register */ |
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| 127 | #define DBGU_C2R 0x44 /* Chip ID2 Register */ |
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| 128 | #define DBGU_FNTR 0x48 /* Force NTRST Register */ |
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| 129 | |
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| 130 | /**************************************************************************/ |
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| 131 | /* USART 0-3 */ |
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| 132 | /**************************************************************************/ |
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| 133 | #define USART0_BASE 0xFFFC0000 |
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| 134 | #define USART1_BASE 0xFFFC4000 |
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| 135 | #define USART2_BASE 0xFFFC8000 |
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| 136 | #define USART3_BASE 0xFFFCC000 |
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| 137 | /* |
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| 138 | * WARNING: The USART3_BASE at the AT91RM9200 Manual is wrong!!! |
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| 139 | * Manual revision: Rev. 1768H-ATARMâ16-Jun-09 |
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| 140 | * USART3_BASE is NOT 0xFFECC000 |
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| 141 | */ |
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| 142 | |
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| 143 | /****************/ |
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| 144 | /* System Timer */ |
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| 145 | /****************/ |
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| 146 | #define ST_BASE 0xFFFFFD00 |
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| 147 | #define ST_REG(_x_) *(vulong *)(ST_BASE + _x_) |
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| 148 | |
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| 149 | /* Register Offsets */ |
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| 150 | #define ST_CR 0x00 /* Control Register */ |
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| 151 | #define ST_PIMR 0x04 /* Period Interval Mode Register */ |
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| 152 | #define ST_WDMR 0x08 /* Watchdog Mode Register */ |
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| 153 | #define ST_RTMR 0x0C /* Real-time Mode Register */ |
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| 154 | #define ST_SR 0x10 /* Status Register */ |
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| 155 | #define ST_IER 0x14 /* Interrupt Enable Register */ |
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| 156 | #define ST_IDR 0x18 /* Interrupt Disable Register */ |
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| 157 | #define ST_IMR 0x1C /* Interrupt Mask Register */ |
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| 158 | #define ST_RTAR 0x20 /* Real-time Alarm Register */ |
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| 159 | #define ST_CRTR 0x24 /* Current Real-time Register */ |
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| 160 | |
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| 161 | /* Bit Defines */ |
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| 162 | /* ST_CR - Control Register */ |
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| 163 | #define ST_CR_WDRST BIT0 /* write 1 to reload WD counter */ |
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| 164 | |
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| 165 | /* ST_PIMR - Period Interval Mode Register */ |
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| 166 | #define ST_PIMR_PIV_MASK 0x0000ffff |
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| 167 | |
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| 168 | /* ST_WDMR - Watchdog Mode Register */ |
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| 169 | #define ST_WDMR_EXTEN BIT17 /* WDOVF is not implemented on AT91RM9200 */ |
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| 170 | #define ST_WDMR_RSTEN BIT16 /* 1 = reset the AT91RM9200 when WD overflows */ |
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| 171 | #define ST_WDMR_WDV_MASK 0x0000ffff /* WD counter is in the lower 16-bits */ |
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| 172 | |
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| 173 | /* ST_RTMR - Real-time Mode Register */ |
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| 174 | #define ST_RTMR_RTPRES_MASK 0x0000ffff /* Real-Time Prescaler */ |
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| 175 | |
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| 176 | /* ST_SR - Status Register - Read Only */ |
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| 177 | /* ST_IER - Interrupt Enable Register - Write Only */ |
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| 178 | /* ST_IDR - Interrupt Disable Register - Write Only */ |
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| 179 | /* ST_IMR - Interrupt Mask Register - Read Only */ |
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| 180 | #define ST_SR_ALMS BIT3 |
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| 181 | #define ST_SR_RTTINC BIT2 |
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| 182 | #define ST_SR_WDOVF BIT1 |
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| 183 | #define ST_SR_PITS BIT0 |
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| 184 | |
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| 185 | /* ST_RTAR - Real-time Alarm Register */ |
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| 186 | #define ST_RTAR_ALMV_MASK 0x000fffff |
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| 187 | |
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| 188 | /* ST_CRTR - Current Real-time Register */ |
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| 189 | #define ST_CRTR_CRTV_MASK 0x000fffff |
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| 190 | |
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| 191 | |
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| 192 | /************************************************************************** |
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| 193 | * Peripheral Data Control (DMA) |
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| 194 | * Note that each of the following peripherals has it's own |
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| 195 | * set of these registers starting at offset 0x100 from it's |
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| 196 | * base address: DBGU, SPI, USART and SSC |
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| 197 | * To access the DMA for a peripheral, use the macro for that |
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| 198 | * peripheral but with these register offsets |
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| 199 | **************************************************************************/ |
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| 200 | /* Register Offsets */ |
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| 201 | #define PDC_RPR 0x100 /* Receive Pointer Register */ |
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| 202 | #define PDC_RCR 0x104 /* Receive Counter Register */ |
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| 203 | #define PDC_TPR 0x108 /* Transmit Pointer Register */ |
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| 204 | #define PDC_TCR 0x10c /* Transmit Counter Register */ |
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| 205 | #define PDC_RNPR 0x110 /* Receive Next Pointer Register */ |
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| 206 | #define PDC_RNCR 0x114 /* Receive Next Counter Register */ |
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| 207 | #define PDC_TNPR 0x118 /* Transmit Next Pointer Register */ |
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| 208 | #define PDC_TNCR 0x11c /* Transmit Next Counter Register */ |
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| 209 | #define PDC_PTCR 0x120 /* PDC Transfer Control Register */ |
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| 210 | #define PDC_PTSR 0x124 /* PDC Transfer Status Register */ |
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| 211 | |
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| 212 | /************************************************************************** |
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| 213 | * Parallel I/O Unit |
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| 214 | * There are four PIO blocks - A, B, C and D. They all have the |
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| 215 | * same register set, but different base addresses |
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| 216 | **************************************************************************/ |
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| 217 | /* Port A */ |
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| 218 | #define PIOA_BASE 0xFFFFF400 |
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| 219 | #define PIOA_REG(_x_) *(vulong *)(PIOA_BASE + _x_) |
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| 220 | |
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| 221 | /* Port B */ |
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| 222 | #define PIOB_BASE 0xFFFFF600 |
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| 223 | #define PIOB_REG(_x_) *(vulong *)(PIOB_BASE + _x_) |
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| 224 | |
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| 225 | /* Port C */ |
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| 226 | #define PIOC_BASE 0xFFFFF800 |
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| 227 | #define PIOC_REG(_x_) *(vulong *)(PIOC_BASE + _x_) |
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| 228 | |
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| 229 | /* Port D */ |
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| 230 | #define PIOD_BASE 0xFFFFFA00 |
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| 231 | #define PIOD_REG(_x_) *(vulong *)(PIOD_BASE + _x_) |
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| 232 | |
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| 233 | /************************************************************************** |
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| 234 | * Power Management and Clock Control |
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| 235 | *************************************************************************/ |
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| 236 | #define PMC_BASE 0xFFFFFC00 |
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| 237 | #define PMC_REG(_x_) *(vulong *)(PMC_BASE + _x_) |
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| 238 | |
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| 239 | /************************************************************************** |
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| 240 | * MAC Unit |
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| 241 | *************************************************************************/ |
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| 242 | #define EMAC_BASE 0xFFFBC000 |
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| 243 | #define EMAC_REG(_x_) *(vulong *)(EMAC_BASE + _x_) |
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| 244 | |
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| 245 | /************************************************************************** |
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| 246 | * Timer/Counter Unit |
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| 247 | **************************************************************************/ |
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| 248 | #define TC_BASE 0xFFFA0000 |
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| 249 | #define TC_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_) |
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| 250 | #define TC_TC0_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_) |
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| 251 | #define TC_TC1_REG(_x_) *(vulong *)(TC_BASE + 0x40 + _x_) |
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| 252 | #define TC_TC2_REG(_x_) *(vulong *)(TC_BASE + 0x80 + _x_) |
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| 253 | |
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| 254 | /* Offsets from TC_TC?_REG */ |
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| 255 | #define TC_CCR 0x00 /* Channel Control Register */ |
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| 256 | #define TC_CMR 0x04 /* Channel Mode Register */ |
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| 257 | #define TC_CV 0x10 /* Counter Value */ |
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| 258 | #define TC_RA 0x14 /* Register A */ |
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| 259 | #define TC_RB 0x18 /* Register B */ |
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| 260 | #define TC_RC 0x1C /* Register C */ |
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| 261 | #define TC_SR 0x20 /* Status Register */ |
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| 262 | #define TC_IER 0x24 /* Interrupt Enable Register */ |
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| 263 | #define TC_IDR 0x28 /* Interrupt Disable Register */ |
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| 264 | #define TC_IMR 0x2C /* Interrupt Mask Register */ |
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| 265 | |
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| 266 | /* Offsets from TC_BASE */ |
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| 267 | #define TC_BCR 0xc0 /* Channel Control Register */ |
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| 268 | #define TC_BMR 0xc4 /* Channel Control Register */ |
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| 269 | |
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| 270 | /* Block control register */ |
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| 271 | #define TC_BCR_SYNC BIT1 /* Set to syncronize channels */ |
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| 272 | |
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| 273 | /* Block mode register */ |
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| 274 | #define TC_BMR_TC0(_x_) ((_x_ & 0x3) << 0) /* TC0 clock source */ |
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| 275 | #define TC_BMR_TC1(_x_) ((_x_ & 0x3) << 2) /* TC1 clock source */ |
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| 276 | #define TC_BMR_TC2(_x_) ((_x_ & 0x3) << 4) /* TC2 clock source */ |
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| 277 | |
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| 278 | /* Channel Control register */ |
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| 279 | #define TC_CCR_CLKEN BIT0 /* Enable clock */ |
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| 280 | #define TC_CCR_CLKDIS BIT1 /* Disable clock */ |
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| 281 | #define TC_CCR_SWTRG BIT2 /* Software trigger command */ |
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| 282 | |
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| 283 | /* Channel mode register */ |
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| 284 | #define TC_CMR_TCCLKS(_x_) ((_x_ & 0x7) << 0) /* Clock source */ |
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| 285 | #define TC_CMR_CLKI BIT3 /* Clock invert */ |
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| 286 | #define TC_BURST(_x_) ((_x_ & 0x3 << 4) /* Burst signal selection */ |
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| 287 | #define TC_WAVE BIT15 /* 0 for catpure, 1 for wave */ |
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| 288 | |
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| 289 | /* Channel mode register - capture mode (TC_WAVE = 0) */ |
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| 290 | #define TC_CMR_LDBSTOP BIT6 /* Set to stop clock when RB loads */ |
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| 291 | #define TC_CMR_LDBDIS BIT7 /* Set to disable clock when RB loads */ |
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| 292 | #define TC_CMR_ETRGEDG(_x_) ((_x_ & 0x3) << 8) /* Select edge triggering mode */ |
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| 293 | #define TC_CMR_ABETRG BIT10 /* Select ext trigger source */ |
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| 294 | #define TC_CMR_CPCTRG BIT14 /* RC Compare trigger enable */ |
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| 295 | #define TC_CMR_LDRA(_x_) ((_x_ & 0x3) << 16) /* RA loading selection */ |
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| 296 | #define TC_CMR_LDRB(_x_) ((_x_ & 0x3) << 18) /* RB loading selection */ |
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| 297 | |
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| 298 | /* Channel mode register - wave mode (TC_WAVE = 1) */ |
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| 299 | #define TC_CMR_CPCSTOP BIT6 /* Clock stopped w/ RC compare */ |
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| 300 | #define TC_CMR_CPCDIS BIT7 /* Clock disabled w/ RC compare */ |
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| 301 | #define TC_CMR_EEVTEDG(_x_) ((_x_ & 0x3) << 8) /* Ext event edge selection */ |
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| 302 | #define TC_CMR_EEVT(_x_) ((_x_ & 0x3) << 10) /* Ext event selection */ |
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| 303 | #define TC_CMR_ENETRG BIT12 /* Ext event trigger enable */ |
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| 304 | #define TC_CMR_WAVESEL(_x_) ((_x_ & 0x3) << 13) /* Waveform selection */ |
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| 305 | #define TC_CMR_ACPA(_x_) ((_x_ & 0x3) << 16) /* RA compare effect on TIOA */ |
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| 306 | #define TC_CMR_ACPC(_x_) ((_x_ & 0x3) << 18) /* RC compare effect on TIOA */ |
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| 307 | #define TC_CMR_AEEVT(_x_) ((_x_ & 0x3) << 20) /* Ext event effect on TIOA */ |
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| 308 | #define TC_CMR_ASWTRG(_x_) ((_x_ & 0x3) << 22) /* SW trigger effect on TIOA */ |
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| 309 | #define TC_CMR_BCPB(_x_) ((_x_ & 0x3) << 24) /* RB compare effect on TIOB */ |
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| 310 | #define TC_CMR_BCPC(_x_) ((_x_ & 0x3) << 26) /* RC compare effect on TIOB */ |
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| 311 | #define TC_CMR_BEEVT(_x_) ((_x_ & 0x3) << 28) /* Ext event effect on TIOB */ |
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| 312 | #define TC_CMR_BSWTRG(_x_) ((_x_ & 0x3) << 30) /* SW trigger effect on TIOB */ |
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| 313 | |
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| 314 | /* Counter value */ |
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| 315 | #define TC_CV_MASK 0xffff /* Timer counter mask */ |
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| 316 | |
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| 317 | /* Status, Interrupt enable, Interrupt disable, and Interrupt mask registers */ |
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| 318 | #define TC_SR_COVFS BIT0 /* Counter overflow status */ |
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| 319 | #define TC_SR_LOVRS BIT1 /* Load overrun status */ |
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| 320 | #define TC_SR_CPAS BIT2 /* RA compare status */ |
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| 321 | #define TC_SR_CPBS BIT3 /* RB compare status */ |
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| 322 | #define TC_SR_CPCS BIT4 /* RC compare status */ |
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| 323 | #define TC_SR_LDRAS BIT5 /* RA loading status */ |
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| 324 | #define TC_SR_LDRBS BIT6 /* RB loading status */ |
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| 325 | #define TC_SR_ETRGS BIT7 /* External trigger status */ |
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| 326 | #define TC_SR_CLKSTA BIT16 /* Clock enabling status */ |
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| 327 | #define TC_SR_MTIOA BIT17 /* TIOA Mirror */ |
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| 328 | #define TC_SR_MTIOB BIT18 /* TIOB Mirror */ |
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| 329 | |
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| 330 | /*************************************************************************** |
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| 331 | * External Bus Interface Unit |
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| 332 | **************************************************************************/ |
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| 333 | #define EBI_BASE 0xFFFFFF60 |
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| 334 | #define EBI_REG(_x_) *(vulong *)(EBI_BASE + _x_) |
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| 335 | |
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| 336 | /*************************************************************************** |
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| 337 | * Static Memory Interface Unit |
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| 338 | ***************************************************************************/ |
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| 339 | #define SMC_REG(_x_) *(vulong *)(EBI_BASE + 0x10 + _x_) |
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| 340 | |
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| 341 | /************************************************************************** |
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| 342 | * SDRAM Memory Interface Unit |
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| 343 | **************************************************************************/ |
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| 344 | #define SDRC_REG(_x_) *(vulong *)(EBI_BASE + 0x30 + _x_) |
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| 345 | |
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| 346 | #endif /* __AT91RM9200_H__ */ |
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| 347 | |
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