source: rtems/c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h @ 359e537

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Last change on this file since 359e537 was 359e537, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/30/09 at 05:09:41

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[af85485]1/*
[4eee8434]2 * Atmel AT91RM9200 Register definitions, used in KIT637_V6 (CSB637)
[af85485]3 *
4 * Copyright (c) 2003 by Cogent Computer Systems
5 * Written by Mike Kelly <mike@cogcomp.com>
[4eee8434]6 *
7 * Modified by Fernando Nicodemos <fgnicodemos@terra.com.br>
8 * from NCB - Sistemas Embarcados Ltda. (Brazil)
9 *
[af85485]10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *
[93f4a906]13 *  http://www.rtems.com/license/LICENSE.
[af85485]14 *
15 *  $Id$
[4eee8434]16*/
17
18
[af85485]19#ifndef __AT91RM9200_H__
20#define __AT91RM9200_H__
21
22#include "bits.h"
23
24typedef volatile unsigned long vulong;
25
26/* Source Mode Register - 32 of them */
27#define AIC_SMR_BASE            0xFFFFF000
28#define AIC_SMR_REG(_x_)        *(vulong *)(AIC_SMR_BASE + (_x_ & 0x7c))
29
30/* Source Vector Register - 32 of them */
31#define AIC_SVR_BASE            0xFFFFF080
32#define AIC_SVR_REG(_x_)        *(vulong *)(AIC_SVR_BASE + (_x_ & 0x7c))
33
34/* Control Register - 32 of them */
[359e537]35#define AIC_CTL_BASE            0xFFFFF100
[af85485]36#define AIC_CTL_REG(_x_)        *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f))
37
38/* Register Offsets */
39/* offsets from AIC_SMR_BASE and AIC_SVR_BASE */
[5e14d89]40#define AIC_SMR_FIQ             0x00    /* Advanced Interrupt Controller FIQ */
41#define AIC_SMR_SYSIRQ          0x04    /* Advanced Interrupt Controller SYSIRQ */
42#define AIC_SMR_PIOA            0x08    /* Parallel I/O Controller A */
43#define AIC_SMR_PIOB            0x0c    /* Parallel I/O Controller B */
44#define AIC_SMR_PIOC            0x10    /* Parallel I/O Controller C */
45#define AIC_SMR_PIOD            0x14    /* Parallel I/O Controller D */
46#define AIC_SMR_US0             0x18    /* USART 0 */
47#define AIC_SMR_US1             0x1c    /* USART 1 */
48#define AIC_SMR_US2             0x20    /* USART 2 */
49#define AIC_SMR_US3             0x24    /* USART 3 */
50#define AIC_SMR_MCI             0x28    /* Multimedia Card Interface */
51#define AIC_SMR_UDP             0x2c    /* USB Device Port */
52#define AIC_SMR_TWI             0x30    /* Two-wire Interface */
53#define AIC_SMR_SPI             0x34    /* Serial Peripheral Interface */
54#define AIC_SMR_SSC0            0x38    /* Synchronous Serial Controller 0 */
55#define AIC_SMR_SSC1            0x3c    /* Synchronous Serial Controller 1 */
56#define AIC_SMR_SSC2            0x40    /* Synchronous Serial Controller 2 */
57#define AIC_SMR_TC0             0x44    /* Timer/Counter 0 */
58#define AIC_SMR_TC1             0x48    /* Timer/Counter 1 */
59#define AIC_SMR_TC2             0x4c    /* Timer/Counter 2 */
60#define AIC_SMR_TC3             0x50    /* Timer/Counter 3 */
61#define AIC_SMR_TC4             0x54    /* Timer/Counter 4 */
62#define AIC_SMR_TC5             0x58    /* Timer/Counter 5 */
63#define AIC_SMR_UHP             0x5c    /* USB Host Port */
64#define AIC_SMR_EMAC            0x60    /* Ethernet MAC */
65#define AIC_SMR_IRQ0            0x64    /* Advanced Interrupt Controller IRQ0 */
66#define AIC_SMR_IRQ1            0x68    /* Advanced Interrupt Controller IRQ1 */
67#define AIC_SMR_IRQ2            0x6c    /* Advanced Interrupt Controller IRQ2 */
68#define AIC_SMR_IRQ3            0x70    /* Advanced Interrupt Controller IRQ3 */
69#define AIC_SMR_IRQ4            0x74    /* Advanced Interrupt Controller IRQ4 */
70#define AIC_SMR_IRQ5            0x78    /* Advanced Interrupt Controller IRQ5 */
71#define AIC_SMR_IRQ6            0x7c    /* Advanced Interrupt Controller IRQ6 */
[af85485]72
73/* from AIC_CTL_BASE */
[5e14d89]74#define AIC_IVR                 0x00    /* IRQ Vector Register */
75#define AIC_FVR                 0x04    /* FIQ Vector Register */
76#define AIC_ISR                 0x08    /* Interrupt Status Register */
77#define AIC_IPR                 0x0C    /* Interrupt Pending Register */
78#define AIC_IMR                 0x10    /* Interrupt Mask Register */
79#define AIC_CISR                0x14    /* Core Interrupt Status Register */
80#define AIC_IECR                0x20    /* Interrupt Enable Command Register */
81#define AIC_IDCR                0x24    /* Interrupt Disable Command Register */
82#define AIC_ICCR                0x28    /* Interrupt Clear Command Register */
83#define AIC_ISCR                0x2C    /* Interrupt Set Command Register */
84#define AIC_EOICR               0x30    /* End of Interrupt Command Register */
85#define AIC_SPU                 0x34    /* Spurious Vector Register */
86#define AIC_DCR                 0x38    /* Debug Control Register (Protect) */
87#define AIC_FFER                0x40    /* Fast Forcing Enable Register */
88#define AIC_FFDR                0x44    /* Fast Forcing Disable Register */
89#define AIC_FFSR                0x48    /* Fast Forcing Status Register */
[af85485]90
91/* Bit Defines */
92/* AIC_ISR - Interrupt Status Register */
[5e14d89]93#define AIC_ISR_IRQID_MASK      0x1f    /* current interrupt ID          */
[af85485]94
[5e14d89]95/* AIC_CISR - Core Interrupt Status Register */
96#define AIC_CISR_IRQ            BIT1    /* 1 = Core IRQ is active */
97#define AIC_CISR_FIQ            BIT0    /* 1 = Core FIQ is active */
[af85485]98
[5e14d89]99/* AIC_DCR - Debug Control Register (Protect) */
100#define AIC_DCR_GMSK            BIT1    /* 0 = AIC controls IRQ and FIQ */
101#define AIC_DCR_PROT            BIT0    /* 1 = enable protection mode */
[af85485]102
[5e14d89]103/* AIC_SMR */
[af85485]104#define AIC_SMR_PRIOR(_x_)      ((_x_ & 0x07) << 0)
[5e14d89]105#define AIC_SMR_SRC_LVL_LOW     (0 << 5)        /* Are these right? docs don't say which is high/low     */
[359e537]106#define AIC_SMR_SRC_EDGE_LOW    (1 << 5)
107#define AIC_SMR_SRC_LVL_HI      (2 << 5)
108#define AIC_SMR_SRC_EDGE_HI     (3 << 5)
[af85485]109
110/**************************************************************************/
[4eee8434]111/* Debug Unit                                                             */
[af85485]112/**************************************************************************/
113#define DBGU_BASE               0xFFFFF200
114#define DBGU_REG(_x_)   *(vulong *)(DBGU_BASE + _x_)
115
[5e14d89]116/* Register Offsets */
117#define DBGU_CR                 0x00    /* Control Register */
118#define DBGU_MR                 0x04    /* Mode Register */
119#define DBGU_IER                0x08    /* Interrupt Enable Register */
120#define DBGU_IDR                0x0C    /* Interrupt Disable Register */
121#define DBGU_IMR                0x10    /* Interrupt Mask Register */
122#define DBGU_CSR                0x14    /* Channel Status Register */
123#define DBGU_RHR                0x18    /* Receiver Holding Register */
124#define DBGU_THR                0x1C    /* Transmitter Holding Register */
125#define DBGU_BRGR               0x20    /* Baud Rate Generator Register */
126#define DBGU_C1R                0x40    /* Chip ID1 Register */
127#define DBGU_C2R                0x44    /* Chip ID2 Register */
128#define DBGU_FNTR               0x48    /* Force NTRST Register */
[af85485]129
[4eee8434]130/**************************************************************************/
131/* USART 0-3                                                              */
132/**************************************************************************/
133#define USART0_BASE             0xFFFC0000
134#define USART1_BASE             0xFFFC4000
135#define USART2_BASE             0xFFFC8000
136#define USART3_BASE             0xFFFCC000
137/**** The USART3_BASE at the AT91RM9200 Manual is wrong ****/
138/**** Manual revision: Rev. 1768H-ATARM–16-Jun-09       ****/
139//#define USART3_BASE             0xFFECC000
140
[af85485]141/****************/
142/* System Timer */
143/****************/
144#define ST_BASE                 0xFFFFFD00
145#define ST_REG(_x_)             *(vulong *)(ST_BASE + _x_)
146
[5e14d89]147/* Register Offsets */
148#define ST_CR                   0x00    /* Control Register */
149#define ST_PIMR                 0x04    /* Period Interval Mode Register */
150#define ST_WDMR                 0x08    /* Watchdog Mode Register */
151#define ST_RTMR                 0x0C    /* Real-time Mode Register */
152#define ST_SR                   0x10    /* Status Register */
153#define ST_IER                  0x14    /* Interrupt Enable Register */
154#define ST_IDR                  0x18    /* Interrupt Disable Register */
155#define ST_IMR                  0x1C    /* Interrupt Mask Register */
156#define ST_RTAR                 0x20    /* Real-time Alarm Register */
157#define ST_CRTR                 0x24    /* Current Real-time Register */
158
159/* Bit Defines */
160/* ST_CR - Control Register */
161#define ST_CR_WDRST                     BIT0    /* write 1 to reload WD counter  */
162
163/* ST_PIMR - Period Interval Mode Register */
[af85485]164#define ST_PIMR_PIV_MASK        0x0000ffff
165
[5e14d89]166/* ST_WDMR - Watchdog Mode Register */
167#define ST_WDMR_EXTEN           BIT17   /* WDOVF is not implemented on AT91RM9200 */
168#define ST_WDMR_RSTEN           BIT16   /* 1 = reset the AT91RM9200 when WD overflows */
169#define ST_WDMR_WDV_MASK        0x0000ffff      /* WD counter is in the lower 16-bits */
[af85485]170
[5e14d89]171/* ST_RTMR - Real-time Mode Register */
172#define ST_RTMR_RTPRES_MASK     0x0000ffff      /* Real-Time Prescaler */
[af85485]173
[5e14d89]174/* ST_SR - Status Register - Read Only */
175/* ST_IER - Interrupt Enable Register - Write Only */
176/* ST_IDR - Interrupt Disable Register - Write Only */
177/* ST_IMR - Interrupt Mask Register - Read Only */
[af85485]178#define ST_SR_ALMS                      BIT3
179#define ST_SR_RTTINC            BIT2
180#define ST_SR_WDOVF                     BIT1
181#define ST_SR_PITS                      BIT0
182
[5e14d89]183/* ST_RTAR - Real-time Alarm Register */
[af85485]184#define ST_RTAR_ALMV_MASK       0x000fffff
185
[5e14d89]186/* ST_CRTR - Current Real-time Register */
[af85485]187#define ST_CRTR_CRTV_MASK       0x000fffff
188
189
190/**************************************************************************
191 * Peripheral Data Control (DMA)
192 * Note that each of the following peripherals has it's own
193 * set of these registers starting at offset 0x100 from it's
194 * base address: DBGU, SPI, USART and SSC
[359e537]195 * To access the DMA for a peripheral, use the macro for that
[af85485]196 * peripheral but with these register offsets
197 **************************************************************************/
[5e14d89]198/* Register Offsets */
199#define PDC_RPR         0x100   /* Receive Pointer Register */
200#define PDC_RCR         0x104   /* Receive Counter Register */
201#define PDC_TPR         0x108   /* Transmit Pointer Register */
202#define PDC_TCR         0x10c   /* Transmit Counter Register */
203#define PDC_RNPR        0x110   /* Receive Next Pointer Register */
204#define PDC_RNCR        0x114   /* Receive Next Counter Register */
205#define PDC_TNPR        0x118   /* Transmit Next Pointer Register */
206#define PDC_TNCR        0x11c   /* Transmit Next Counter Register */
207#define PDC_PTCR        0x120   /* PDC Transfer Control Register */
208#define PDC_PTSR        0x124   /* PDC Transfer Status Register */
[af85485]209
210/**************************************************************************
211 * Parallel I/O Unit
212 * There are four PIO blocks - A, B, C and D.  They all have the
213 * same register set, but different base addresses
214 **************************************************************************/
[5e14d89]215/* Port A */
[af85485]216#define PIOA_BASE               0xFFFFF400
217#define PIOA_REG(_x_)   *(vulong *)(PIOA_BASE + _x_)
218
[5e14d89]219/* Port B */
[af85485]220#define PIOB_BASE               0xFFFFF600
221#define PIOB_REG(_x_)   *(vulong *)(PIOB_BASE + _x_)
222
[5e14d89]223/* Port C */
[af85485]224#define PIOC_BASE               0xFFFFF800
225#define PIOC_REG(_x_)   *(vulong *)(PIOC_BASE + _x_)
226
[5e14d89]227/* Port D */
[af85485]228#define PIOD_BASE               0xFFFFFA00
229#define PIOD_REG(_x_)   *(vulong *)(PIOD_BASE + _x_)
230
231/**************************************************************************
232 * Power Management and Clock Control
233 *************************************************************************/
234#define PMC_BASE                0xFFFFFC00
235#define PMC_REG(_x_)    *(vulong *)(PMC_BASE + _x_)
236
237/**************************************************************************
238 * MAC Unit
239 *************************************************************************/
240#define EMAC_BASE               0xFFFBC000
241#define EMAC_REG(_x_)   *(vulong *)(EMAC_BASE + _x_)
242
243/**************************************************************************
244 * Timer/Counter Unit
245 **************************************************************************/
246#define TC_BASE         0xFFFA0000
247#define TC_REG(_x_)     *(vulong *)(TC_BASE + 0x00 + _x_)
248#define TC_TC0_REG(_x_) *(vulong *)(TC_BASE + 0x00 + _x_)
249#define TC_TC1_REG(_x_) *(vulong *)(TC_BASE + 0x40 + _x_)
250#define TC_TC2_REG(_x_) *(vulong *)(TC_BASE + 0x80 + _x_)
251
[5e14d89]252/* Offsets from TC_TC?_REG  */
253#define TC_CCR      0x00    /* Channel Control Register  */
254#define TC_CMR      0x04    /* Channel Mode Register  */
255#define TC_CV       0x10    /* Counter Value  */
256#define TC_RA       0x14    /* Register A  */
257#define TC_RB       0x18    /* Register B  */
258#define TC_RC       0x1C    /* Register C  */
259#define TC_SR       0x20    /* Status Register  */
260#define TC_IER      0x24    /* Interrupt Enable Register  */
261#define TC_IDR      0x28    /* Interrupt Disable Register  */
262#define TC_IMR      0x2C    /* Interrupt Mask Register  */
263
264/* Offsets from TC_BASE */
265#define TC_BCR      0xc0    /* Channel Control Register  */
266#define TC_BMR      0xc4    /* Channel Control Register  */
267
268/* Block control register */
269#define TC_BCR_SYNC    BIT1       /* Set to syncronize channels */
270
271/* Block mode register */
272#define TC_BMR_TC0(_x_)    ((_x_ & 0x3) << 0)   /* TC0 clock source */
273#define TC_BMR_TC1(_x_)    ((_x_ & 0x3) << 2)   /* TC1 clock source */
274#define TC_BMR_TC2(_x_)    ((_x_ & 0x3) << 4)   /* TC2 clock source */
275
276/* Channel Control register */
277#define TC_CCR_CLKEN     BIT0       /* Enable clock */
278#define TC_CCR_CLKDIS    BIT1       /* Disable clock */
279#define TC_CCR_SWTRG     BIT2       /* Software trigger command */
280
281/* Channel mode register */
282#define TC_CMR_TCCLKS(_x_)   ((_x_ & 0x7) << 0)  /* Clock source */
283#define TC_CMR_CLKI          BIT3                /* Clock invert */
284#define TC_BURST(_x_)        ((_x_ & 0x3 << 4)   /* Burst signal selection */
285#define TC_WAVE              BIT15               /* 0 for catpure, 1 for wave */
286
287/* Channel mode register - capture mode (TC_WAVE = 0) */
288#define TC_CMR_LDBSTOP       BIT6                /* Set to stop clock when RB loads */
289#define TC_CMR_LDBDIS        BIT7                /* Set to disable clock when RB loads */
290#define TC_CMR_ETRGEDG(_x_)  ((_x_ & 0x3) << 8)  /* Select edge triggering mode */
291#define TC_CMR_ABETRG        BIT10               /* Select ext trigger source */
292#define TC_CMR_CPCTRG        BIT14               /* RC Compare trigger enable */
293#define TC_CMR_LDRA(_x_)     ((_x_ & 0x3) << 16) /* RA loading selection */
294#define TC_CMR_LDRB(_x_)     ((_x_ & 0x3) << 18) /* RB loading selection */
295
296/* Channel mode register - wave mode (TC_WAVE = 1) */
297#define TC_CMR_CPCSTOP       BIT6                 /* Clock stopped w/ RC compare */
298#define TC_CMR_CPCDIS        BIT7                 /* Clock disabled w/ RC compare */
299#define TC_CMR_EEVTEDG(_x_)  ((_x_ & 0x3) << 8)   /* Ext event edge selection */
300#define TC_CMR_EEVT(_x_)     ((_x_ & 0x3) << 10)  /* Ext event selection */
301#define TC_CMR_ENETRG        BIT12                /* Ext event trigger enable */
302#define TC_CMR_WAVESEL(_x_)  ((_x_ & 0x3) << 13)  /* Waveform selection */
303#define TC_CMR_ACPA(_x_)     ((_x_ & 0x3) << 16)  /* RA compare effect on TIOA */
304#define TC_CMR_ACPC(_x_)     ((_x_ & 0x3) << 18)  /* RC compare effect on TIOA */
305#define TC_CMR_AEEVT(_x_)    ((_x_ & 0x3) << 20)  /* Ext event effect on TIOA */
306#define TC_CMR_ASWTRG(_x_)   ((_x_ & 0x3) << 22)  /* SW trigger effect on TIOA */
307#define TC_CMR_BCPB(_x_)     ((_x_ & 0x3) << 24)  /* RB compare effect on TIOB */
308#define TC_CMR_BCPC(_x_)     ((_x_ & 0x3) << 26)  /* RC compare effect on TIOB */
309#define TC_CMR_BEEVT(_x_)    ((_x_ & 0x3) << 28)  /* Ext event effect on TIOB */
310#define TC_CMR_BSWTRG(_x_)   ((_x_ & 0x3) << 30)  /* SW trigger effect on TIOB */
311
312/* Counter value */
313#define TC_CV_MASK            0xffff              /* Timer counter mask */
314
315/* Status, Interrupt enable, Interrupt disable, and Interrupt mask registers */
316#define TC_SR_COVFS     BIT0        /* Counter overflow status */
317#define TC_SR_LOVRS     BIT1        /* Load overrun status */
318#define TC_SR_CPAS      BIT2        /* RA compare status */
319#define TC_SR_CPBS      BIT3        /* RB compare status */
320#define TC_SR_CPCS      BIT4        /* RC compare status */
321#define TC_SR_LDRAS     BIT5        /* RA loading status */
322#define TC_SR_LDRBS     BIT6        /* RB loading  status */
323#define TC_SR_ETRGS     BIT7        /* External trigger status */
324#define TC_SR_CLKSTA    BIT16       /* Clock enabling status */
325#define TC_SR_MTIOA     BIT17       /* TIOA Mirror */
326#define TC_SR_MTIOB     BIT18       /* TIOB Mirror */
[af85485]327
328/***************************************************************************
329 * External Bus Interface Unit
330 **************************************************************************/
331#define EBI_BASE                        0xFFFFFF60
332#define EBI_REG(_x_)            *(vulong *)(EBI_BASE + _x_)
333
334/***************************************************************************
335 * Static Memory Interface Unit
336 ***************************************************************************/
337#define SMC_REG(_x_)            *(vulong *)(EBI_BASE + 0x10 + _x_)
338
339/**************************************************************************
340 * SDRAM Memory Interface Unit
341 **************************************************************************/
342#define SDRC_REG(_x_)           *(vulong *)(EBI_BASE + 0x30 + _x_)
343
344#endif /* __AT91RM9200_H__ */
345
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