1 | /* |
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2 | * This file contains the console driver chip level routines for the |
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3 | * Zilog z85c30 chip. |
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4 | * |
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5 | * The Zilog Z8530 is also available as: |
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6 | * |
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7 | * + Intel 82530 |
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8 | * + AMD ??? |
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9 | * |
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10 | * COPYRIGHT (c) 1998 by Radstone Technology |
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11 | * |
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12 | * |
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13 | * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY |
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14 | * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE |
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15 | * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK |
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16 | * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. |
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17 | * |
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18 | * You are hereby granted permission to use, copy, modify, and distribute |
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19 | * this file, provided that this notice, plus the above copyright notice |
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20 | * and disclaimer, appears in all copies. Radstone Technology will provide |
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21 | * no support for this code. |
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22 | * |
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23 | * COPYRIGHT (c) 1989-1997. |
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24 | * On-Line Applications Research Corporation (OAR). |
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25 | * Copyright assigned to U.S. Government, 1994. |
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26 | * |
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27 | * The license and distribution terms for this file may be |
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28 | * found in the file LICENSE in this distribution or at |
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29 | * http://www.OARcorp.com/rtems/license.html. |
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30 | * |
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31 | * $Id$ |
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32 | */ |
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33 | |
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34 | #include <rtems.h> |
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35 | #include <rtems/libio.h> |
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36 | #include <stdlib.h> |
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37 | |
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38 | #include <libchip/serial.h> |
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39 | #include "z85c30_p.h" |
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40 | #include "sersupp.h" |
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41 | |
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42 | /* |
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43 | * Flow control is only supported when using interrupts |
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44 | */ |
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45 | |
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46 | console_flow z85c30_flow_RTSCTS = |
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47 | { |
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48 | z85c30_negate_RTS, /* deviceStopRemoteTx */ |
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49 | z85c30_assert_RTS /* deviceStartRemoteTx */ |
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50 | }; |
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51 | |
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52 | console_flow z85c30_flow_DTRCTS = |
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53 | { |
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54 | z85c30_negate_DTR, /* deviceStopRemoteTx */ |
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55 | z85c30_assert_DTR /* deviceStartRemoteTx */ |
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56 | }; |
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57 | |
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58 | /* |
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59 | * Exported driver function table |
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60 | */ |
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61 | |
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62 | console_fns z85c30_fns = |
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63 | { |
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64 | libchip_serial_default_probe, /* deviceProbe */ |
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65 | z85c30_open, /* deviceFirstOpen */ |
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66 | z85c30_flush, /* deviceLastClose */ |
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67 | NULL, /* deviceRead */ |
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68 | z85c30_write_support_int, /* deviceWrite */ |
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69 | z85c30_initialize_interrupts, /* deviceInitialize */ |
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70 | z85c30_write_polled, /* deviceWritePolled */ |
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71 | NULL, /* deviceSetAttributes */ |
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72 | TRUE /* deviceOutputUsesInterrupts */ |
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73 | }; |
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74 | |
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75 | console_fns z85c30_fns_polled = |
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76 | { |
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77 | libchip_serial_default_probe, /* deviceProbe */ |
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78 | z85c30_open, /* deviceFirstOpen */ |
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79 | z85c30_close, /* deviceLastClose */ |
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80 | z85c30_inbyte_nonblocking_polled, /* deviceRead */ |
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81 | z85c30_write_support_polled, /* deviceWrite */ |
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82 | z85c30_init, /* deviceInitialize */ |
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83 | z85c30_write_polled, /* deviceWritePolled */ |
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84 | NULL, /* deviceSetAttributes */ |
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85 | FALSE, /* deviceOutputUsesInterrupts */ |
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86 | }; |
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87 | |
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88 | extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); |
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89 | |
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90 | |
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91 | |
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92 | /* |
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93 | * z85c30_initialize_port |
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94 | * |
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95 | * initialize a z85c30 Port |
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96 | */ |
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97 | |
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98 | Z85C30_STATIC void z85c30_initialize_port( |
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99 | int minor |
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100 | ) |
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101 | { |
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102 | unsigned32 ulCtrlPort; |
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103 | unsigned32 ulBaudDivisor; |
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104 | setRegister_f setReg; |
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105 | |
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106 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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107 | setReg = Console_Port_Tbl[minor].setRegister; |
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108 | |
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109 | /* |
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110 | * Using register 4 |
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111 | * Set up the clock rate is 16 times the data |
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112 | * rate, 8 bit sync char, 1 stop bit, no parity |
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113 | */ |
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114 | |
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115 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK ); |
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116 | |
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117 | /* |
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118 | * Set up for 8 bits/character on receive with |
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119 | * receiver disable via register 3 |
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120 | */ |
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121 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS ); |
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122 | |
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123 | /* |
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124 | * Set up for 8 bits/character on transmit |
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125 | * with transmitter disable via register 5 |
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126 | */ |
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127 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS ); |
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128 | |
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129 | /* |
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130 | * Clear misc control bits |
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131 | */ |
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132 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 ); |
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133 | |
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134 | /* |
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135 | * Setup the source of the receive and xmit |
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136 | * clock as BRG output and the transmit clock |
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137 | * as the output source for TRxC pin via register 11 |
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138 | */ |
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139 | (*setReg)( |
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140 | ulCtrlPort, |
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141 | SCC_WR0_SEL_WR11, |
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142 | SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI | |
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143 | SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN |
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144 | ); |
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145 | |
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146 | ulBaudDivisor = Z85C30_Baud( |
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147 | (unsigned32) Console_Port_Tbl[minor].ulClock, |
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148 | (unsigned32) Console_Port_Tbl[minor].pDeviceParams |
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149 | ); |
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150 | |
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151 | /* |
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152 | * Setup the lower 8 bits time constants=1E. |
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153 | * If the time constans=1E, then the desire |
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154 | * baud rate will be equilvalent to 9600, via register 12. |
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155 | */ |
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156 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
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157 | |
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158 | /* |
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159 | * using register 13 |
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160 | * Setup the upper 8 bits time constant |
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161 | */ |
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162 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
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163 | |
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164 | /* |
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165 | * Enable the baud rate generator enable with clock from the |
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166 | * SCC's PCLK input via register 14. |
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167 | */ |
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168 | (*setReg)( |
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169 | ulCtrlPort, |
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170 | SCC_WR0_SEL_WR14, |
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171 | SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL |
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172 | ); |
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173 | |
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174 | /* |
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175 | * We are only interested in CTS state changes |
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176 | */ |
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177 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE ); |
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178 | |
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179 | /* |
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180 | * Reset errors |
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181 | */ |
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182 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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183 | |
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184 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST ); |
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185 | |
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186 | /* |
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187 | * Enable the receiver via register 3 |
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188 | */ |
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189 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN ); |
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190 | |
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191 | /* |
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192 | * Enable the transmitter pins set via register 5. |
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193 | */ |
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194 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN ); |
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195 | |
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196 | /* |
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197 | * Disable interrupts |
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198 | */ |
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199 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 ); |
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200 | |
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201 | /* |
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202 | * Reset TX CRC |
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203 | */ |
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204 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC ); |
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205 | |
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206 | /* |
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207 | * Reset interrupts |
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208 | */ |
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209 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); |
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210 | } |
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211 | |
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212 | Z85C30_STATIC int z85c30_open( |
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213 | int major, |
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214 | int minor, |
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215 | void *arg |
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216 | ) |
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217 | { |
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218 | /* |
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219 | * Assert DTR |
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220 | */ |
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221 | |
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222 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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223 | z85c30_assert_DTR(minor); |
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224 | } |
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225 | |
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226 | return(RTEMS_SUCCESSFUL); |
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227 | } |
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228 | |
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229 | Z85C30_STATIC int z85c30_close( |
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230 | int major, |
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231 | int minor, |
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232 | void *arg |
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233 | ) |
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234 | { |
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235 | /* |
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236 | * Negate DTR |
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237 | */ |
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238 | |
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239 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { |
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240 | z85c30_negate_DTR(minor); |
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241 | } |
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242 | |
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243 | return(RTEMS_SUCCESSFUL); |
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244 | } |
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245 | |
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246 | /* |
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247 | * z85c30_write_polled |
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248 | * |
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249 | * This routine transmits a character using polling. |
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250 | */ |
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251 | |
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252 | Z85C30_STATIC void z85c30_write_polled( |
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253 | int minor, |
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254 | char cChar |
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255 | ) |
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256 | { |
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257 | volatile unsigned8 z85c30_status; |
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258 | unsigned32 ulCtrlPort; |
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259 | getRegister_f getReg; |
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260 | setData_f setData; |
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261 | |
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262 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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263 | getReg = Console_Port_Tbl[minor].getRegister; |
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264 | setData = Console_Port_Tbl[minor].setData; |
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265 | |
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266 | /* |
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267 | * Wait for the Transmit buffer to indicate that it is empty. |
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268 | */ |
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269 | |
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270 | z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 ); |
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271 | |
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272 | while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
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273 | /* |
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274 | * Yield while we wait |
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275 | */ |
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276 | if (_System_state_Is_up(_System_state_Get())) { |
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277 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
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278 | } |
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279 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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280 | } |
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281 | |
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282 | /* |
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283 | * Write the character. |
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284 | */ |
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285 | |
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286 | (*setData)(Console_Port_Tbl[minor].ulDataPort, cChar); |
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287 | } |
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288 | |
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289 | /* |
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290 | * Console Device Driver Entry Points |
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291 | */ |
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292 | |
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293 | Z85C30_STATIC void z85c30_init(int minor) |
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294 | { |
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295 | unsigned32 ulCtrlPort; |
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296 | unsigned8 dummy; |
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297 | z85c30_context *pz85c30Context; |
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298 | setRegister_f setReg; |
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299 | getRegister_f getReg; |
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300 | |
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301 | setReg = Console_Port_Tbl[minor].setRegister; |
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302 | getReg = Console_Port_Tbl[minor].getRegister; |
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303 | |
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304 | pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context)); |
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305 | |
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306 | Console_Port_Data[minor].pDeviceContext=(void *)pz85c30Context; |
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307 | |
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308 | pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN; |
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309 | |
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310 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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311 | if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort2) { |
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312 | /* |
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313 | * This is channel A |
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314 | */ |
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315 | /* |
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316 | * Ensure port state machine is reset |
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317 | */ |
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318 | dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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319 | |
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320 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST); |
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321 | |
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322 | } else { |
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323 | /* |
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324 | * This is channel B |
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325 | */ |
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326 | /* |
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327 | * Ensure port state machine is reset |
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328 | */ |
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329 | dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
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330 | |
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331 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST); |
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332 | } |
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333 | |
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334 | z85c30_initialize_port(minor); |
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335 | } |
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336 | |
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337 | /* |
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338 | * These routines provide control of the RTS and DTR lines |
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339 | */ |
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340 | |
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341 | /* |
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342 | * z85c30_assert_RTS |
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343 | */ |
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344 | |
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345 | Z85C30_STATIC int z85c30_assert_RTS(int minor) |
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346 | { |
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347 | rtems_interrupt_level Irql; |
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348 | z85c30_context *pz85c30Context; |
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349 | setRegister_f setReg; |
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350 | |
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351 | setReg = Console_Port_Tbl[minor].setRegister; |
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352 | |
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353 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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354 | |
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355 | /* |
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356 | * Assert RTS |
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357 | */ |
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358 | |
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359 | rtems_interrupt_disable(Irql); |
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360 | pz85c30Context->ucModemCtrl|=SCC_WR5_RTS; |
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361 | (*setReg)( |
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362 | Console_Port_Tbl[minor].ulCtrlPort1, |
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363 | SCC_WR0_SEL_WR5, |
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364 | pz85c30Context->ucModemCtrl |
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365 | ); |
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366 | rtems_interrupt_enable(Irql); |
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367 | return 0; |
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368 | } |
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369 | |
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370 | /* |
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371 | * z85c30_negate_RTS |
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372 | */ |
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373 | |
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374 | Z85C30_STATIC int z85c30_negate_RTS(int minor) |
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375 | { |
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376 | rtems_interrupt_level Irql; |
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377 | z85c30_context *pz85c30Context; |
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378 | setRegister_f setReg; |
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379 | |
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380 | setReg = Console_Port_Tbl[minor].setRegister; |
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381 | |
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382 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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383 | |
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384 | /* |
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385 | * Negate RTS |
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386 | */ |
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387 | |
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388 | rtems_interrupt_disable(Irql); |
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389 | pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS; |
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390 | (*setReg)( |
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391 | Console_Port_Tbl[minor].ulCtrlPort1, |
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392 | SCC_WR0_SEL_WR5, |
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393 | pz85c30Context->ucModemCtrl |
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394 | ); |
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395 | rtems_interrupt_enable(Irql); |
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396 | return 0; |
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397 | } |
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398 | |
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399 | /* |
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400 | * These flow control routines utilise a connection from the local DTR |
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401 | * line to the remote CTS line |
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402 | */ |
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403 | |
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404 | /* |
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405 | * z85c30_assert_DTR |
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406 | */ |
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407 | |
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408 | Z85C30_STATIC int z85c30_assert_DTR(int minor) |
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409 | { |
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410 | rtems_interrupt_level Irql; |
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411 | z85c30_context *pz85c30Context; |
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412 | setRegister_f setReg; |
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413 | |
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414 | setReg = Console_Port_Tbl[minor].setRegister; |
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415 | |
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416 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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417 | |
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418 | /* |
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419 | * Assert DTR |
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420 | */ |
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421 | |
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422 | rtems_interrupt_disable(Irql); |
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423 | pz85c30Context->ucModemCtrl|=SCC_WR5_DTR; |
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424 | (*setReg)( |
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425 | Console_Port_Tbl[minor].ulCtrlPort1, |
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426 | SCC_WR0_SEL_WR5, |
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427 | pz85c30Context->ucModemCtrl |
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428 | ); |
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429 | rtems_interrupt_enable(Irql); |
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430 | return 0; |
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431 | } |
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432 | |
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433 | /* |
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434 | * z85c30_negate_DTR |
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435 | */ |
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436 | |
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437 | Z85C30_STATIC int z85c30_negate_DTR(int minor) |
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438 | { |
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439 | rtems_interrupt_level Irql; |
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440 | z85c30_context *pz85c30Context; |
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441 | setRegister_f setReg; |
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442 | |
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443 | setReg = Console_Port_Tbl[minor].setRegister; |
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444 | |
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445 | pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; |
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446 | |
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447 | /* |
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448 | * Negate DTR |
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449 | */ |
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450 | |
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451 | rtems_interrupt_disable(Irql); |
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452 | pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR; |
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453 | (*setReg)( |
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454 | Console_Port_Tbl[minor].ulCtrlPort1, |
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455 | SCC_WR0_SEL_WR5, |
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456 | pz85c30Context->ucModemCtrl |
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457 | ); |
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458 | rtems_interrupt_enable(Irql); |
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459 | return 0; |
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460 | } |
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461 | |
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462 | /* |
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463 | * z85c30_set_attributes |
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464 | * |
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465 | * This function sets the SCC channel to reflect the requested termios |
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466 | * port settings. |
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467 | */ |
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468 | |
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469 | Z85C30_STATIC int z85c30_set_attributes( |
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470 | int minor, |
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471 | const struct termios *t |
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472 | ) |
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473 | { |
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474 | unsigned32 ulCtrlPort; |
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475 | unsigned32 ulBaudDivisor; |
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476 | unsigned32 wr3; |
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477 | unsigned32 wr4; |
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478 | unsigned32 wr5; |
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479 | int baud_requested; |
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480 | setRegister_f setReg; |
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481 | rtems_interrupt_level Irql; |
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482 | |
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483 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
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484 | setReg = Console_Port_Tbl[minor].setRegister; |
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485 | |
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486 | /* |
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487 | * Calculate the baud rate divisor |
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488 | */ |
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489 | |
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490 | baud_requested = t->c_cflag & CBAUD; |
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491 | if (!baud_requested) |
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492 | baud_requested = B9600; /* default to 9600 baud */ |
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493 | |
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494 | ulBaudDivisor = Z85C30_Baud( |
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495 | (unsigned32) Console_Port_Tbl[minor].ulClock, |
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496 | (unsigned32) termios_baud_to_number( baud_requested ) |
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497 | ); |
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498 | |
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499 | wr3 = SCC_WR3_RX_EN; |
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500 | wr4 = SCC_WR4_16_CLOCK; |
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501 | wr5 = SCC_WR5_TX_EN; |
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502 | |
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503 | /* |
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504 | * Parity |
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505 | */ |
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506 | |
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507 | if (t->c_cflag & PARENB) { |
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508 | wr4 |= SCC_WR4_PAR_EN; |
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509 | if (!(t->c_cflag & PARODD)) |
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510 | wr4 |= SCC_WR4_PAR_EVEN; |
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511 | } |
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512 | |
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513 | /* |
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514 | * Character Size |
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515 | */ |
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516 | |
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517 | if (t->c_cflag & CSIZE) { |
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518 | switch (t->c_cflag & CSIZE) { |
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519 | case CS5: break; |
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520 | case CS6: wr3 |= SCC_WR3_RX_6_BITS; wr5 |= SCC_WR5_TX_6_BITS; break; |
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521 | case CS7: wr3 |= SCC_WR3_RX_7_BITS; wr5 |= SCC_WR5_TX_7_BITS; break; |
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522 | case CS8: wr3 |= SCC_WR3_RX_8_BITS; wr5 |= SCC_WR5_TX_8_BITS; break; |
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523 | } |
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524 | } else { |
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525 | wr3 |= SCC_WR3_RX_8_BITS; /* default to 9600,8,N,1 */ |
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526 | wr5 |= SCC_WR5_TX_8_BITS; /* default to 9600,8,N,1 */ |
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527 | } |
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528 | |
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529 | /* |
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530 | * Stop Bits |
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531 | */ |
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532 | |
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533 | if (t->c_cflag & CSTOPB) { |
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534 | wr4 |= SCC_WR4_2_STOP; /* 2 stop bits */ |
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535 | } else { |
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536 | wr4 |= SCC_WR4_1_STOP; /* 1 stop bits */ |
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537 | } |
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538 | |
---|
539 | rtems_interrupt_disable(Irql); |
---|
540 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, wr4 ); |
---|
541 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, wr3 ); |
---|
542 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, wr5 ); |
---|
543 | |
---|
544 | /* |
---|
545 | * Setup the lower 8 bits time constants=1E. |
---|
546 | * If the time constans=1E, then the desire |
---|
547 | * baud rate will be equilvalent to 9600, via register 12. |
---|
548 | */ |
---|
549 | |
---|
550 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); |
---|
551 | |
---|
552 | /* |
---|
553 | * using register 13 |
---|
554 | * Setup the upper 8 bits time constant |
---|
555 | */ |
---|
556 | |
---|
557 | (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); |
---|
558 | |
---|
559 | rtems_interrupt_enable(Irql); |
---|
560 | |
---|
561 | return 0; |
---|
562 | } |
---|
563 | |
---|
564 | /* |
---|
565 | * z85c30_isr |
---|
566 | * |
---|
567 | * This routine is the console interrupt handler for COM3 and COM4 |
---|
568 | * |
---|
569 | * Input parameters: |
---|
570 | * vector - vector number |
---|
571 | * |
---|
572 | * Output parameters: NONE |
---|
573 | * |
---|
574 | * Return values: NONE |
---|
575 | */ |
---|
576 | |
---|
577 | Z85C30_STATIC void z85c30_process( |
---|
578 | int minor, |
---|
579 | unsigned8 ucIntPend |
---|
580 | ) |
---|
581 | { |
---|
582 | unsigned32 ulCtrlPort; |
---|
583 | unsigned32 ulDataPort; |
---|
584 | volatile unsigned8 z85c30_status; |
---|
585 | char cChar; |
---|
586 | setRegister_f setReg; |
---|
587 | getRegister_f getReg; |
---|
588 | getData_f getData; |
---|
589 | setData_f setData; |
---|
590 | |
---|
591 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
592 | ulDataPort = Console_Port_Tbl[minor].ulDataPort; |
---|
593 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
594 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
595 | getData = Console_Port_Tbl[minor].getData; |
---|
596 | setData = Console_Port_Tbl[minor].setData; |
---|
597 | |
---|
598 | /* |
---|
599 | * Deal with any received characters |
---|
600 | */ |
---|
601 | while (ucIntPend&SCC_RR3_B_RX_IP) |
---|
602 | { |
---|
603 | z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
604 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
605 | break; |
---|
606 | } |
---|
607 | |
---|
608 | /* |
---|
609 | * Return the character read. |
---|
610 | */ |
---|
611 | |
---|
612 | cChar = (*getData)(ulDataPort); |
---|
613 | |
---|
614 | rtems_termios_enqueue_raw_characters( |
---|
615 | Console_Port_Data[minor].termios_data, |
---|
616 | &cChar, |
---|
617 | 1 |
---|
618 | ); |
---|
619 | } |
---|
620 | |
---|
621 | while (TRUE) |
---|
622 | { |
---|
623 | z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
624 | if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { |
---|
625 | /* |
---|
626 | * We'll get another interrupt when |
---|
627 | * the transmitter holding reg. becomes |
---|
628 | * free again and we are clear to send |
---|
629 | */ |
---|
630 | break; |
---|
631 | } |
---|
632 | |
---|
633 | if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) { |
---|
634 | /* |
---|
635 | * We can't transmit yet |
---|
636 | */ |
---|
637 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
638 | /* |
---|
639 | * The next state change of CTS will wake us up |
---|
640 | */ |
---|
641 | break; |
---|
642 | } |
---|
643 | |
---|
644 | if (Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { |
---|
645 | Console_Port_Data[minor].bActive=FALSE; |
---|
646 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
647 | z85c30_negate_RTS(minor); |
---|
648 | } |
---|
649 | /* |
---|
650 | * There is no data to transmit |
---|
651 | */ |
---|
652 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
653 | break; |
---|
654 | } |
---|
655 | |
---|
656 | Ring_buffer_Remove_character( &Console_Port_Data[minor].TxBuffer, cChar); |
---|
657 | |
---|
658 | /* |
---|
659 | * transmit character |
---|
660 | */ |
---|
661 | (*setData)(ulDataPort, cChar); |
---|
662 | |
---|
663 | /* |
---|
664 | * Interrupt once FIFO has room |
---|
665 | */ |
---|
666 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); |
---|
667 | break; |
---|
668 | } |
---|
669 | |
---|
670 | if (ucIntPend&SCC_RR3_B_EXT_IP) { |
---|
671 | /* |
---|
672 | * Clear the external status interrupt |
---|
673 | */ |
---|
674 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
675 | z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
676 | } |
---|
677 | |
---|
678 | /* |
---|
679 | * Reset interrupts |
---|
680 | */ |
---|
681 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS); |
---|
682 | } |
---|
683 | |
---|
684 | Z85C30_STATIC rtems_isr z85c30_isr( |
---|
685 | rtems_vector_number vector |
---|
686 | ) |
---|
687 | { |
---|
688 | int minor; |
---|
689 | unsigned32 ulCtrlPort; |
---|
690 | volatile unsigned8 ucIntPend; |
---|
691 | volatile unsigned8 ucIntPendPort; |
---|
692 | getRegister_f getReg; |
---|
693 | |
---|
694 | for (minor=0;minor<Console_Port_Count;minor++) { |
---|
695 | if (vector==Console_Port_Tbl[minor].ulIntVector) { |
---|
696 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort2; |
---|
697 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
698 | do { |
---|
699 | ucIntPend=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3); |
---|
700 | |
---|
701 | /* |
---|
702 | * If this is channel A select channel A status |
---|
703 | */ |
---|
704 | |
---|
705 | if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort1) { |
---|
706 | ucIntPendPort = ucIntPend>>3; |
---|
707 | ucIntPendPort = ucIntPendPort&=7; |
---|
708 | } else { |
---|
709 | ucIntPendPort = ucIntPend &= 7; |
---|
710 | } |
---|
711 | |
---|
712 | if (ucIntPendPort) { |
---|
713 | z85c30_process(minor, ucIntPendPort); |
---|
714 | } |
---|
715 | } while (ucIntPendPort); |
---|
716 | } |
---|
717 | } |
---|
718 | } |
---|
719 | |
---|
720 | /* |
---|
721 | * z85c30_flush |
---|
722 | */ |
---|
723 | |
---|
724 | Z85C30_STATIC int z85c30_flush( |
---|
725 | int major, |
---|
726 | int minor, |
---|
727 | void *arg |
---|
728 | ) |
---|
729 | { |
---|
730 | while (!Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { |
---|
731 | /* |
---|
732 | * Yield while we wait |
---|
733 | */ |
---|
734 | if (_System_state_Is_up(_System_state_Get())) { |
---|
735 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
736 | } |
---|
737 | } |
---|
738 | |
---|
739 | z85c30_close(major, minor, arg); |
---|
740 | |
---|
741 | return(RTEMS_SUCCESSFUL); |
---|
742 | } |
---|
743 | |
---|
744 | /* |
---|
745 | * z85c30_initialize_interrupts |
---|
746 | * |
---|
747 | * This routine initializes the console's receive and transmit |
---|
748 | * ring buffers and loads the appropriate vectors to handle the interrupts. |
---|
749 | * |
---|
750 | * Input parameters: NONE |
---|
751 | * |
---|
752 | * Output parameters: NONE |
---|
753 | * |
---|
754 | * Return values: NONE |
---|
755 | */ |
---|
756 | |
---|
757 | Z85C30_STATIC void z85c30_enable_interrupts( |
---|
758 | int minor |
---|
759 | ) |
---|
760 | { |
---|
761 | unsigned32 ulCtrlPort; |
---|
762 | setRegister_f setReg; |
---|
763 | |
---|
764 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
765 | setReg = Console_Port_Tbl[minor].setRegister; |
---|
766 | |
---|
767 | /* |
---|
768 | * Enable interrupts |
---|
769 | */ |
---|
770 | (*setReg)( |
---|
771 | ulCtrlPort, |
---|
772 | SCC_WR0_SEL_WR1, |
---|
773 | SCC_WR1_EXT_INT_EN | SCC_WR1_TX_INT_EN | SCC_WR1_INT_ALL_RX |
---|
774 | ); |
---|
775 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR2, 0); |
---|
776 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_MIE); |
---|
777 | |
---|
778 | /* |
---|
779 | * Reset interrupts |
---|
780 | */ |
---|
781 | (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); |
---|
782 | } |
---|
783 | |
---|
784 | Z85C30_STATIC void z85c30_initialize_interrupts( |
---|
785 | int minor |
---|
786 | ) |
---|
787 | { |
---|
788 | z85c30_init(minor); |
---|
789 | |
---|
790 | Ring_buffer_Initialize(&Console_Port_Data[minor].TxBuffer); |
---|
791 | |
---|
792 | Console_Port_Data[minor].bActive=FALSE; |
---|
793 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
794 | z85c30_negate_RTS(minor); |
---|
795 | } |
---|
796 | |
---|
797 | if (Console_Port_Tbl[minor].ulCtrlPort1== Console_Port_Tbl[minor].ulCtrlPort2) { |
---|
798 | /* |
---|
799 | * Only do this for Channel A |
---|
800 | */ |
---|
801 | |
---|
802 | set_vector(z85c30_isr, Console_Port_Tbl[minor].ulIntVector, 1); |
---|
803 | } |
---|
804 | |
---|
805 | z85c30_enable_interrupts(minor); |
---|
806 | } |
---|
807 | |
---|
808 | /* |
---|
809 | * z85c30_write_support_int |
---|
810 | * |
---|
811 | * Console Termios output entry point. |
---|
812 | * |
---|
813 | */ |
---|
814 | |
---|
815 | Z85C30_STATIC int z85c30_write_support_int( |
---|
816 | int minor, |
---|
817 | const char *buf, |
---|
818 | int len) |
---|
819 | { |
---|
820 | int i; |
---|
821 | unsigned32 Irql; |
---|
822 | |
---|
823 | for (i=0; i<len;) { |
---|
824 | if (Ring_buffer_Is_full(&Console_Port_Data[minor].TxBuffer)) { |
---|
825 | if (!Console_Port_Data[minor].bActive) { |
---|
826 | /* |
---|
827 | * Wake up the device |
---|
828 | */ |
---|
829 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
830 | z85c30_assert_RTS(minor); |
---|
831 | } |
---|
832 | rtems_interrupt_disable(Irql); |
---|
833 | Console_Port_Data[minor].bActive=TRUE; |
---|
834 | z85c30_process(minor, SCC_RR3_B_TX_IP); |
---|
835 | rtems_interrupt_enable(Irql); |
---|
836 | } else { |
---|
837 | /* |
---|
838 | * Yield while we await an interrupt |
---|
839 | */ |
---|
840 | rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); |
---|
841 | } |
---|
842 | |
---|
843 | /* |
---|
844 | * Wait for ring buffer to empty |
---|
845 | */ |
---|
846 | continue; |
---|
847 | } else { |
---|
848 | Ring_buffer_Add_character( &Console_Port_Data[minor].TxBuffer, buf[i]); |
---|
849 | i++; |
---|
850 | } |
---|
851 | } |
---|
852 | |
---|
853 | /* |
---|
854 | * Ensure that characters are on the way |
---|
855 | */ |
---|
856 | if (!Console_Port_Data[minor].bActive) { |
---|
857 | /* |
---|
858 | * Wake up the device |
---|
859 | */ |
---|
860 | if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { |
---|
861 | z85c30_assert_RTS(minor); |
---|
862 | } |
---|
863 | rtems_interrupt_disable(Irql); |
---|
864 | Console_Port_Data[minor].bActive=TRUE; |
---|
865 | z85c30_process(minor, SCC_RR3_B_TX_IP); |
---|
866 | rtems_interrupt_enable(Irql); |
---|
867 | } |
---|
868 | |
---|
869 | return (len); |
---|
870 | } |
---|
871 | |
---|
872 | /* |
---|
873 | * z85c30_inbyte_nonblocking_polled |
---|
874 | * |
---|
875 | * This routine polls for a character. |
---|
876 | */ |
---|
877 | |
---|
878 | Z85C30_STATIC int z85c30_inbyte_nonblocking_polled( |
---|
879 | int minor |
---|
880 | ) |
---|
881 | { |
---|
882 | volatile unsigned8 z85c30_status; |
---|
883 | unsigned32 ulCtrlPort; |
---|
884 | getRegister_f getReg; |
---|
885 | getData_f getData; |
---|
886 | |
---|
887 | ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; |
---|
888 | getData = Console_Port_Tbl[minor].getData; |
---|
889 | getReg = Console_Port_Tbl[minor].getRegister; |
---|
890 | |
---|
891 | /* |
---|
892 | * return -1 if a character is not available. |
---|
893 | */ |
---|
894 | z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); |
---|
895 | if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { |
---|
896 | return -1; |
---|
897 | } |
---|
898 | |
---|
899 | /* |
---|
900 | * Return the character read. |
---|
901 | */ |
---|
902 | return (*getData)(Console_Port_Tbl[minor].ulDataPort); |
---|
903 | } |
---|
904 | |
---|
905 | /* |
---|
906 | * z85c30_write_support_polled |
---|
907 | * |
---|
908 | * Console Termios output entry point. |
---|
909 | * |
---|
910 | */ |
---|
911 | |
---|
912 | Z85C30_STATIC int z85c30_write_support_polled( |
---|
913 | int minor, |
---|
914 | const char *buf, |
---|
915 | int len) |
---|
916 | { |
---|
917 | int nwrite=0; |
---|
918 | |
---|
919 | /* |
---|
920 | * poll each byte in the string out of the port. |
---|
921 | */ |
---|
922 | while (nwrite < len) { |
---|
923 | z85c30_write_polled(minor, *buf++); |
---|
924 | nwrite++; |
---|
925 | } |
---|
926 | |
---|
927 | /* |
---|
928 | * return the number of bytes written. |
---|
929 | */ |
---|
930 | return nwrite; |
---|
931 | } |
---|