1 | /* |
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2 | * |
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3 | * COPYRIGHT (c) 1989-1998. |
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4 | * On-Line Applications Research Corporation (OAR). |
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5 | * Copyright assigned to U.S. Government, 1994. |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.OARcorp.com/rtems/license.html. |
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10 | * |
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11 | * $Id$ |
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12 | */ |
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13 | |
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14 | #ifndef _MC68681_P_H_ |
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15 | #define _MC68681_P_H_ |
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16 | |
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17 | #ifdef __cplusplus |
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18 | extern "C" { |
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19 | #endif |
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20 | |
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21 | /* |
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22 | * mc68681 register offsets Read/Write Addresses |
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23 | */ |
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24 | |
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25 | #define MC68681_MODE_REG_1A 0 /* MR1A-MR Prior to Read */ |
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26 | #define MC68681_MODE_REG_2A 0 /* MR2A-MR After Read */ |
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27 | |
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28 | #define MC68681_COUNT_MODE_CURRENT_MSB 6 /* CTU */ |
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29 | #define MC68681_COUNTER_TIMER_UPPER_REG 6 /* CTU */ |
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30 | #define MC68681_COUNT_MODE_CURRENT_LSB 7 /* CTL */ |
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31 | #define MC68681_COUNTER_TIMER_LOWER_REG 7 /* CTL */ |
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32 | #define MC68681_INTERRUPT_VECTOR_REG 12 /* IVR */ |
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33 | |
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34 | #define MC68681_MODE_REG_1B 8 /* MR1B-MR Prior to Read */ |
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35 | #define MC68681_MODE_REG_2B 8 /* MR2BA-MR After Read */ |
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36 | |
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37 | /* |
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38 | * mc68681 register offsets Read Only Addresses |
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39 | */ |
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40 | |
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41 | #define MC68681_STATUS_REG_A 1 /* SRA */ |
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42 | #define MC68681_MASK_ISR_REG 2 /* MISR */ |
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43 | #define MC68681_RECEIVE_BUFFER_A 3 /* RHRA */ |
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44 | #define MC68681_INPUT_PORT_CHANGE_REG 4 /* IPCR */ |
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45 | #define MC68681_INTERRUPT_STATUS_REG 5 /* ISR */ |
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46 | #define MC68681_STATUS_REG_B 9 /* SRB */ |
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47 | #define MC68681_RECEIVE_BUFFER_B 11 /* RHRB */ |
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48 | #define MC68681_INPUT_PORT 13 /* IP */ |
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49 | #define MC68681_START_COUNT_CMD 14 /* SCC */ |
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50 | #define MC68681_STOP_COUNT_CMD 15 /* STC */ |
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51 | |
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52 | /* |
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53 | * mc68681 register offsets Write Only Addresses |
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54 | */ |
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55 | |
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56 | #define MC68681_CLOCK_SELECT_REG_A 1 /* CSRA */ |
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57 | #define MC68681_COMMAND_REG_A 2 /* CRA */ |
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58 | #define MC68681_TRANSMIT_BUFFER_A 3 /* THRA */ |
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59 | #define MC68681_AUX_CTRL_REG 4 /* ACR */ |
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60 | #define MC68681_INTERRUPT_MASK_REG 5 /* IMR */ |
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61 | #define MC68681_CLOCK_SELECT_REG_B 9 /* CSRB */ |
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62 | #define MC68681_COMMAND_REG_B 10 /* CRB */ |
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63 | #define MC68681_TRANSMIT_BUFFER_B 11 /* THRB */ |
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64 | #define MC68681_OUTPUT_PORT_CONFIG_REG 13 /* OPCR */ |
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65 | #define MC68681_OUTPUT_PORT_SET_REG 14 /* SOPBC */ |
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66 | #define MC68681_OUTPUT_PORT_RESET_BITS 15 /* COPBC */ |
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67 | |
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68 | /* |
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69 | * DUART Command Register Definitions: |
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70 | * |
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71 | * MC68681_COMMAND_REG_A,MC68681_COMMAND_REG_B |
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72 | */ |
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73 | |
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74 | #define MC68681_MODE_REG_ENABLE_RX 0x01 |
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75 | #define MC68681_MODE_REG_DISABLE_RX 0x02 |
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76 | #define MC68681_MODE_REG_ENABLE_TX 0x04 |
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77 | #define MC68681_MODE_REG_DISABLE_TX 0x08 |
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78 | #define MC68681_MODE_REG_RESET_MR_PTR 0x10 |
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79 | #define MC68681_MODE_REG_RESET_RX 0x20 |
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80 | #define MC68681_MODE_REG_RESET_TX 0x30 |
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81 | #define MC68681_MODE_REG_RESET_ERROR 0x40 |
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82 | #define MC68681_MODE_REG_RESET_BREAK 0x50 |
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83 | #define MC68681_MODE_REG_START_BREAK 0x60 |
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84 | #define MC68681_MODE_REG_STOP_BREAK 0x70 |
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85 | #define MC68681_MODE_REG_SET_RX_BRG 0x80 |
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86 | #define MC68681_MODE_REG_CLEAR_RX_BRG 0x90 |
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87 | #define MC68681_MODE_REG_SET_TX_BRG 0xa0 |
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88 | #define MC68681_MODE_REG_CLEAR_TX_BRG 0xb0 |
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89 | #define MC68681_MODE_REG_SET_STANDBY 0xc0 |
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90 | #define MC68681_MODE_REG_SET_ACTIVE 0xd0 |
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91 | |
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92 | /* |
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93 | * Mode Register Definitions |
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94 | * |
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95 | * MC68681_MODE_REG_1A |
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96 | * MC68681_MODE_REG_1B |
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97 | */ |
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98 | |
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99 | #define MC68681_5BIT_CHARS 0x00 |
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100 | #define MC68681_6BIT_CHARS 0x01 |
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101 | #define MC68681_7BIT_CHARS 0x02 |
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102 | #define MC68681_8BIT_CHARS 0x03 |
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103 | |
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104 | #define MC68681_ODD_PARITY 0x00 |
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105 | #define MC68681_EVEN_PARITY 0x04 |
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106 | |
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107 | #define MC68681_WITH_PARITY 0x00 |
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108 | #define MC68681_FORCE_PARITY 0x08 |
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109 | #define MC68681_NO_PARITY 0x10 |
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110 | #define MC68681_MULTI_DROP 0x18 |
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111 | |
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112 | #define MC68681_ERR_MODE_CHAR 0x00 |
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113 | #define MC68681_ERR_MODE_BLOCK 0x20 |
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114 | |
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115 | #define MC68681_RX_INTR_RX_READY 0x00 |
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116 | #define MC68681_RX_INTR_FFULL 0x40 |
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117 | |
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118 | #define MC68681_NO_RX_RTS_CTL 0x00 |
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119 | #define MC68681_RX_RTS_CTRL 0x80 |
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120 | |
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121 | /* |
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122 | * Mode Register Definitions |
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123 | * |
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124 | * MC68681_MODE_REG_2A |
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125 | * MC68681_MODE_REG_2B |
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126 | */ |
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127 | |
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128 | #define MC68681_STOP_BIT_LENGTH__563 0x00 |
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129 | #define MC68681_STOP_BIT_LENGTH__625 0x01 |
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130 | #define MC68681_STOP_BIT_LENGTH__688 0x02 |
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131 | #define MC68681_STOP_BIT_LENGTH__75 0x03 |
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132 | #define MC68681_STOP_BIT_LENGTH__813 0x04 |
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133 | #define MC68681_STOP_BIT_LENGTH__875 0x05 |
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134 | #define MC68681_STOP_BIT_LENGTH__938 0x06 |
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135 | #define MC68681_STOP_BIT_LENGTH_1 0x07 |
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136 | #define MC68681_STOP_BIT_LENGTH_1_563 0x08 |
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137 | #define MC68681_STOP_BIT_LENGTH_1_625 0x09 |
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138 | #define MC68681_STOP_BIT_LENGTH_1_688 0x0a |
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139 | #define MC68681_STOP_BIT_LENGTH_1_75 0x0b |
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140 | #define MC68681_STOP_BIT_LENGTH_1_813 0x0c |
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141 | #define MC68681_STOP_BIT_LENGTH_1_875 0x0d |
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142 | #define MC68681_STOP_BIT_LENGTH_1_938 0x0e |
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143 | #define MC68681_STOP_BIT_LENGTH_2 0x0f |
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144 | |
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145 | #define MC68681_CTS_ENABLE_TX 0x10 |
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146 | #define MC68681_TX_RTS_CTRL 0x20 |
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147 | |
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148 | #define MC68681_CHANNEL_MODE_NORMAL 0x00 |
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149 | #define MC68681_CHANNEL_MODE_ECHO 0x40 |
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150 | #define MC68681_CHANNEL_MODE_LOCAL_LOOP 0x80 |
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151 | #define MC68681_CHANNEL_MODE_REMOTE_LOOP 0xc0 |
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152 | |
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153 | /* |
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154 | * Status Register Definitions |
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155 | * |
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156 | * MC68681_STATUS_REG_A, MC68681_STATUS_REG_B |
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157 | */ |
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158 | |
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159 | #define MC68681_RX_READY 0x01 |
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160 | #define MC68681_FFULL 0x02 |
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161 | #define MC68681_TX_READY 0x04 |
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162 | #define MC68681_TX_EMPTY 0x08 |
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163 | #define MC68681_OVERRUN_ERROR 0x10 |
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164 | #define MC68681_PARITY_ERROR 0x20 |
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165 | #define MC68681_FRAMING_ERROR 0x40 |
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166 | #define MC68681_RECEIVED_BREAK 0x80 |
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167 | |
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168 | #define MC68681_RX_ERRORS \ |
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169 | (MC68681_OVERRUN_ERROR|MC68681_PARITY_ERROR| \ |
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170 | MC68681_FRAMING_ERROR|MC68681_RECEIVED_BREAK) |
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171 | |
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172 | /* |
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173 | * Interupt Status Register Definitions. |
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174 | * |
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175 | * MC68681_INTERRUPT_STATUS_REG |
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176 | */ |
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177 | |
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178 | /* |
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179 | * Interupt Mask Register Definitions |
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180 | * |
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181 | * MC68681_INTERRUPT_MASK_REG |
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182 | */ |
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183 | |
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184 | #define MC68681_IR_TX_READY_A 0x01 |
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185 | #define MC68681_IR_RX_READY_A 0x02 |
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186 | #define MC68681_IR_BREAK_A 0x04 |
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187 | #define MC68681_IR_COUNTER_READY 0x08 |
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188 | #define MC68681_IR_TX_READY_B 0x10 |
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189 | #define MC68681_IR_RX_READY_B 0x20 |
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190 | #define MC68681_IR_BREAK_B 0x40 |
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191 | #define MC68681_IR_INPUT_PORT_CHANGE 0x80 |
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192 | |
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193 | /* |
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194 | * Status Register Definitions. |
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195 | * |
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196 | * MC68681_STATUS_REG_A,MC68681_STATUS_REG_B |
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197 | */ |
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198 | |
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199 | #define MC68681_STATUS_RXRDY 0x01 |
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200 | #define MC68681_STATUS_FFULL 0x02 |
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201 | #define MC68681_STATUS_TXRDY 0x04 |
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202 | #define MC68681_STATUS_TXEMT 0x08 |
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203 | #define MC68681_STATUS_OVERRUN_ERROR 0x10 |
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204 | #define MC68681_STATUS_PARITY_ERROR 0x20 |
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205 | #define MC68681_STATUS_FRAMING_ERROR 0x40 |
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206 | #define MC68681_STATUS_RECEIVED_BREAK 0x80 |
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207 | |
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208 | /* |
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209 | * Definitions for the Interrupt Vector Register: |
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210 | * |
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211 | * MC68681_INTERRUPT_VECTOR_REG |
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212 | */ |
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213 | |
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214 | #define MC68681_INTERRUPT_VECTOR_INIT 0x0f |
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215 | |
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216 | /* |
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217 | * Definitions for the Auxiliary Control Register |
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218 | * |
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219 | * MC68681_AUX_CTRL_REG |
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220 | */ |
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221 | |
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222 | #define MC68681_AUX_BRG_SET1 0x00 |
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223 | #define MC68681_AUX_BRG_SET2 0x80 |
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224 | |
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225 | /* |
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226 | * Per chip context control |
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227 | */ |
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228 | |
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229 | typedef struct _mc68681_context |
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230 | { |
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231 | int mate; |
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232 | } mc68681_context; |
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233 | |
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234 | /* |
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235 | * Driver functions |
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236 | */ |
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237 | static boolean mc68681_probe(int minor); |
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238 | |
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239 | static int mc68681_set_attributes( |
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240 | int minor, |
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241 | const struct termios *t |
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242 | ); |
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243 | |
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244 | static void mc68681_init(int minor); |
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245 | |
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246 | static int mc68681_open( |
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247 | int major, |
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248 | int minor, |
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249 | void * arg |
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250 | ); |
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251 | |
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252 | static int mc68681_close( |
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253 | int major, |
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254 | int minor, |
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255 | void * arg |
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256 | ); |
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257 | |
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258 | static void mc68681_write_polled( |
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259 | int minor, |
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260 | char cChar |
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261 | ); |
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262 | |
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263 | static void mc68681_initialize_interrupts(int minor); |
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264 | |
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265 | static int mc68681_flush(int major, int minor, void *arg); |
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266 | |
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267 | static int mc68681_write_support_int( |
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268 | int minor, |
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269 | const char *buf, |
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270 | int len |
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271 | ); |
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272 | |
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273 | static int mc68681_write_support_polled( |
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274 | int minor, |
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275 | const char *buf, |
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276 | int len |
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277 | ); |
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278 | |
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279 | static int mc68681_inbyte_nonblocking_polled( |
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280 | int minor |
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281 | ); |
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282 | |
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283 | #ifdef __cplusplus |
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284 | } |
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285 | #endif |
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286 | |
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287 | #endif /* _MC68681_P_H_ */ |
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