1 | # |
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2 | # Copyright (c) 2005 Jakub Jermar |
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3 | # All rights reserved. |
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4 | # |
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5 | # Redistribution and use in source and binary forms, with or without |
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6 | # modification, are permitted provided that the following conditions |
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7 | # are met: |
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8 | # |
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9 | # - Redistributions of source code must retain the above copyright |
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10 | # notice, this list of conditions and the following disclaimer. |
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11 | # - Redistributions in binary form must reproduce the above copyright |
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12 | # notice, this list of conditions and the following disclaimer in the |
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13 | # documentation and/or other materials provided with the distribution. |
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14 | # - The name of the author may not be used to endorse or promote products |
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15 | # derived from this software without specific prior written permission. |
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16 | # |
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17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | # |
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28 | |
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29 | /* |
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30 | * $Id$ |
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31 | * |
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32 | * This file originally is sparc64/src/sun4u/start.S |
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33 | * A lot of changes are made to the code, because we only need the relevant |
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34 | * portions for taking over the D- and I-MMUs. |
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35 | * |
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36 | */ |
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37 | #define RTEMS |
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38 | |
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39 | #include <rtems/asm.h> |
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40 | |
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41 | /* RTEMS: moved all of these to a common include directory */ |
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42 | #if 0 |
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43 | #include <arch/arch.h> |
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44 | #include <arch/cpu.h> |
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45 | #include <arch/regdef.h> |
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46 | #endif |
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47 | #include <arch/boot.h> |
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48 | #include <arch/stack.h> |
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49 | |
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50 | #include <arch/mm/mmu.h> |
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51 | #include <arch/mm/tlb.h> |
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52 | #include <arch/mm/tte.h> |
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53 | |
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54 | #if 0 |
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55 | #ifdef CONFIG_SMP |
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56 | #include <arch/context_offset.h> |
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57 | #endif |
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58 | #endif |
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59 | |
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60 | .register %g2, #scratch |
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61 | .register %g3, #scratch |
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62 | #if defined (RTEMS) |
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63 | .section BOOTSTRAP |
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64 | #endif |
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65 | |
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66 | #if 0 |
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67 | .section K_TEXT_START, "ax" |
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68 | |
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69 | #define BSP_FLAG 1 |
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70 | |
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71 | /* |
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72 | * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on |
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73 | * a given processor. |
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74 | */ |
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75 | #if defined (US) |
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76 | #define PHYSMEM_ADDR_SIZE 41 |
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77 | #elif defined (US3) |
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78 | #define PHYSMEM_ADDR_SIZE 43 |
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79 | #endif |
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80 | #endif |
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81 | |
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82 | #if defined (RTEMS) |
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83 | #define PHYSMEM_ADDR_SIZE 43 |
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84 | #endif |
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85 | |
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86 | #if 0 |
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87 | /* |
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88 | * Here is where the kernel is passed control from the boot loader. |
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89 | * |
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90 | * The registers are expected to be in this state: |
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91 | * - %o0 starting address of physical memory + bootstrap processor flag |
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92 | * bits 63...1: physical memory starting address / 2 |
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93 | * bit 0: non-zero on BSP processor, zero on AP processors |
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94 | * - %o1 bootinfo structure address (BSP only) |
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95 | * - %o2 bootinfo structure size (BSP only) |
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96 | * |
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97 | * Moreover, we depend on boot having established the following environment: |
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98 | * - TLBs are on |
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99 | * - identity mapping for the kernel image |
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100 | */ |
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101 | .global kernel_image_start |
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102 | kernel_image_start: |
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103 | mov BSP_FLAG, %l0 |
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104 | and %o0, %l0, %l7 ! l7 <= bootstrap processor? |
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105 | andn %o0, %l0, %l6 ! l6 <= start of physical memory |
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106 | |
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107 | ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. |
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108 | srlx %l6, 13, %l5 |
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109 | |
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110 | ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] |
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111 | sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 |
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112 | srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5 |
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113 | |
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114 | /* |
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115 | * Setup basic runtime environment. |
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116 | */ |
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117 | |
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118 | wrpr %g0, NWINDOWS - 2, %cansave ! set maximum saveable windows |
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119 | wrpr %g0, 0, %canrestore ! get rid of windows we will |
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120 | ! never need again |
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121 | wrpr %g0, 0, %otherwin ! make sure the window state is |
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122 | ! consistent |
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123 | wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window |
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124 | ! traps for kernel |
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125 | |
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126 | wrpr %g0, 0, %wstate ! use default spill/fill trap |
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127 | |
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128 | wrpr %g0, 0, %tl ! TL = 0, primary context |
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129 | ! register is used |
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130 | |
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131 | wrpr %g0, PSTATE_PRIV_BIT, %pstate ! disable interrupts and disable |
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132 | ! 32-bit address masking |
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133 | |
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134 | wrpr %g0, 0, %pil ! intialize %pil |
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135 | #endif |
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136 | |
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137 | #if defined (RTEMS) |
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138 | /* pass o0 as start of physical memory */ |
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139 | .global _take_mmu |
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140 | _take_mmu: |
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141 | save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
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142 | mov %i0, %l6 |
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143 | #endif |
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144 | |
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145 | /* these are copied from above */ |
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146 | ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base. |
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147 | srlx %l6, 13, %l5 |
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148 | |
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149 | ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13] |
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150 | sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5 |
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151 | srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5 |
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152 | |
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153 | /* |
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154 | * Switch to kernel trap table. |
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155 | */ |
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156 | sethi %hi(trap_table), %g1 |
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157 | wrpr %g1, %lo(trap_table), %tba |
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158 | |
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159 | |
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160 | /* |
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161 | * Take over the DMMU by installing locked TTE entry identically |
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162 | * mapping the first 4M of memory. |
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163 | * |
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164 | * In case of DMMU, no FLUSH instructions need to be issued. Because of |
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165 | * that, the old DTLB contents can be demapped pretty straightforwardly |
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166 | * and without causing any traps. |
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167 | */ |
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168 | |
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169 | wr %g0, ASI_DMMU, %asi |
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170 | /* |
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171 | #define SET_TLB_DEMAP_CMD(r1, context_id) \ |
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172 | set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \ |
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173 | TLB_DEMAP_CONTEXT_SHIFT), %r1 |
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174 | */ |
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175 | /* |
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176 | ! demap context 0 |
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177 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
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178 | stxa %g0, [%g1] ASI_DMMU_DEMAP |
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179 | membar #Sync |
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180 | */ |
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181 | #define SET_TLB_TAG(r1, context) \ |
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182 | set VMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1 |
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183 | |
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184 | ! write DTLB tag |
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185 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
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186 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
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187 | membar #Sync |
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188 | |
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189 | #ifdef CONFIG_VIRT_IDX_DCACHE |
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190 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_CV | TTE_P | LMA | (imm)) |
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191 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
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192 | #define TTE_LOW_DATA(imm) (TTE_CP | TTE_P | LMA | (imm)) |
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193 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
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194 | |
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195 | #define SET_TLB_DATA(r1, r2, imm) \ |
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196 | set TTE_LOW_DATA(imm), %r1; \ |
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197 | or %r1, %l5, %r1; \ |
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198 | mov PAGESIZE_4M, %r2; \ |
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199 | sllx %r2, TTE_SIZE_SHIFT, %r2; \ |
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200 | or %r1, %r2, %r1; \ |
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201 | mov 1, %r2; \ |
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202 | sllx %r2, TTE_V_SHIFT, %r2; \ |
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203 | or %r1, %r2, %r1; |
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204 | |
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205 | ! write DTLB data and install the kernel mapping |
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206 | SET_TLB_DATA(g1, g2, TTE_L | TTE_W) ! use non-global mapping |
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207 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
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208 | membar #Sync |
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209 | |
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210 | /* |
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211 | * Because we cannot use global mappings (because we want to have |
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212 | * separate 64-bit address spaces for both the kernel and the |
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213 | * userspace), we prepare the identity mapping also in context 1. This |
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214 | * step is required by the code installing the ITLB mapping. |
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215 | */ |
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216 | /* ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP) |
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217 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
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218 | stxa %g1, [VA_DMMU_TAG_ACCESS] %asi |
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219 | membar #Sync |
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220 | |
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221 | ! write DTLB data and install the kernel mapping in context 1 |
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222 | SET_TLB_DATA(g1, g2, TTE_W) ! use non-global mapping |
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223 | stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG |
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224 | membar #Sync |
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225 | */ |
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226 | /* |
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227 | * Now is time to take over the IMMU. Unfortunatelly, it cannot be done |
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228 | * as easily as the DMMU, because the IMMU is mapping the code it |
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229 | * executes. |
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230 | * |
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231 | * [ Note that brave experiments with disabling the IMMU and using the |
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232 | * DMMU approach failed after a dozen of desparate days with only little |
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233 | * success. ] |
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234 | * |
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235 | * The approach used here is inspired from OpenBSD. First, the kernel |
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236 | * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and |
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237 | * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped |
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238 | * afterwards and replaced with the kernel permanent mapping. Finally, |
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239 | * the kernel switches back to context 0 and demaps context 1. |
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240 | * |
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241 | * Moreover, the IMMU requires use of the FLUSH instructions. But that |
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242 | * is OK because we always use operands with addresses already mapped by |
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243 | * the taken over DTLB. |
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244 | */ |
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245 | #if 0 |
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246 | set kernel_image_start, %g5 |
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247 | #endif |
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248 | #if defined (RTEMS) |
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249 | set _take_mmu, %g5 |
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250 | #endif |
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251 | /* |
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252 | ! write ITLB tag of context 1 |
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253 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
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254 | mov VA_DMMU_TAG_ACCESS, %g2 |
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255 | stxa %g1, [%g2] ASI_IMMU |
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256 | flush %g5 |
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257 | |
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258 | ! write ITLB data and install the temporary mapping in context 1 |
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259 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
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260 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
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261 | flush %g5 |
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262 | |
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263 | ! switch to context 1 |
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264 | mov MEM_CONTEXT_TEMP, %g1 |
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265 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
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266 | flush %g5 |
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267 | |
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268 | ! demap context 0 |
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269 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
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270 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
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271 | flush %g5 |
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272 | */ |
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273 | ! write ITLB tag of context 0 |
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274 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
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275 | mov VA_DMMU_TAG_ACCESS, %g2 |
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276 | stxa %g1, [%g2] ASI_IMMU |
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277 | flush %g5 |
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278 | |
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279 | ! write ITLB data and install the permanent kernel mapping in context 0 |
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280 | SET_TLB_DATA(g1, g2, TTE_L) ! use non-global mapping |
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281 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
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282 | flush %g5 |
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283 | /* |
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284 | ! enter nucleus - using context 0 |
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285 | wrpr %g0, 1, %tl |
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286 | |
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287 | ! demap context 1 |
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288 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
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289 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
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290 | flush %g5 |
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291 | |
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292 | ! set context 0 in the primary context register |
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293 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
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294 | flush %g5 |
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295 | |
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296 | ! leave nucleus - using primary context, i.e. context 0 |
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297 | wrpr %g0, 0, %tl |
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298 | |
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299 | wrpr %g0, 0, %wstate ! default spill/fill trap |
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300 | */ |
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301 | #if 0 |
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302 | brz %l7, 1f ! skip if you are not the bootstrap CPU |
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303 | nop |
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304 | |
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305 | /* |
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306 | * Save physmem_base for use by the mm subsystem. |
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307 | * %l6 contains starting physical address |
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308 | */ |
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309 | sethi %hi(physmem_base), %l4 |
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310 | stx %l6, [%l4 + %lo(physmem_base)] |
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311 | |
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312 | /* |
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313 | * Precompute kernel 8K TLB data template. |
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314 | * %l5 contains starting physical address |
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315 | * bits [(PHYSMEM_ADDR_SIZE - 1):13] |
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316 | */ |
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317 | sethi %hi(kernel_8k_tlb_data_template), %l4 |
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318 | ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3 |
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319 | or %l3, %l5, %l3 |
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320 | stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)] |
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321 | #endif |
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322 | |
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323 | /* |
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324 | * Flush D-Cache. |
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325 | */ |
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326 | call dcache_flush |
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327 | nop |
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328 | |
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329 | #if 0 |
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330 | /* |
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331 | * So far, we have not touched the stack. |
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332 | * It is a good idea to set the kernel stack to a known state now. |
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333 | */ |
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334 | sethi %hi(temporary_boot_stack), %sp |
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335 | or %sp, %lo(temporary_boot_stack), %sp |
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336 | sub %sp, STACK_BIAS, %sp |
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337 | |
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338 | sethi %hi(bootinfo), %o0 |
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339 | call memcpy ! copy bootinfo |
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340 | or %o0, %lo(bootinfo), %o0 |
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341 | |
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342 | call arch_pre_main |
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343 | nop |
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344 | |
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345 | call main_bsp |
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346 | nop |
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347 | #endif |
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348 | |
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349 | #if defined (RTEMS) |
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350 | ret |
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351 | restore |
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352 | #endif |
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353 | |
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354 | /* Not reached. */ |
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355 | |
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356 | 0: |
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357 | ba %xcc, 0b |
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358 | nop |
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359 | |
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360 | #if 0 |
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361 | 1: |
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362 | #ifdef CONFIG_SMP |
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363 | /* |
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364 | * Determine the width of the MID and save its mask to %g3. The width |
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365 | * is |
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366 | * * 5 for US and US-IIIi, |
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367 | * * 10 for US3 except US-IIIi. |
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368 | */ |
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369 | #if defined(US) |
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370 | mov 0x1f, %g3 |
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371 | #elif defined(US3) |
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372 | mov 0x3ff, %g3 |
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373 | rdpr %ver, %g2 |
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374 | sllx %g2, 16, %g2 |
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375 | srlx %g2, 48, %g2 |
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376 | cmp %g2, IMPL_ULTRASPARCIII_I |
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377 | move %xcc, 0x1f, %g3 |
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378 | #endif |
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379 | |
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380 | /* |
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381 | * Read MID from the processor. |
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382 | */ |
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383 | ldxa [%g0] ASI_ICBUS_CONFIG, %g1 |
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384 | srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1 |
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385 | and %g1, %g3, %g1 |
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386 | |
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387 | /* |
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388 | * Active loop for APs until the BSP picks them up. A processor cannot |
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389 | * leave the loop until the global variable 'waking_up_mid' equals its |
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390 | * MID. |
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391 | */ |
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392 | set waking_up_mid, %g2 |
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393 | 2: |
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394 | ldx [%g2], %g3 |
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395 | cmp %g3, %g1 |
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396 | bne %xcc, 2b |
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397 | nop |
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398 | |
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399 | /* |
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400 | * Configure stack for the AP. |
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401 | * The AP is expected to use the stack saved |
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402 | * in the ctx global variable. |
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403 | */ |
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404 | set ctx, %g1 |
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405 | add %g1, OFFSET_SP, %g1 |
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406 | ldx [%g1], %o6 |
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407 | |
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408 | call main_ap |
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409 | nop |
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410 | |
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411 | /* Not reached. */ |
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412 | #endif |
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413 | |
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414 | 0: |
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415 | ba %xcc, 0b |
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416 | nop |
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417 | |
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418 | |
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419 | .section K_DATA_START, "aw", @progbits |
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420 | |
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421 | /* |
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422 | * Create small stack to be used by the bootstrap processor. It is going to be |
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423 | * used only for a very limited period of time, but we switch to it anyway, |
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424 | * just to be sure we are properly initialized. |
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425 | */ |
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426 | |
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427 | #define INITIAL_STACK_SIZE 1024 |
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428 | |
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429 | .align STACK_ALIGNMENT |
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430 | .space INITIAL_STACK_SIZE |
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431 | .align STACK_ALIGNMENT |
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432 | temporary_boot_stack: |
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433 | .space STACK_WINDOW_SAVE_AREA_SIZE |
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434 | |
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435 | #endif /* 0 */ |
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436 | |
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437 | .data |
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438 | |
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439 | .align 8 |
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440 | .global physmem_base ! copy of the physical memory base address |
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441 | physmem_base: |
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442 | .quad 0 |
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443 | |
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444 | /* |
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445 | * The fast_data_access_mmu_miss_data_hi label and the end_of_identity and |
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446 | * kernel_8k_tlb_data_template variables are meant to stay together, |
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447 | * aligned on 16B boundary. |
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448 | */ |
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449 | .global fast_data_access_mmu_miss_data_hi |
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450 | .global end_of_identity |
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451 | .global kernel_8k_tlb_data_template |
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452 | |
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453 | .align 16 |
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454 | /* |
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455 | * This label is used by the fast_data_access_MMU_miss trap handler. |
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456 | */ |
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457 | fast_data_access_mmu_miss_data_hi: |
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458 | /* |
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459 | * This variable is used by the fast_data_access_MMU_miss trap handler. |
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460 | * In runtime, it is modified to contain the address of the end of physical |
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461 | * memory. |
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462 | */ |
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463 | end_of_identity: |
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464 | .quad -1 |
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465 | /* |
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466 | * This variable is used by the fast_data_access_MMU_miss trap handler. |
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467 | * In runtime, it is further modified to reflect the starting address of |
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468 | * physical memory. |
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469 | */ |
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470 | kernel_8k_tlb_data_template: |
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471 | #ifdef CONFIG_VIRT_IDX_DCACHE |
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472 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
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473 | TTE_CV | TTE_P | TTE_W) |
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474 | #else /* CONFIG_VIRT_IDX_DCACHE */ |
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475 | .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \ |
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476 | TTE_P | TTE_W) |
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477 | #endif /* CONFIG_VIRT_IDX_DCACHE */ |
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