source: rtems/c/src/lib/libbsp/sparc64/shared/helenos/kernel/sparc64/src/sun4u/takemmu.S @ 48449a8

4.115
Last change on this file since 48449a8 was 48449a8, checked in by Joel Sherrill <joel.sherrill@…>, on 10/06/11 at 16:46:36

2011-10-06 Gedare Bloom <giddyup44@…>

PR 1920/bsp

  • shared/helenos/kernel/sparc64/src/sun4u/takemmu.S, shared/start/start.S, shared/startup/bspgetworkarea.c, shared/startup/linkcmds: Fix BSP memory use to support more than 4 MB of RAM.
  • Property mode set to 100644
File size: 13.0 KB
Line 
1#
2# Copyright (c) 2005 Jakub Jermar
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions
7# are met:
8#
9# - Redistributions of source code must retain the above copyright
10#   notice, this list of conditions and the following disclaimer.
11# - Redistributions in binary form must reproduce the above copyright
12#   notice, this list of conditions and the following disclaimer in the
13#   documentation and/or other materials provided with the distribution.
14# - The name of the author may not be used to endorse or promote products
15#   derived from this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28
29/*
30 * $Id$
31 *
32 * This file originally is sparc64/src/sun4u/start.S
33 * A lot of changes are made to the code, because we only need the relevant
34 * portions for taking over the D- and I-MMUs.
35 *
36 */
37#define RTEMS
38
39#include <rtems/asm.h>
40
41/* RTEMS: moved all of these to a common include directory */
42#if 0
43#include <arch/arch.h>
44#include <arch/cpu.h>
45#include <arch/regdef.h>
46#endif
47#include <arch/boot.h>
48#include <arch/stack.h>
49
50#include <arch/mm/mmu.h>
51#include <arch/mm/tlb.h>
52#include <arch/mm/tte.h>
53
54#if 0
55#ifdef CONFIG_SMP
56#include <arch/context_offset.h>
57#endif
58#endif
59
60.register %g2, #scratch
61.register %g3, #scratch
62#if defined (RTEMS)
63.section BOOTSTRAP
64#endif
65
66#if 0
67.section K_TEXT_START, "ax"
68
69#define BSP_FLAG        1
70
71/*
72 * 2^PHYSMEM_ADDR_SIZE is the size of the physical address space on
73 * a given processor.
74 */
75#if defined (US)
76    #define PHYSMEM_ADDR_SIZE   41
77#elif defined (US3)
78    #define PHYSMEM_ADDR_SIZE   43
79#endif
80#endif
81
82#if defined (RTEMS)
83  #define PHYSMEM_ADDR_SIZE 43
84#endif
85
86#if 0
87/*
88 * Here is where the kernel is passed control from the boot loader.
89 *
90 * The registers are expected to be in this state:
91 * - %o0 starting address of physical memory + bootstrap processor flag
92 *      bits 63...1:    physical memory starting address / 2
93 *      bit 0:          non-zero on BSP processor, zero on AP processors
94 * - %o1 bootinfo structure address (BSP only)
95 * - %o2 bootinfo structure size (BSP only)
96 *
97 * Moreover, we depend on boot having established the following environment:
98 * - TLBs are on
99 * - identity mapping for the kernel image
100 */
101.global kernel_image_start
102kernel_image_start:
103        mov BSP_FLAG, %l0
104        and %o0, %l0, %l7                       ! l7 <= bootstrap processor?
105        andn %o0, %l0, %l6                      ! l6 <= start of physical memory
106
107        ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
108        srlx %l6, 13, %l5
109       
110        ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
111        sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
112        srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5     
113
114        /*
115         * Setup basic runtime environment.
116         */
117
118        wrpr %g0, NWINDOWS - 2, %cansave        ! set maximum saveable windows
119        wrpr %g0, 0, %canrestore                ! get rid of windows we will
120                                                ! never need again
121        wrpr %g0, 0, %otherwin                  ! make sure the window state is
122                                                ! consistent
123        wrpr %g0, NWINDOWS - 1, %cleanwin       ! prevent needless clean_window
124                                                ! traps for kernel
125                                               
126        wrpr %g0, 0, %wstate                    ! use default spill/fill trap
127
128        wrpr %g0, 0, %tl                        ! TL = 0, primary context
129                                                ! register is used
130
131        wrpr %g0, PSTATE_PRIV_BIT, %pstate      ! disable interrupts and disable
132                                                ! 32-bit address masking
133
134        wrpr %g0, 0, %pil                       ! intialize %pil
135#endif
136
137#if defined (RTEMS)
138  /* pass o0 as start of physical memory */
139.global _take_mmu
140_take_mmu:
141        save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
142  mov %i0, %l6
143#endif
144 
145  /* these are copied from above */
146  ! Get bits (PHYSMEM_ADDR_SIZE - 1):13 of physmem_base.
147  srlx %l6, 13, %l5
148
149  ! l5 <= physmem_base[(PHYSMEM_ADDR_SIZE - 1):13]
150  sllx %l5, 13 + (63 - (PHYSMEM_ADDR_SIZE - 1)), %l5
151  srlx %l5, 63 - (PHYSMEM_ADDR_SIZE - 1), %l5
152       
153  /*
154         * Switch to kernel trap table.
155         */
156        sethi %hi(trap_table), %g1
157        wrpr %g1, %lo(trap_table), %tba
158
159
160        /*
161         * Take over the DMMU by installing locked TTE entry identically
162         * mapping the first 4M of memory.
163         *
164         * In case of DMMU, no FLUSH instructions need to be issued. Because of
165         * that, the old DTLB contents can be demapped pretty straightforwardly
166         * and without causing any traps.
167         */
168
169        wr %g0, ASI_DMMU, %asi
170/*
171#define SET_TLB_DEMAP_CMD(r1, context_id) \
172        set (TLB_DEMAP_CONTEXT << TLB_DEMAP_TYPE_SHIFT) | (context_id << \
173                TLB_DEMAP_CONTEXT_SHIFT), %r1
174*/
175/*     
176        ! demap context 0
177        SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
178        stxa %g0, [%g1] ASI_DMMU_DEMAP                 
179        membar #Sync
180*/
181#define SET_TLB_TAG(xVMA, r1, context) \
182        set xVMA | (context << TLB_TAG_ACCESS_CONTEXT_SHIFT), %r1
183
184        ! write DTLB tag
185        SET_TLB_TAG(0x4000, g1, MEM_CONTEXT_KERNEL)
186        stxa %g1, [VA_DMMU_TAG_ACCESS] %asi                     
187        membar #Sync
188
189#ifdef CONFIG_VIRT_IDX_DCACHE
190#define TTE_LOW_DATA(imm)       (TTE_CP | TTE_CV | TTE_P | LMA | (imm))
191#else /* CONFIG_VIRT_IDX_DCACHE */
192#define TTE_LOW_DATA(imm)       (TTE_CP | TTE_P | LMA | (imm))
193#endif /* CONFIG_VIRT_IDX_DCACHE */
194
195#define SET_TLB_DATA(r1, r2, imm) \
196        set TTE_LOW_DATA(imm), %r1; \
197        or %r1, %l5, %r1; \
198        mov PAGESIZE_4M, %r2; \
199        sllx %r2, TTE_SIZE_SHIFT, %r2; \
200        or %r1, %r2, %r1; \
201        mov 1, %r2; \
202        sllx %r2, TTE_V_SHIFT, %r2; \
203        or %r1, %r2, %r1;
204       
205        ! write DTLB data and install the kernel mapping
206        SET_TLB_DATA(g1, g2, TTE_L | TTE_W)     ! use non-global mapping
207        stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG           
208        membar #Sync
209
210        /*
211         * Because we cannot use global mappings (because we want to have
212         * separate 64-bit address spaces for both the kernel and the
213         * userspace), we prepare the identity mapping also in context 1. This
214         * step is required by the code installing the ITLB mapping.
215         */
216/*      ! write DTLB tag of context 1 (i.e. MEM_CONTEXT_TEMP)
217        SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
218        stxa %g1, [VA_DMMU_TAG_ACCESS] %asi                     
219        membar #Sync
220
221        ! write DTLB data and install the kernel mapping in context 1
222        SET_TLB_DATA(g1, g2, TTE_W)                     ! use non-global mapping
223        stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG           
224        membar #Sync
225*/
226        /*
227         * Now is time to take over the IMMU. Unfortunatelly, it cannot be done
228         * as easily as the DMMU, because the IMMU is mapping the code it
229         * executes.
230         *
231         * [ Note that brave experiments with disabling the IMMU and using the
232         * DMMU approach failed after a dozen of desparate days with only little
233         * success. ]
234         *
235         * The approach used here is inspired from OpenBSD. First, the kernel
236         * creates IMMU mapping for itself in context 1 (MEM_CONTEXT_TEMP) and
237         * switches to it. Context 0 (MEM_CONTEXT_KERNEL) can be demapped
238         * afterwards and replaced with the kernel permanent mapping. Finally,
239         * the kernel switches back to context 0 and demaps context 1.
240         *
241         * Moreover, the IMMU requires use of the FLUSH instructions. But that
242         * is OK because we always use operands with addresses already mapped by
243         * the taken over DTLB.
244         */
245#if 0   
246        set kernel_image_start, %g5
247#endif
248#if defined (RTEMS)
249  set _take_mmu, %g5
250#endif
251/*     
252        ! write ITLB tag of context 1
253        SET_TLB_TAG(g1, MEM_CONTEXT_TEMP)
254        mov VA_DMMU_TAG_ACCESS, %g2
255        stxa %g1, [%g2] ASI_IMMU
256        flush %g5
257
258        ! write ITLB data and install the temporary mapping in context 1
259        SET_TLB_DATA(g1, g2, 0)                 ! use non-global mapping
260        stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG           
261        flush %g5
262       
263        ! switch to context 1
264        mov MEM_CONTEXT_TEMP, %g1
265        stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
266        flush %g5
267       
268        ! demap context 0
269        SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS)
270        stxa %g0, [%g1] ASI_IMMU_DEMAP                 
271        flush %g5
272*/
273        ! write ITLB tag of context 0
274        SET_TLB_TAG(0x4000, g1, MEM_CONTEXT_KERNEL)
275        mov VA_DMMU_TAG_ACCESS, %g2
276        stxa %g1, [%g2] ASI_IMMU
277        flush %g5
278
279        ! write ITLB data and install the permanent kernel mapping in context 0
280        SET_TLB_DATA(g1, g2, TTE_L)             ! use non-global mapping
281        stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG           
282        flush %g5
283
284  ! GAB: add more mappings for dmmu in 4 MB chunks
285  SET_TLB_TAG(0x404000, g1, MEM_CONTEXT_KERNEL)
286  stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
287  membar #Sync
288  set 0x400000, %g1
289  add %g1, %l5, %l5
290  SET_TLB_DATA(g1, g2, TTE_L | TTE_W)
291  stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
292  membar #Sync
293
294  SET_TLB_TAG(0x804000, g1, MEM_CONTEXT_KERNEL)
295  stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
296  membar #Sync
297  set 0x400000, %g1
298  add %g1, %l5, %l5
299  SET_TLB_DATA(g1, g2, TTE_L | TTE_W)
300  stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
301  membar #Sync
302
303  SET_TLB_TAG(0xc04000, g1, MEM_CONTEXT_KERNEL)
304  stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
305  membar #Sync
306  set 0x400000, %g1
307  add %g1, %l5, %l5
308  SET_TLB_DATA(g1, g2, TTE_L | TTE_W)
309  stxa %g1, [%g0] ASI_DTLB_DATA_IN_REG
310  membar #Sync
311
312
313/*
314        ! enter nucleus - using context 0
315        wrpr %g0, 1, %tl
316
317        ! demap context 1
318        SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY)
319        stxa %g0, [%g1] ASI_IMMU_DEMAP                 
320        flush %g5
321       
322        ! set context 0 in the primary context register
323        stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!!
324        flush %g5
325       
326        ! leave nucleus - using primary context, i.e. context 0
327        wrpr %g0, 0, %tl
328
329  wrpr %g0, 0, %wstate ! default spill/fill trap
330*/
331#if 0
332        brz %l7, 1f                             ! skip if you are not the bootstrap CPU
333        nop
334
335        /*
336         * Save physmem_base for use by the mm subsystem.
337         * %l6 contains starting physical address
338         */
339        sethi %hi(physmem_base), %l4
340        stx %l6, [%l4 + %lo(physmem_base)]
341
342        /*
343         * Precompute kernel 8K TLB data template.
344         * %l5 contains starting physical address
345         * bits [(PHYSMEM_ADDR_SIZE - 1):13]
346         */
347        sethi %hi(kernel_8k_tlb_data_template), %l4
348        ldx [%l4 + %lo(kernel_8k_tlb_data_template)], %l3
349        or %l3, %l5, %l3
350        stx %l3, [%l4 + %lo(kernel_8k_tlb_data_template)]
351#endif
352
353        /*
354         * Flush D-Cache.
355         */
356        call dcache_flush
357        nop
358
359#if 0
360        /*
361         * So far, we have not touched the stack.
362         * It is a good idea to set the kernel stack to a known state now.
363         */
364        sethi %hi(temporary_boot_stack), %sp
365        or %sp, %lo(temporary_boot_stack), %sp
366        sub %sp, STACK_BIAS, %sp
367
368        sethi %hi(bootinfo), %o0
369        call memcpy                             ! copy bootinfo
370        or %o0, %lo(bootinfo), %o0
371
372        call arch_pre_main
373        nop
374       
375        call main_bsp
376        nop
377#endif
378
379#if defined (RTEMS)
380  ret
381  restore
382#endif
383
384        /* Not reached. */
385
3860:
387        ba %xcc, 0b
388        nop
389
390#if 0
3911:
392#ifdef CONFIG_SMP
393        /*
394         * Determine the width of the MID and save its mask to %g3. The width
395         * is
396         *      * 5 for US and US-IIIi,
397         *      * 10 for US3 except US-IIIi.
398         */
399#if defined(US)
400        mov 0x1f, %g3
401#elif defined(US3)
402        mov 0x3ff, %g3
403        rdpr %ver, %g2
404        sllx %g2, 16, %g2
405        srlx %g2, 48, %g2
406        cmp %g2, IMPL_ULTRASPARCIII_I
407        move %xcc, 0x1f, %g3
408#endif
409
410        /*
411         * Read MID from the processor.
412         */
413        ldxa [%g0] ASI_ICBUS_CONFIG, %g1
414        srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1
415        and %g1, %g3, %g1
416
417        /*
418         * Active loop for APs until the BSP picks them up. A processor cannot
419         * leave the loop until the global variable 'waking_up_mid' equals its
420         * MID.
421         */
422        set waking_up_mid, %g2
4232:
424        ldx [%g2], %g3
425        cmp %g3, %g1
426        bne %xcc, 2b
427        nop
428
429        /*
430         * Configure stack for the AP.
431         * The AP is expected to use the stack saved
432         * in the ctx global variable.
433         */
434        set ctx, %g1
435        add %g1, OFFSET_SP, %g1
436        ldx [%g1], %o6
437
438        call main_ap
439        nop
440
441        /* Not reached. */
442#endif
443       
4440:
445        ba %xcc, 0b
446        nop
447
448
449.section K_DATA_START, "aw", @progbits
450
451/*
452 * Create small stack to be used by the bootstrap processor. It is going to be
453 * used only for a very limited period of time, but we switch to it anyway,
454 * just to be sure we are properly initialized.
455 */
456
457#define INITIAL_STACK_SIZE      1024
458
459.align STACK_ALIGNMENT
460        .space INITIAL_STACK_SIZE
461.align STACK_ALIGNMENT
462temporary_boot_stack:
463        .space STACK_WINDOW_SAVE_AREA_SIZE
464
465#endif /* 0 */
466
467.data
468
469.align 8
470.global physmem_base            ! copy of the physical memory base address
471physmem_base:
472        .quad 0
473
474/*
475 * The fast_data_access_mmu_miss_data_hi label and the end_of_identity and
476 * kernel_8k_tlb_data_template variables are meant to stay together,
477 * aligned on 16B boundary.
478 */
479.global fast_data_access_mmu_miss_data_hi
480.global end_of_identity
481.global kernel_8k_tlb_data_template
482
483.align 16
484/*
485 * This label is used by the fast_data_access_MMU_miss trap handler.
486 */
487fast_data_access_mmu_miss_data_hi:
488/*
489 * This variable is used by the fast_data_access_MMU_miss trap handler.
490 * In runtime, it is modified to contain the address of the end of physical
491 * memory.
492 */
493end_of_identity:
494        .quad -1
495/*
496 * This variable is used by the fast_data_access_MMU_miss trap handler.
497 * In runtime, it is further modified to reflect the starting address of
498 * physical memory.
499 */
500kernel_8k_tlb_data_template:
501#ifdef CONFIG_VIRT_IDX_DCACHE
502        .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \
503                 TTE_CV | TTE_P | TTE_W)
504#else /* CONFIG_VIRT_IDX_DCACHE */
505        .quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | \
506                TTE_P | TTE_W)
507#endif /* CONFIG_VIRT_IDX_DCACHE */
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