source: rtems/c/src/lib/libbsp/sparc64/shared/clock/ckinit.c @ 9d090fb7

4.115
Last change on this file since 9d090fb7 was 9d090fb7, checked in by Gedare Bloom <gedare@…>, on Feb 23, 2015 at 8:42:59 PM

sparc64: fix copyright notices.

The sparc64 port had some incorrect copyright notices affixed to
source code files.

  • Property mode set to 100644
File size: 2.9 KB
Line 
1/*  ckinit.c
2 *
3 *  This file provides a template for the clock device driver initialization.
4 *
5 *  Modified for sun4v - niagara
6 */
7
8/*
9 *  Copyright (c) 2010 Gedare Bloom.
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.org/license/LICENSE.
14 */
15
16#include <stdlib.h>
17
18#include <rtems.h>
19#include <bsp.h>
20#include <bspopts.h>
21#include <boot/ofw.h>
22
23/* This is default frequency for simics simulator of niagara. Use the
24 * get_Frequency function to determine the CPU clock frequency at runtime.
25 */
26#define CPU_FREQ (5000000)
27
28uint64_t sparc64_cycles_per_tick;
29
30/* TICK_CMPR and STICK_CMPR trigger soft interrupt 14 */
31#define CLOCK_VECTOR SPARC_SYNCHRONOUS_TRAP(0x4E)
32
33static unsigned int get_Frequency(void)
34{
35  phandle root = ofw_find_device("/");
36  unsigned int freq;
37
38  if (ofw_get_property(root, "clock-frequency", &freq, sizeof(freq)) <= 0) {
39    printk("Unable to determine frequency, default: 0x%x\n",CPU_FREQ);
40    return CPU_FREQ;
41  }
42
43  return freq;
44}
45
46static void Clock_driver_support_at_tick(void)
47{
48  uint64_t tick_reg;
49  int bit_mask;
50  uint64_t pil_reg;
51
52  bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14);
53  sparc64_clear_interrupt_bits(bit_mask);
54
55  sparc64_get_pil(pil_reg);
56  if(pil_reg == 0xe) { /* 0xe is the tick compare interrupt (softint(14)) */
57    pil_reg--;
58    sparc64_set_pil(pil_reg); /* enable the next timer interrupt */
59  }
60  /* Note: sun4v uses stick_cmpr for clock driver for M5 simulator, which
61   * does not currently have tick_cmpr implemented */
62  /* TODO: this could be more efficiently implemented as a single assembly
63   * inline */
64#if defined (SUN4U)
65  sparc64_read_tick(tick_reg);
66#elif defined (SUN4V)
67  sparc64_read_stick(tick_reg);
68#endif
69  tick_reg &= ~(1UL<<63); /* mask out NPT bit, prevents int_dis from being set */
70
71  tick_reg += sparc64_cycles_per_tick;
72
73#if defined (SUN4U)
74  sparc64_write_tick_cmpr(tick_reg);
75#elif defined (SUN4V)
76  sparc64_write_stick_cmpr(tick_reg);
77#endif
78}
79
80#define Clock_driver_support_install_isr(_new, _old) \
81  do { \
82    _old = set_vector( _new, CLOCK_VECTOR, 1 ); \
83  } while ( 0 )
84
85static void Clock_driver_support_initialize_hardware(void)
86{
87  uint64_t tick_reg;
88  int bit_mask;
89
90  bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14);
91  sparc64_clear_interrupt_bits(bit_mask);
92
93  sparc64_cycles_per_tick =
94    rtems_configuration_get_microseconds_per_tick()*(get_Frequency()/1000000);
95
96#if defined (SUN4U)
97  sparc64_read_tick(tick_reg);
98#elif defined (SUN4V)
99  sparc64_read_stick(tick_reg);
100#endif
101
102  tick_reg &= ~(1UL<<63); /* mask out NPT bit, prevents int_dis from being set */
103  tick_reg += sparc64_cycles_per_tick;
104
105#if defined (SUN4U)
106  sparc64_write_tick_cmpr(tick_reg);
107#elif defined (SUN4V)
108  sparc64_write_stick_cmpr(tick_reg);
109#endif
110}
111
112#define Clock_driver_support_shutdown_hardware( ) \
113  do { \
114    \
115  } while ( 0 )
116
117#include "../../../shared/clockdrv_shell.h"
118
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