source: rtems/c/src/lib/libbsp/sparc64/shared/clock/ckinit.c @ 46e72c8

4.115
Last change on this file since 46e72c8 was 46e72c8, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 7, 2014 at 2:36:15 PM

sparc64/shared/clock/ckinit.c: Clean up formatting

  • Property mode set to 100644
File size: 3.0 KB
Line 
1/*  ckinit.c
2 *
3 *  This file provides a template for the clock device driver initialization.
4 *
5 *  Modified for sun4v - niagara
6 */
7
8/*
9 *  COPYRIGHT (c) 1989-1999.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  Modifications Copyright (c) 2010 Gedare Bloom.
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#include <stdlib.h>
20
21#include <rtems.h>
22#include <bsp.h>
23#include <bspopts.h>
24#include <boot/ofw.h>
25
26/* This is default frequency for simics simulator of niagara. Use the
27 * get_Frequency function to determine the CPU clock frequency at runtime.
28 */
29#define CPU_FREQ (5000000)
30
31uint64_t sparc64_cycles_per_tick;
32
33/* TICK_CMPR and STICK_CMPR trigger soft interrupt 14 */
34#define CLOCK_VECTOR SPARC_SYNCHRONOUS_TRAP(0x4E)
35
36static unsigned int get_Frequency(void)
37{
38  phandle root = ofw_find_device("/");
39  unsigned int freq;
40
41  if (ofw_get_property(root, "clock-frequency", &freq, sizeof(freq)) <= 0) {
42    printk("Unable to determine frequency, default: 0x%x\n",CPU_FREQ);
43    return CPU_FREQ;
44  }
45
46  return freq;
47}
48
49void Clock_driver_support_at_tick(void)
50{
51  uint64_t tick_reg;
52  int bit_mask;
53  uint64_t pil_reg;
54
55  bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14);
56  sparc64_clear_interrupt_bits(bit_mask);
57
58  sparc64_get_pil(pil_reg);
59  if(pil_reg == 0xe) { /* 0xe is the tick compare interrupt (softint(14)) */
60    pil_reg--;
61    sparc64_set_pil(pil_reg); /* enable the next timer interrupt */
62  }
63  /* Note: sun4v uses stick_cmpr for clock driver for M5 simulator, which
64   * does not currently have tick_cmpr implemented */
65  /* TODO: this could be more efficiently implemented as a single assembly
66   * inline */
67#if defined (SUN4U)
68  sparc64_read_tick(tick_reg);
69#elif defined (SUN4V)
70  sparc64_read_stick(tick_reg);
71#endif
72  tick_reg &= ~(1UL<<63); /* mask out NPT bit, prevents int_dis from being set */
73
74  tick_reg += sparc64_cycles_per_tick;
75
76#if defined (SUN4U)
77  sparc64_write_tick_cmpr(tick_reg);
78#elif defined (SUN4V)
79  sparc64_write_stick_cmpr(tick_reg);
80#endif
81}
82
83#define Clock_driver_support_install_isr(_new, _old) \
84  do { \
85    _old = set_vector( _new, CLOCK_VECTOR, 1 ); \
86  } while ( 0 )
87
88void Clock_driver_support_initialize_hardware(void)
89{
90  uint64_t tick_reg;
91  int bit_mask;
92
93  bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14);
94  sparc64_clear_interrupt_bits(bit_mask);
95
96  sparc64_cycles_per_tick =
97    rtems_configuration_get_microseconds_per_tick()*(get_Frequency()/1000000);
98
99#if defined (SUN4U)
100  sparc64_read_tick(tick_reg);
101#elif defined (SUN4V)
102  sparc64_read_stick(tick_reg);
103#endif
104
105  tick_reg &= ~(1UL<<63); /* mask out NPT bit, prevents int_dis from being set */
106  tick_reg += sparc64_cycles_per_tick;
107
108#if defined (SUN4U)
109  sparc64_write_tick_cmpr(tick_reg);
110#elif defined (SUN4V)
111  sparc64_write_stick_cmpr(tick_reg);
112#endif
113}
114
115#define Clock_driver_support_shutdown_hardware( ) \
116  do { \
117    \
118  } while ( 0 )
119
120#include "../../../shared/clockdrv_shell.h"
121
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