1 | /* ckinit.c |
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2 | * |
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3 | * This file provides a template for the clock device driver initialization. |
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4 | * |
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5 | * Modified for sun4v - niagara |
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6 | */ |
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7 | |
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8 | /* |
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9 | * COPYRIGHT (c) 1989-1999. |
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10 | * On-Line Applications Research Corporation (OAR). |
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11 | * |
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12 | * Modifications Copyright (c) 2010 Gedare Bloom. |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | */ |
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18 | |
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19 | #include <stdlib.h> |
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20 | |
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21 | #include <rtems.h> |
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22 | #include <bsp.h> |
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23 | #include <bspopts.h> |
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24 | #include <boot/ofw.h> |
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25 | |
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26 | /* This is default frequency for simics simulator of niagara. Use the |
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27 | * get_Frequency function to determine the CPU clock frequency at runtime. |
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28 | */ |
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29 | #define CPU_FREQ (5000000) |
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30 | |
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31 | uint64_t sparc64_cycles_per_tick; |
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32 | |
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33 | /* TICK_CMPR and STICK_CMPR trigger soft interrupt 14 */ |
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34 | #define CLOCK_VECTOR SPARC_SYNCHRONOUS_TRAP(0x4E) |
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35 | |
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36 | static unsigned int get_Frequency(void) |
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37 | { |
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38 | phandle root = ofw_find_device("/"); |
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39 | unsigned int freq; |
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40 | |
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41 | if (ofw_get_property(root, "clock-frequency", &freq, sizeof(freq)) <= 0) { |
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42 | printk("Unable to determine frequency, default: 0x%x\n",CPU_FREQ); |
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43 | return CPU_FREQ; |
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44 | } |
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45 | |
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46 | return freq; |
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47 | } |
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48 | |
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49 | void Clock_driver_support_at_tick(void) |
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50 | { |
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51 | uint64_t tick_reg; |
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52 | int bit_mask; |
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53 | uint64_t pil_reg; |
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54 | |
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55 | bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14); |
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56 | sparc64_clear_interrupt_bits(bit_mask); |
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57 | |
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58 | sparc64_get_pil(pil_reg); |
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59 | if(pil_reg == 0xe) { /* 0xe is the tick compare interrupt (softint(14)) */ |
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60 | pil_reg--; |
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61 | sparc64_set_pil(pil_reg); /* enable the next timer interrupt */ |
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62 | } |
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63 | /* Note: sun4v uses stick_cmpr for clock driver for M5 simulator, which |
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64 | * does not currently have tick_cmpr implemented */ |
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65 | /* TODO: this could be more efficiently implemented as a single assembly |
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66 | * inline */ |
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67 | #if defined (SUN4U) |
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68 | sparc64_read_tick(tick_reg); |
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69 | #elif defined (SUN4V) |
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70 | sparc64_read_stick(tick_reg); |
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71 | #endif |
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72 | tick_reg &= ~(1UL<<63); /* mask out NPT bit, prevents int_dis from being set */ |
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73 | |
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74 | tick_reg += sparc64_cycles_per_tick; |
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75 | |
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76 | #if defined (SUN4U) |
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77 | sparc64_write_tick_cmpr(tick_reg); |
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78 | #elif defined (SUN4V) |
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79 | sparc64_write_stick_cmpr(tick_reg); |
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80 | #endif |
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81 | } |
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82 | |
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83 | #define Clock_driver_support_install_isr(_new, _old) \ |
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84 | do { \ |
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85 | _old = set_vector( _new, CLOCK_VECTOR, 1 ); \ |
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86 | } while ( 0 ) |
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87 | |
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88 | void Clock_driver_support_initialize_hardware(void) |
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89 | { |
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90 | uint64_t tick_reg; |
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91 | int bit_mask; |
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92 | |
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93 | bit_mask = SPARC_SOFTINT_TM_MASK | SPARC_SOFTINT_SM_MASK | (1<<14); |
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94 | sparc64_clear_interrupt_bits(bit_mask); |
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95 | |
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96 | sparc64_cycles_per_tick = |
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97 | rtems_configuration_get_microseconds_per_tick()*(get_Frequency()/1000000); |
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98 | |
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99 | #if defined (SUN4U) |
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100 | sparc64_read_tick(tick_reg); |
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101 | #elif defined (SUN4V) |
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102 | sparc64_read_stick(tick_reg); |
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103 | #endif |
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104 | |
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105 | tick_reg &= ~(1UL<<63); /* mask out NPT bit, prevents int_dis from being set */ |
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106 | tick_reg += sparc64_cycles_per_tick; |
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107 | |
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108 | #if defined (SUN4U) |
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109 | sparc64_write_tick_cmpr(tick_reg); |
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110 | #elif defined (SUN4V) |
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111 | sparc64_write_stick_cmpr(tick_reg); |
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112 | #endif |
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113 | } |
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114 | |
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115 | #define Clock_driver_support_shutdown_hardware( ) \ |
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116 | do { \ |
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117 | \ |
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118 | } while ( 0 ) |
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119 | |
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120 | #include "../../../shared/clockdrv_shell.h" |
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121 | |
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