4.115
Last change
on this file since 4d6f5f5 was
4d6f5f5,
checked in by Joel Sherrill <joel.sherrill@…>, on 06/17/10 at 16:20:34
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2010-06-17 Joel Sherrill <joel.sherrill@…>
- ChangeLog?, Makefile.am, README, bsp_specs, configure.ac,
preinstall.am, include/bsp.h, include/tm27.h,
make/custom/niagara.cfg, start/bspinit.S: New files.
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-
Property mode set to
100644
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File size:
1.4 KB
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1 | # |
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2 | # $Id$ |
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3 | # |
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4 | |
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5 | BSP NAME: niagara |
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6 | BOARD: |
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7 | BUS: n/a |
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8 | CPU FAMILY: SPARC V9 with UltraSPARC Architecture 2005 (a.k.a. sun4v) |
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9 | CPU: UltraSPARC T1 (OpenSPARC T1) |
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10 | COPROCESSORS: |
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11 | MODE: n/a |
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12 | |
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13 | DEBUG MONITOR: |
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14 | |
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15 | PERIPHERALS |
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16 | =========== |
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17 | TIMERS: TICK and STICK registers (ASRs 4 and 24) |
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18 | RESOLUTION: CPU clock resolution |
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19 | SERIAL PORTS: |
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20 | REAL-TIME CLOCK: |
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21 | DMA: none |
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22 | VIDEO: none |
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23 | SCSI: none |
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24 | NETWORKING: none |
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25 | |
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26 | DRIVER INFORMATION |
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27 | ================== |
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28 | CLOCK DRIVER: |
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29 | IOSUPP DRIVER: |
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30 | SHMSUPP: |
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31 | TIMER DRIVER: |
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32 | TTY DRIVER: |
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33 | |
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34 | STDIO |
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35 | ===== |
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36 | PORT: |
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37 | ELECTRICAL: |
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38 | BAUD: |
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39 | BITS PER CHARACTER: |
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40 | PARITY: |
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41 | STOP BITS: |
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42 | |
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43 | NOTES |
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44 | ===== |
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45 | |
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46 | Board description |
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47 | ----------------- |
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48 | clock rate: |
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49 | bus width: |
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50 | ROM: |
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51 | RAM: |
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52 | |
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53 | This BSP is designed to operate on the UltraSPARC T1 (Niagara) SPARC64 |
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54 | and similar processors. |
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55 | |
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56 | This BSP has been run on the Simics simulator with the niagara target, which |
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57 | simulates the OpenSPARC T1 Niagara implementation. |
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58 | |
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59 | This BSP has been run on the M5 simulator with the SPARC_FS target, which |
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60 | simulates the OpenSPARC T1 Niagara implementation. |
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61 | |
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62 | Simics: |
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63 | A commercially available simulator licensed by Virtutech. |
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64 | https://www.simics.net/ |
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65 | |
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66 | M5: |
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67 | An open-source simulator. |
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68 | http://www.m5sim.org/wiki/index.php/Main_Page |
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69 | |
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