Context Navigation

start.S @ 6930aa7f

4.115

Last change on this file since 6930aa7f was 348d1812, checked in by Daniel Hellstrom <daniel@…>, on 05/27/14 at 09:15:46

SPARC: window overflow optimization

I see no need for waiting the 3 instruction delay for wim to be
written in this case, since the STD after does not depend on WIM

Property mode set to 100644

File size: 12.6 KB

Line
1	/**
2	* Common start code for SPARC.
3	*
4	* This is based on the file srt0.s provided with the binary
5	* distribution of the SPARC Instruction Simulator (SIS) found
6	* at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32.
7	*/
8
9	/*
10	* COPYRIGHT (c) 1989-2011.
11	* On-Line Applications Research Corporation (OAR).
12	*
13	* The license and distribution terms for this file may be
14	* found in the file LICENSE in this distribution or at
15	* http://www.rtems.org/license/LICENSE.
16	*/
17
18	#include <rtems/asm.h>
19	#include <rtems/score/percpu.h>
20	#include <bspopts.h>
21
22	#if defined(RTEMS_SMP) && defined(BSP_LEON3_SMP)
23	#define START_LEON3_ENABLE_SMP
24	#endif
25
26	/*
27	* Unexpected trap will halt the processor by forcing it to error state
28	*/
29	#define BAD_TRAP \
30	ta 0; \
31	nop; \
32	nop; \
33	nop;
34
35	/*
36	* System call optimized trap table entry
37	*/
38	#define SYSCALL_TRAP(_vector, _handler) \
39	mov %psr, %l0 ; \
40	sethi %hi(_handler), %l4 ; \
41	jmp %l4+%lo(_handler); \
42	subcc %g1, 3, %g0; ! prepare for syscall 3 check
43
44	/*
45	* Window Overflow optimized trap table entry
46	*/
47	#define WOTRAP(_vector, _handler) \
48	sethi %hi(_handler), %l4; \
49	jmp %l4+%lo(_handler); \
50	save; \
51	nop
52
53	/*
54	* Software trap. Treat as BAD_TRAP for the time being...
55	*/
56
57	#define SOFT_TRAP BAD_TRAP
58
59	.seg "text"
60	PUBLIC(start)
61	.global start, __bsp_mem_init
62
63	SYM(start):
64	start:
65
66	/*
67	* The trap table has to be the first code in a boot PROM. But because
68	* the Memory Configuration comes up thinking we only have 4K of PROM, we
69	* cannot have a full trap table and still have room left over to
70	* reprogram the Memory Configuration register correctly. This file
71	* uses an abbreviated trap which has every entry which might be used
72	* before RTEMS installs its own trap table.
73	*/
74
75	PUBLIC(trap_table)
76	SYM(trap_table):
77
78	RTRAP( 0, SYM(hard_reset) ); ! 00 reset trap
79	BAD_TRAP; ! 01 instruction access
80	! exception
81	BAD_TRAP; ! 02 illegal instruction
82	BAD_TRAP; ! 03 privileged instruction
83	BAD_TRAP; ! 04 fp disabled
84	WOTRAP(5, SYM(window_overflow_trap_handler)); ! 05 window overflow
85	TRAP( 6, SYM(window_underflow_trap_handler) );! 06 window underflow
86	BAD_TRAP; ! 07 memory address not aligned
87	BAD_TRAP; ! 08 fp exception
88	BAD_TRAP; ! 09 data access exception
89	BAD_TRAP; ! 0A tag overflow
90	BAD_TRAP; ! 0B undefined
91	BAD_TRAP; ! 0C undefined
92	BAD_TRAP; ! 0D undefined
93	BAD_TRAP; ! 0E undefined
94	BAD_TRAP; ! 0F undefined
95	BAD_TRAP; ! 10 undefined
96
97	/*
98	* ERC32 defined traps
99	*/
100
101	BAD_TRAP; ! 11 masked errors
102	BAD_TRAP; ! 12 external 1
103	BAD_TRAP; ! 13 external 2
104	BAD_TRAP; ! 14 UART A RX/TX
105	BAD_TRAP; ! 15 UART B RX/TX
106	BAD_TRAP; ! 16 correctable memory error
107	BAD_TRAP; ! 17 UART error
108	BAD_TRAP; ! 18 DMA access error
109	BAD_TRAP; ! 19 DMA timeout
110	BAD_TRAP; ! 1A external 3
111	BAD_TRAP; ! 1B external 4
112	BAD_TRAP; ! 1C general purpose timer
113	BAD_TRAP; ! 1D real time clock
114	BAD_TRAP; ! 1E external 5
115	BAD_TRAP; ! 1F watchdog timeout
116
117	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 20 - 23 undefined
118	BAD_TRAP; ! 24 cp_disabled
119	BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 25 - 27 undefined
120	BAD_TRAP; ! 28 cp_exception
121	BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 29 - 2B undefined
122	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 2C - 2F undefined
123	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30 - 33 undefined
124	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34 - 37 undefined
125	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38 - 3B undefined
126	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3C - 3F undefined
127	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40 - 43 undefined
128	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44 - 47 undefined
129	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48 - 4B undefined
130	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4C - 4F undefined
131	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50 - 53 undefined
132	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54 - 57 undefined
133	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58 - 5B undefined
134	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5C - 5F undefined
135	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60 - 63 undefined
136	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64 - 67 undefined
137	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68 - 6B undefined
138	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6C - 6F undefined
139	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70 - 73 undefined
140	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74 - 77 undefined
141	BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78 - 7B undefined
142
143	/*
144	This is a sad patch to make sure that we know where the
145	MEC timer control register mirror is so we can stop the timers
146	from an external debugger. It is needed because the control
147	register is write-only. Trap 0x7C cannot occure in ERC32...
148
149	We also use this location to store the last location of the
150	usable RAM in order not to overwrite the remote debugger with
151	the RTEMS work-space area.
152
153	*/
154
155	.global SYM(_ERC32_MEC_Timer_Control_Mirror), SYM(rdb_start), SYM(CLOCK_SPEED)
156
157	SYM(rdb_start):
158	SYM(_ERC32_MEC_Timer_Control_Mirror):
159
160	BAD_TRAP; BAD_TRAP; ! 7C - 7D undefined
161
162	SYM(CLOCK_SPEED):
163
164	.word 0x0a, 0, 0, 0 ! 7E (10 MHz default)
165
166	BAD_TRAP; ! 7F undefined
167
168	/*
169	* Software traps
170	*
171	* NOTE: At the risk of being redundant... this is not a full
172	* table. The setjmp on the SPARC requires a window flush trap
173	* handler and RTEMS will preserve the entries that were
174	* installed before.
175	*/
176
177	SYSCALL_TRAP( 0x80, SYM(syscall) ); ! 80 syscall SW trap
178	SOFT_TRAP; SOFT_TRAP; ! 81 - 82
179	TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap
180
181	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84 - 87
182	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88 - 8B
183	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8C - 8F
184	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90 - 93
185	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94 - 97
186	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98 - 9B
187	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9C - 9F
188	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A0 - A3
189	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A4 - A7
190	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A8 - AB
191	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! AC - AF
192	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B0 - B3
193	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B4 - B7
194	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B8 - BB
195	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! BC - BF
196	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C0 - C3
197	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C4 - C7
198	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C8 - CB
199	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! CC - CF
200	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D0 - D3
201	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D4 - D7
202	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D8 - DB
203	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! DC - DF
204	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E0 - E3
205	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E4 - E7
206	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E8 - EB
207	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! EC - EF
208	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F0 - F3
209	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F4 - F7
210	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F8 - FB
211	SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! FC - FF
212
213	/*
214	* This is the hard reset code.
215	*/
216
217	#define PSR_INIT 0x10c0 /* Disable traps, set s and ps */
218	#define WIM_INIT 2
219	#define STACK_SIZE 16 * 1024
220
221	PUBLIC(hard_reset)
222	SYM(hard_reset):
223
224	/* Common initialisation */
225
226	set SYM(trap_table), %g1 ! Initialize TBR
227	mov %g1, %tbr
228
229	mov %psr, %g1 ! Initialize WIM
230	add %g1, 1, %g2
231	and %g2, 0x7, %g2
232	set 1, %g3
233	sll %g3, %g2, %g3
234	mov %g3, %wim
235
236	or %g1, 0xf20, %g1
237	wr %g1, %psr ! enable traps and disable ints
238
239	nop
240	nop
241	nop
242
243	sethi %hi(_Per_CPU_Information), %g6 ! get per-CPU control
244	add %g6, %lo(_Per_CPU_Information), %g6
245
246	#if defined(START_LEON3_ENABLE_SMP)
247	rd %asr17, %o0 ! get CPU identifier
248	srl %o0, LEON3_ASR17_PROCESSOR_INDEX_SHIFT, %o0
249
250	cmp %o0, 0
251	beq cpu0
252	nop
253
254	sll %o0, PER_CPU_CONTROL_SIZE_LOG2, %l0
255	add %g6, %l0, %g6
256
257	ld [%g6 + PER_CPU_INTERRUPT_STACK_HIGH], %sp ! set stack pointer
258	sub %sp, 4, %sp ! stack starts at end of area - 4
259	andn %sp, 0x0f, %sp ! align stack on 16-byte boundary
260	mov %sp, %fp ! set frame pointer
261
262	call SYM(bsp_start_on_secondary_processor) ! does not return
263	sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
264	cpu0:
265	#endif
266
267	set (SYM(rdb_start)), %g5 ! End of RAM
268	st %sp, [%g5]
269	sub %sp, 4, %sp ! stack starts at end of RAM - 4
270	andn %sp, 0x0f, %sp ! align stack on 16-byte boundary
271	mov %sp, %fp ! Set frame pointer
272	nop
273
274	#if ENABLE_SIS_QUIRKS==1
275
276	#include <erc32.h>
277
278	/* Check if MEC is initialised. If not, this means that we are
279	running on the simulator. Initiate some of the parameters
280	that are done by the boot-prom otherwise.
281	*/
282
283	set SYM(ERC32_MEC), %g3 ! g3 = base address of peripherals
284	ld [%g3], %g2
285	set 0xfe080000, %g1
286	andcc %g1, %g2, %g0
287	bne 2f
288
289	/* Set the correct memory size in MEC memory config register */
290
291	set SYM(PROM_SIZE), %l0
292	set 0, %l1
293	srl %l0, 18, %l0
294	1:
295	tst %l0
296	srl %l0, 1, %l0
297	bne,a 1b
298	inc %l1
299	sll %l1, 8, %l1
300
301	set SYM(RAM_SIZE), %l0
302	srl %l0, 19, %l0
303	1:
304	tst %l0
305	srl %l0, 1, %l0
306	bne,a 1b
307	inc %l1
308	sll %l1, 10, %l1
309
310	! set the Memory Configuration
311	st %l1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ]
312	!DISABLE THE HARDWARE WATCHDOG
313	st %g0, [ %g3 + ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET ]
314	!Reduce the number of wait states to 0 for all memory areas.
315	st %g0, [ %g3 + ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET ]
316
317	set SYM(RAM_START), %l1 ! Cannot use RAM_END due to bug in linker
318	set SYM(RAM_SIZE), %l2
319	add %l1, %l2, %sp
320	st %sp, [%g5]
321
322
323	set SYM(CLOCK_SPEED), %g5 ! Use 14 MHz in simulator
324	set 14, %g1
325	st %g1, [%g5]
326
327	2:
328	#endif
329
330	/*
331	* Copy the initialized data to RAM
332	*
333	* FROM: _endtext
334	* TO: _data_start
335	* LENGTH: (__bss_start - _data_start) bytes
336	*/
337
338	sethi %hi(_endtext),%g1
339	or %g1,%lo(_endtext),%g1 ! g1 = start of initialized data in ROM
340
341	sethi %hi(_data_start),%g3
342	or %g3,%lo(_data_start),%g3 ! g3 = start of initialized data in RAM
343
344	sethi %hi(__bss_start), %g2
345	or %g2,%lo(__bss_start),%g2 ! g2 = end of initialized data in RAM
346
347	cmp %g1, %g3
348	be 1f
349	nop
350
351	copy_data:
352	ldd [%g1], %g4
353	std %g4 , [%g3] ! copy this double word
354	add %g3, 8, %g3 ! bump the destination pointer
355	add %g1, 8, %g1 ! bump the source pointer
356	cmp %g3, %g2 ! Is the pointer past the end of dest?
357	bl copy_data
358	nop
359
360	/* clear the bss */
361	1:
362
363	sethi %hi(_end),%g3
364	or %g3,%lo(_end),%g3 ! g3 = end of bss
365	mov %g0,%g1 ! so std has two zeros
366	zerobss:
367	std %g0,[%g2]
368	add %g2,8,%g2
369	cmp %g2,%g3
370	bleu,a zerobss
371	nop
372
373	mov %0, %o0 ! command line
374	call SYM(boot_card) ! does not return
375	sub %sp, 0x60, %sp ! room for boot_card to save args
376
377	/* end of file */

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Original Format