1 | /* |
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2 | * start.s |
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3 | * |
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4 | * Common start code for SPARC. |
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5 | * |
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6 | * This is based on the file srt0.s provided with the binary |
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7 | * distribution of the SPARC Instruction Simulator (SIS) found |
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8 | * at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32. |
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9 | * |
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10 | * COPYRIGHT (c) 1989-2006. |
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11 | * On-Line Applications Research Corporation (OAR). |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.com/license/LICENSE. |
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16 | * |
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17 | * $Id$ |
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18 | */ |
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19 | |
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20 | #include <rtems/asm.h> |
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21 | #include <bspopts.h> |
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22 | |
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23 | /* |
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24 | * Unexpected trap will halt the processor by forcing it to error state |
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25 | */ |
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26 | |
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27 | #define BAD_TRAP \ |
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28 | ta 0; \ |
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29 | nop; \ |
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30 | nop; \ |
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31 | nop; |
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32 | |
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33 | /* |
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34 | * Software trap. Treat as BAD_TRAP for the time being... |
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35 | */ |
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36 | |
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37 | #define SOFT_TRAP BAD_TRAP |
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38 | |
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39 | .seg "text" |
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40 | PUBLIC(start) |
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41 | .global start, __bsp_mem_init |
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42 | |
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43 | SYM(start): |
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44 | start: |
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45 | |
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46 | /* |
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47 | * The trap table has to be the first code in a boot PROM. But because |
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48 | * the Memory Configuration comes up thinking we only have 4K of PROM, we |
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49 | * cannot have a full trap table and still have room left over to |
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50 | * reprogram the Memory Configuration register correctly. This file |
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51 | * uses an abbreviated trap which has every entry which might be used |
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52 | * before RTEMS installs its own trap table. |
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53 | */ |
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54 | |
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55 | PUBLIC(trap_table) |
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56 | SYM(trap_table): |
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57 | |
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58 | RTRAP( 0, SYM(hard_reset) ); ! 00 reset trap |
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59 | BAD_TRAP; ! 01 instruction access |
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60 | ! exception |
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61 | BAD_TRAP; ! 02 illegal instruction |
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62 | BAD_TRAP; ! 03 privileged instruction |
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63 | BAD_TRAP; ! 04 fp disabled |
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64 | TRAP( 5, SYM(window_overflow_trap_handler) ); ! 05 window overflow |
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65 | TRAP( 6, SYM(window_underflow_trap_handler) );! 06 window underflow |
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66 | BAD_TRAP; ! 07 memory address not aligned |
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67 | BAD_TRAP; ! 08 fp exception |
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68 | BAD_TRAP; ! 09 data access exception |
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69 | BAD_TRAP; ! 0A tag overflow |
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70 | BAD_TRAP; ! 0B undefined |
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71 | BAD_TRAP; ! 0C undefined |
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72 | BAD_TRAP; ! 0D undefined |
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73 | BAD_TRAP; ! 0E undefined |
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74 | BAD_TRAP; ! 0F undefined |
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75 | BAD_TRAP; ! 10 undefined |
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76 | |
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77 | /* |
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78 | * ERC32 defined traps |
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79 | */ |
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80 | |
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81 | BAD_TRAP; ! 11 masked errors |
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82 | BAD_TRAP; ! 12 external 1 |
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83 | BAD_TRAP; ! 13 external 2 |
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84 | BAD_TRAP; ! 14 UART A RX/TX |
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85 | BAD_TRAP; ! 15 UART B RX/TX |
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86 | BAD_TRAP; ! 16 correctable memory error |
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87 | BAD_TRAP; ! 17 UART error |
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88 | BAD_TRAP; ! 18 DMA access error |
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89 | BAD_TRAP; ! 19 DMA timeout |
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90 | BAD_TRAP; ! 1A external 3 |
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91 | BAD_TRAP; ! 1B external 4 |
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92 | BAD_TRAP; ! 1C general purpose timer |
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93 | BAD_TRAP; ! 1D real time clock |
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94 | BAD_TRAP; ! 1E external 5 |
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95 | BAD_TRAP; ! 1F watchdog timeout |
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96 | |
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97 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 20 - 23 undefined |
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98 | BAD_TRAP; ! 24 cp_disabled |
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99 | BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 25 - 27 undefined |
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100 | BAD_TRAP; ! 28 cp_exception |
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101 | BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 29 - 2B undefined |
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102 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 2C - 2F undefined |
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103 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 30 - 33 undefined |
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104 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 34 - 37 undefined |
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105 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 38 - 3B undefined |
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106 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 3C - 3F undefined |
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107 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 40 - 43 undefined |
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108 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 44 - 47 undefined |
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109 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 48 - 4B undefined |
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110 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 4C - 4F undefined |
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111 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 50 - 53 undefined |
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112 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 54 - 57 undefined |
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113 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 58 - 5B undefined |
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114 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 5C - 5F undefined |
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115 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 60 - 63 undefined |
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116 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 64 - 67 undefined |
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117 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 68 - 6B undefined |
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118 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 6C - 6F undefined |
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119 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 70 - 73 undefined |
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120 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 74 - 77 undefined |
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121 | BAD_TRAP; BAD_TRAP; BAD_TRAP; BAD_TRAP; ! 78 - 7B undefined |
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122 | |
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123 | /* |
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124 | This is a sad patch to make sure that we know where the |
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125 | MEC timer control register mirror is so we can stop the timers |
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126 | from an external debugger. It is needed because the control |
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127 | register is write-only. Trap 0x7C cannot occure in ERC32... |
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128 | |
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129 | We also use this location to store the last location of the |
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130 | usable RAM in order not to overwrite the remote debugger with |
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131 | the RTEMS work-space area. |
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132 | |
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133 | */ |
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134 | |
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135 | .global SYM(_ERC32_MEC_Timer_Control_Mirror), SYM(rdb_start), SYM(CLOCK_SPEED) |
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136 | .global SYM(Configuration) |
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137 | |
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138 | SYM(rdb_start): |
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139 | SYM(_ERC32_MEC_Timer_Control_Mirror): |
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140 | |
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141 | BAD_TRAP; BAD_TRAP; ! 7C - 7D undefined |
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142 | |
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143 | SYM(CLOCK_SPEED): |
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144 | |
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145 | .word 0x0a, 0, 0, 0 ! 7E (10 MHz default) |
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146 | |
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147 | BAD_TRAP; ! 7F undefined |
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148 | |
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149 | /* |
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150 | * Software traps |
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151 | * |
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152 | * NOTE: At the risk of being redundant... this is not a full |
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153 | * table. The setjmp on the SPARC requires a window flush trap |
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154 | * handler and RTEMS will preserve the entries that were |
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155 | * installed before. |
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156 | */ |
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157 | |
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158 | TRAP( 0x80, SYM(syscall) ); ! 80 syscall SW trap |
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159 | SOFT_TRAP; SOFT_TRAP; ! 81 - 82 |
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160 | TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap |
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161 | |
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162 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 84 - 87 |
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163 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 88 - 8B |
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164 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 8C - 8F |
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165 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 90 - 93 |
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166 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 94 - 97 |
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167 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 98 - 9B |
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168 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! 9C - 9F |
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169 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A0 - A3 |
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170 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A4 - A7 |
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171 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! A8 - AB |
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172 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! AC - AF |
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173 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B0 - B3 |
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174 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B4 - B7 |
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175 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! B8 - BB |
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176 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! BC - BF |
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177 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C0 - C3 |
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178 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C4 - C7 |
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179 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! C8 - CB |
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180 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! CC - CF |
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181 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D0 - D3 |
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182 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D4 - D7 |
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183 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! D8 - DB |
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184 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! DC - DF |
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185 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E0 - E3 |
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186 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E4 - E7 |
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187 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! E8 - EB |
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188 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! EC - EF |
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189 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F0 - F3 |
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190 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F4 - F7 |
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191 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! F8 - FB |
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192 | SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; SOFT_TRAP; ! FC - FF |
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193 | |
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194 | /* |
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195 | * This is the hard reset code. |
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196 | */ |
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197 | |
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198 | #define PSR_INIT 0x10c0 /* Disable traps, set s and ps */ |
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199 | #define WIM_INIT 2 |
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200 | #define STACK_SIZE 16 * 1024 |
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201 | |
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202 | PUBLIC(hard_reset) |
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203 | SYM(hard_reset): |
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204 | |
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205 | /* Common initialisation */ |
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206 | |
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207 | set SYM(trap_table), %g1 ! Initialize TBR |
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208 | mov %g1, %tbr |
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209 | |
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210 | mov %psr, %g1 ! Initialize WIM |
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211 | add %g1, 1, %g2 |
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212 | and %g2, 0x7, %g2 |
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213 | set 1, %g3 |
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214 | sll %g3, %g2, %g3 |
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215 | mov %g3, %wim |
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216 | |
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217 | or %g1, 0x20, %g1 |
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218 | wr %g1, %psr ! enable traps |
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219 | |
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220 | nop |
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221 | nop |
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222 | nop |
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223 | |
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224 | set (SYM(rdb_start)), %g6 ! End of work-space area |
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225 | st %sp, [%g6] |
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226 | sub %g6, 4, %sp ! stack starts at end of RAM - 4 |
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227 | andn %sp, 0x0f, %sp ! align stack on 16-byte boundary |
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228 | mov %sp, %fp ! Set frame pointer |
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229 | nop |
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230 | |
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231 | #if ENABLE_SIS_QUIRKS==1 |
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232 | |
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233 | #include <erc32.h> |
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234 | |
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235 | /* Check if MEC is initialised. If not, this means that we are |
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236 | running on the simulator. Initiate some of the parameters |
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237 | that are done by the boot-prom otherwise. |
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238 | */ |
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239 | |
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240 | set SYM(ERC32_MEC), %g3 ! g3 = base address of peripherals |
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241 | ld [%g3], %g2 |
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242 | set 0xfe080000, %g1 |
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243 | andcc %g1, %g2, %g0 |
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244 | bne 2f |
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245 | |
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246 | /* Set the correct memory size in MEC memory config register */ |
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247 | |
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248 | set SYM(PROM_SIZE), %l0 |
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249 | set 0, %l1 |
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250 | srl %l0, 18, %l0 |
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251 | 1: |
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252 | tst %l0 |
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253 | srl %l0, 1, %l0 |
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254 | bne,a 1b |
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255 | inc %l1 |
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256 | sll %l1, 8, %l1 |
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257 | |
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258 | set SYM(RAM_SIZE), %l0 |
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259 | srl %l0, 19, %l0 |
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260 | 1: |
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261 | tst %l0 |
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262 | srl %l0, 1, %l0 |
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263 | bne,a 1b |
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264 | inc %l1 |
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265 | sll %l1, 10, %l1 |
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266 | |
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267 | ! set the Memory Configuration |
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268 | st %l1, [ %g3 + ERC32_MEC_MEMORY_CONFIGURATION_OFFSET ] |
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269 | !DISABLE THE HARDWARE WATCHDOG |
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270 | st %g0, [ %g3 + ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET ] |
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271 | !Reduce the number of wait states to 0 for all memory areas. |
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272 | st %g0, [ %g3 + ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET ] |
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273 | |
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274 | set SYM(RAM_START), %l1 ! Cannot use RAM_END due to bug in linker |
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275 | set SYM(RAM_SIZE), %l2 |
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276 | add %l1, %l2, %sp |
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277 | st %sp, [%g6] |
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278 | |
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279 | |
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280 | set SYM(CLOCK_SPEED), %g6 ! Use 14 MHz in simulator |
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281 | set 14, %g1 |
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282 | st %g1, [%g6] |
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283 | |
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284 | 2: |
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285 | #endif |
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286 | |
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287 | /* |
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288 | * Copy the initialized data to RAM |
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289 | * |
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290 | * FROM: _endtext |
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291 | * TO: _data_start |
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292 | * LENGTH: (__bss_start - _data_start) bytes |
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293 | */ |
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294 | |
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295 | sethi %hi(_endtext),%g2 |
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296 | or %g2,%lo(_endtext),%g2 ! g2 = start of initialized data in ROM |
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297 | |
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298 | sethi %hi(_data_start),%g3 |
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299 | or %g3,%lo(_data_start),%g3 ! g3 = start of initialized data in RAM |
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300 | |
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301 | sethi %hi(__bss_start),%g4 |
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302 | or %g4,%lo(__bss_start),%g4 ! g4 = end of initialized data in RAM |
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303 | |
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304 | cmp %g2, %g3 |
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305 | be 1f |
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306 | nop |
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307 | |
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308 | copy_data: |
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309 | ldd [ %g2 ], %g6 |
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310 | std %g6 , [ %g3 ] ! copy this double word |
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311 | add %g3, 8, %g3 ! bump the destination pointer |
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312 | add %g2, 8, %g2 ! bump the source pointer |
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313 | cmp %g3, %g4 ! Is the pointer past the end of dest? |
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314 | bl copy_data |
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315 | nop |
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316 | |
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317 | /* clear the bss */ |
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318 | 1: |
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319 | |
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320 | sethi %hi(_edata),%g2 |
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321 | or %g2,%lo(_edata),%g2 ! g2 = start of bss |
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322 | sethi %hi(_end),%g3 |
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323 | or %g3,%lo(_end),%g3 ! g3 = end of bss |
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324 | mov %g0,%g1 ! so std has two zeros |
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325 | zerobss: |
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326 | std %g0,[%g2] |
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327 | add %g2,8,%g2 |
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328 | cmp %g2,%g3 |
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329 | bleu,a zerobss |
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330 | nop |
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331 | |
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332 | mov %0, %o2 ! environ |
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333 | mov %0, %o1 ! argv |
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334 | mov %0, %o0 ! argc |
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335 | call SYM(boot_card) |
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336 | sub %sp, 0x60, %sp ! room for boot_card to save args |
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337 | nop |
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338 | |
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339 | PUBLIC(BSP_fatal_return) |
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340 | SYM(BSP_fatal_return): |
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341 | mov 1, %g1 |
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342 | ta 0 ! Halt if _main returns ... |
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343 | nop |
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344 | |
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345 | /* end of file */ |
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