1 | /* Select PCI driver */ |
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2 | #define GRSPW_PCI |
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3 | |
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4 | #undef GRSPW_MAXDEVS |
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5 | #undef DEBUG_SPACEWIRE_ONOFF |
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6 | /*#define DEBUG_SPACEWIRE_ONOFF*/ |
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7 | /* |
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8 | * If USE_AT697_RAM is defined the RAM on the AT697 board will be used for DMA buffers (but rx message queue is always in AT697 ram). |
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9 | * USE_AT697_DMA specifies whether the messages will be fetched using DMA or PIO. |
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10 | * |
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11 | * RASTA_PCI_BASE is the base address of the GRPCI AHB slave |
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12 | * |
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13 | */ |
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14 | |
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15 | #define USE_AT697_RAM 1 |
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16 | #define USE_AT697_DMA 0 |
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17 | #define RASTA_PCI_BASE 0xe0000000 |
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18 | #define GRSPW_RASTA_MEM_OFF 0x21000 |
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19 | |
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20 | /* Make GRSPW driver use malloced or static memory |
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21 | */ |
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22 | #ifdef USE_AT697_RAM |
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23 | #undef GRSPW_STATIC_MEM |
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24 | #else |
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25 | #define GRSPW_STATIC_MEM |
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26 | #define GRSPW_CALC_MEMOFS(maxcores,corenum,ptr_mem_base,ptr_mem_end,ptr_bdtable_base) \ |
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27 | grspw_rasta_calc_memoffs((maxcores),(corenum),(ptr_mem_base),(ptr_mem_end),(ptr_bdtable_base)) |
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28 | #endif |
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29 | |
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30 | /* We have custom address tranlation for HW addresses */ |
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31 | #define GRSPW_ADR_TO |
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32 | |
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33 | /* MEMAREA=>CPU used when reading descriptor buffer pointers, |
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34 | * they need to be translated from adresses used by GRSPW HW |
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35 | * into CPU readable addresses. |
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36 | * |
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37 | * NOT NEEDED AS GRSPW DRIVER USES INDEXES TO GET DESCRIPTOR |
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38 | * DATA POINTER ADDRESSES. |
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39 | */ |
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40 | #undef GRSPW_ADR_FROM |
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41 | |
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42 | /* Set registered device name */ |
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43 | #define GRSPW_DEVNAME "/dev/grspwrasta0" |
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44 | #define GRSPW_DEVNAME_NO(devstr,no) ((devstr)[15]='0'+(no)) |
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45 | |
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46 | /* Any non-static function will begin with */ |
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47 | #define GRSPW_PREFIX(name) grspwrasta##name |
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48 | |
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49 | /* do nothing, assume that the interrupt handler is called |
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50 | * setup externally calling grspw_interrupt_handler. |
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51 | */ |
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52 | #define GRSPW_REG_INT(handler,irq,arg) \ |
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53 | if ( grspw_rasta_int_reg ) \ |
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54 | grspw_rasta_int_reg(handler,irq,arg); |
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55 | |
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56 | #define GRSPW_DONT_BYPASS_CACHE |
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57 | |
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58 | #ifdef GRSPW_ADR_TO |
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59 | /* Translate a address within the Memory Region (memarea) into an Hardware |
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60 | * device address. This address is put into hardware registers or descriptors |
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61 | * so that the hardware can access the Memory Region. |
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62 | * Example: |
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63 | * An local AMBA access at 0xe0000000 will translate into PCI address 0x40000000, |
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64 | * the PCI address 0x40000000 will translate into CPU-AMBA address 0x40000000. |
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65 | */ |
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66 | static inline unsigned int memarea_to_hw(unsigned int addr) { |
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67 | return ((addr & 0x0fffffff) | RASTA_PCI_BASE); |
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68 | } |
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69 | #endif |
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70 | |
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71 | void (*grspw_rasta_int_reg)(void *handler, int irq, void *arg) = 0; |
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72 | |
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73 | static int grspw_rasta_calc_memoffs(int maxcores, int corenum, unsigned int *mem_base, unsigned int *mem_end, unsigned int *bdtable_base); |
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74 | |
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75 | int grspw_rasta_interrupt_handler(unsigned int status); |
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76 | |
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77 | void grspwrasta_interrupt_handler(int irq, void *pDev); |
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78 | |
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79 | #include "grspw.c" |
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80 | |
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81 | unsigned int grspw_rasta_memarea_address; |
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82 | |
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83 | /* Register RASTA GRSPW driver. |
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84 | * |
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85 | * memarea = preallocated memory somewhere, pointer to start of memory. |
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86 | */ |
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87 | |
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88 | int grspw_rasta_register( |
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89 | amba_confarea_type *bus, |
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90 | unsigned int ram_base |
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91 | ) |
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92 | { |
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93 | /* Setup configuration */ |
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94 | |
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95 | /* if zero the malloc will be used */ |
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96 | grspw_rasta_memarea_address = ram_base + GRSPW_RASTA_MEM_OFF; |
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97 | |
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98 | /* Register the driver */ |
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99 | return GRSPW_PREFIX(_register)(bus); |
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100 | } |
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101 | |
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102 | #if 0 |
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103 | /* Call this from PCI interrupt handler, simply figures out |
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104 | * which GRSPW core was responsible for the IRQ (may be multiple). |
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105 | * v = status of the PCI/AMBA MCPU IRQ CTRL |
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106 | */ |
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107 | int grspw_rasta_interrupt_handler(unsigned int status) |
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108 | { |
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109 | int minor; |
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110 | |
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111 | for(minor = 0; minor < spw_cores; minor++) { |
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112 | if (status & (1<<grspw_devs[minor].irq) ) { |
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113 | grspw_interrupt(&grspw_devs[minor]); |
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114 | } |
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115 | } |
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116 | } |
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117 | #endif |
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118 | |
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119 | void GRSPW_PREFIX(_interrupt_handler)(int irq, void *pDev) |
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120 | { |
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121 | grspw_interrupt(pDev); |
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122 | } |
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123 | |
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124 | |
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125 | #ifdef GRSPW_STATIC_MEM |
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126 | /* |
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127 | * --------------------------------------- <- |
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128 | * | Core1: BD TABLE 1 and 2 | |
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129 | * | Core2: BD TABLE 1 and 2 | |
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130 | * | Core3: BD TABLE 1 and 2 | |
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131 | * |-------------------------------------| |
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132 | * | Core1: rx data buf + rx header buf | |
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133 | * | Core2: rx data buf + rx header buf | |
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134 | * | Core3: rx data buf + rx header buf | |
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135 | * --------------------------------------- |
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136 | */ |
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137 | static int grspw_rasta_calc_memoffs(int maxcores, int corenum, unsigned int *mem_base, unsigned int *mem_end, unsigned int *bdtable_base) |
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138 | { |
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139 | if ( maxcores > 3 ) |
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140 | return -1; |
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141 | |
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142 | if ( bdtable_base ) |
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143 | *bdtable_base = grspw_rasta_memarea_address + corenum*2*SPACEWIRE_BDTABLE_SIZE; |
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144 | |
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145 | if ( mem_base ) |
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146 | *mem_base = grspw_rasta_memarea_address + coremax*2*SPACEWIRE_BDTABLE_SIZE + corenum*BUFMEM_PER_LINK; |
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147 | |
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148 | if ( mem_end ) |
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149 | *mem_end = grspw_rasta_memarea_address + coremax*2*SPACEWIRE_BDTABLE_SIZE + (corenum+1)*BUFMEM_PER_LINK; |
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150 | |
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151 | return 0; |
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152 | } |
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153 | #endif |
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