source: rtems/c/src/lib/libbsp/sparc/shared/spw/grspw_rasta.c @ 226455f

4.104.114.84.95
Last change on this file since 226455f was 226455f, checked in by Joel Sherrill <joel.sherrill@…>, on 09/06/07 at 13:27:25

2007-09-06 Daniel Hellstrom <daniel@…>

New drivers: PCI, b1553BRM, SpaceWire?(GRSPW), CAN (GRCAN,OC_CAN),
Raw UART.

  • shared/1553/b1553brm.c, shared/1553/b1553brm_pci.c, shared/1553/b1553brm_rasta.c, shared/can/grcan.c, shared/can/grcan_rasta.c, shared/can/occan.c, shared/can/occan_pci.c, shared/spw/grspw.c, shared/spw/grspw_pci.c, shared/spw/grspw_rasta.c, shared/uart/apbuart.c, shared/uart/apbuart_pci.c, shared/uart/apbuart_rasta.c: New files missed in previous commit.
  • Property mode set to 100644
File size: 4.5 KB
Line 
1/* Select PCI driver */
2#define GRSPW_PCI
3
4#undef GRSPW_MAXDEVS
5#undef DEBUG_SPACEWIRE_ONOFF
6/*#define DEBUG_SPACEWIRE_ONOFF*/
7/*
8 * If USE_AT697_RAM is defined the RAM on the AT697 board will be used for DMA buffers (but rx message queue is always in AT697 ram).
9 * USE_AT697_DMA specifies whether the messages will be fetched using DMA or PIO.
10 *
11 * RASTA_PCI_BASE is the base address of the GRPCI AHB slave
12 *
13  */
14
15#define USE_AT697_RAM              1
16#define USE_AT697_DMA              0
17#define RASTA_PCI_BASE             0xe0000000
18#define GRSPW_RASTA_MEM_OFF        0x21000
19
20/* Make GRSPW driver use malloced or static memory
21 */
22#ifdef USE_AT697_RAM
23#undef GRSPW_STATIC_MEM
24#else
25#define GRSPW_STATIC_MEM
26#define GRSPW_CALC_MEMOFS(maxcores,corenum,ptr_mem_base,ptr_mem_end,ptr_bdtable_base) \
27        grspw_rasta_calc_memoffs((maxcores),(corenum),(ptr_mem_base),(ptr_mem_end),(ptr_bdtable_base))
28#endif
29
30/* We have custom address tranlation for HW addresses */
31#define GRSPW_ADR_TO
32
33/* MEMAREA=>CPU used when reading descriptor buffer pointers,
34 * they need to be translated from adresses used by GRSPW HW
35 * into CPU readable addresses.
36 *
37 * NOT NEEDED AS GRSPW DRIVER USES INDEXES TO GET DESCRIPTOR
38 * DATA POINTER ADDRESSES.
39 */
40#undef GRSPW_ADR_FROM
41
42/* Set registered device name */
43#define GRSPW_DEVNAME "/dev/grspwrasta0"
44#define GRSPW_DEVNAME_NO(devstr,no) ((devstr)[15]='0'+(no))
45
46/* Any non-static function will begin with */
47#define GRSPW_PREFIX(name) grspwrasta##name
48
49/* do nothing, assume that the interrupt handler is called
50 * setup externally calling grspw_interrupt_handler.
51 */
52#define GRSPW_REG_INT(handler,irq,arg) \
53  if ( grspw_rasta_int_reg ) \
54    grspw_rasta_int_reg(handler,irq,arg);
55
56#define GRSPW_DONT_BYPASS_CACHE
57 
58#ifdef GRSPW_ADR_TO
59/* Translate a address within the Memory Region (memarea) into an Hardware
60 * device address. This address is put into hardware registers or descriptors
61 * so that the hardware can access the Memory Region.
62 * Example:
63 * An local AMBA access at 0xe0000000 will translate into PCI address 0x40000000,
64 * the PCI address 0x40000000 will translate into CPU-AMBA address 0x40000000.
65 */
66static inline unsigned int memarea_to_hw(unsigned int addr) {
67    return ((addr & 0x0fffffff) | RASTA_PCI_BASE);
68}
69#endif
70
71void (*grspw_rasta_int_reg)(void *handler, int irq, void *arg) = 0;
72
73static int grspw_rasta_calc_memoffs(int maxcores, int corenum, unsigned int *mem_base, unsigned int *mem_end, unsigned int *bdtable_base);
74
75int grspw_rasta_interrupt_handler(unsigned int status);
76
77void grspwrasta_interrupt_handler(int irq, void *pDev);
78
79#include "grspw.c"
80
81unsigned int grspw_rasta_memarea_address;
82
83/* Register RASTA GRSPW driver.
84 *
85 * memarea     = preallocated memory somewhere, pointer to start of memory.
86 */
87
88int grspw_rasta_register(
89 amba_confarea_type *bus,
90 unsigned int ram_base
91 )
92{
93        /* Setup configuration */
94       
95        /* if zero the malloc will be used */
96        grspw_rasta_memarea_address = ram_base + GRSPW_RASTA_MEM_OFF;
97
98        /* Register the driver */
99        return GRSPW_PREFIX(_register)(bus);
100}
101
102#if 0
103/* Call this from PCI interrupt handler, simply figures out
104 * which GRSPW core was responsible for the IRQ (may be multiple).
105 * v = status of the PCI/AMBA MCPU IRQ CTRL
106 */
107int grspw_rasta_interrupt_handler(unsigned int status)
108{
109        int minor;
110
111        for(minor = 0; minor < spw_cores; minor++) {
112                if (status & (1<<grspw_devs[minor].irq) ) {
113                        grspw_interrupt(&grspw_devs[minor]);
114                }
115        }
116}
117#endif
118
119void GRSPW_PREFIX(_interrupt_handler)(int irq, void *pDev)
120{
121  grspw_interrupt(pDev);
122}
123
124
125#ifdef GRSPW_STATIC_MEM
126/*
127 *  --------------------------------------- <-   
128 *  | Core1: BD TABLE 1 and 2             |
129 *  | Core2: BD TABLE 1 and 2             |
130 *  | Core3: BD TABLE 1 and 2             |
131 *  |-------------------------------------|
132 *  | Core1: rx data buf + rx header buf  |
133 *  | Core2: rx data buf + rx header buf  |
134 *  | Core3: rx data buf + rx header buf  |
135 *  ---------------------------------------
136 */
137static int grspw_rasta_calc_memoffs(int maxcores, int corenum, unsigned int *mem_base, unsigned int *mem_end, unsigned int *bdtable_base)
138{       
139        if ( maxcores > 3 )
140                return -1;
141       
142        if ( bdtable_base )
143                *bdtable_base = grspw_rasta_memarea_address + corenum*2*SPACEWIRE_BDTABLE_SIZE;
144       
145        if ( mem_base )
146                *mem_base = grspw_rasta_memarea_address + coremax*2*SPACEWIRE_BDTABLE_SIZE + corenum*BUFMEM_PER_LINK;
147       
148        if ( mem_end )
149                *mem_end = grspw_rasta_memarea_address + coremax*2*SPACEWIRE_BDTABLE_SIZE + (corenum+1)*BUFMEM_PER_LINK;
150       
151        return 0;
152}
153#endif
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