1 | /* GRLIB PCIF PCI HOST driver. |
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2 | * |
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3 | * COPYRIGHT (c) 2008. |
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4 | * Cobham Gaisler AB. |
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5 | * |
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6 | * Configures the PCIF core and initialize, |
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7 | * - the PCI Library (pci.c) |
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8 | * - the general part of the PCI Bus driver (pci_bus.c) |
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9 | * |
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10 | * System interrupt assigned to PCI interrupt (INTA#..INTD#) is by |
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11 | * default taken from Plug and Play, but may be overridden by the |
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12 | * driver resources INTA#..INTD#. |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | */ |
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18 | |
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19 | #include <stdio.h> |
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20 | #include <stdlib.h> |
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21 | #include <string.h> |
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22 | #include <libcpu/byteorder.h> |
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23 | #include <libcpu/access.h> |
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24 | #include <rtems/bspIo.h> |
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25 | #include <pci.h> |
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26 | #include <pci/cfg.h> |
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27 | |
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28 | #include <drvmgr/drvmgr.h> |
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29 | #include <drvmgr/ambapp_bus.h> |
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30 | #include <ambapp.h> |
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31 | #include <drvmgr/pci_bus.h> |
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32 | #include <bsp/pcif.h> |
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33 | |
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34 | |
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35 | /* Configuration options */ |
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36 | #define SYSTEM_MAINMEM_START 0x40000000 |
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37 | |
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38 | /* Interrupt assignment. Set to other value than 0xff in order to |
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39 | * override defaults and plug&play information |
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40 | */ |
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41 | #ifndef PCIF_INTA_SYSIRQ |
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42 | #define PCIF_INTA_SYSIRQ 0xff |
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43 | #endif |
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44 | #ifndef PCIF_INTB_SYSIRQ |
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45 | #define PCIF_INTB_SYSIRQ 0xff |
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46 | #endif |
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47 | #ifndef PCIF_INTC_SYSIRQ |
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48 | #define PCIF_INTC_SYSIRQ 0xff |
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49 | #endif |
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50 | #ifndef PCIF_INTD_SYSIRQ |
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51 | #define PCIF_INTD_SYSIRQ 0xff |
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52 | #endif |
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53 | |
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54 | /*#define DEBUG 1 */ |
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55 | |
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56 | #ifdef DEBUG |
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57 | #define DBG(x...) printk(x) |
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58 | #else |
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59 | #define DBG(x...) |
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60 | #endif |
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61 | |
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62 | /* |
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63 | * Bit encode for PCI_CONFIG_HEADER_TYPE register |
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64 | */ |
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65 | struct pcif_regs { |
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66 | volatile unsigned int bars[4]; /* 0x00-0x10 */ |
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67 | volatile unsigned int bus; /* 0x10 */ |
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68 | volatile unsigned int map_io; /* 0x14 */ |
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69 | volatile unsigned int status; /* 0x18 */ |
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70 | volatile unsigned int intr; /* 0x1c */ |
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71 | int unused[(0x40-0x20)/4]; /* 0x20-0x40 */ |
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72 | volatile unsigned int maps[(0x80-0x40)/4]; /* 0x40-0x80*/ |
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73 | }; |
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74 | |
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75 | /* Used internally for accessing the PCI bridge's configuration space itself */ |
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76 | #define HOST_TGT PCI_DEV(0xff, 0, 0) |
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77 | |
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78 | struct pcif_priv *pcifpriv = NULL; |
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79 | static int pcif_minor = 0; |
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80 | |
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81 | /* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#) |
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82 | * to a system interrupt number. |
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83 | */ |
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84 | unsigned char pcif_pci_irq_table[4] = |
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85 | { |
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86 | /* INTA# */ PCIF_INTA_SYSIRQ, |
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87 | /* INTB# */ PCIF_INTB_SYSIRQ, |
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88 | /* INTC# */ PCIF_INTC_SYSIRQ, |
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89 | /* INTD# */ PCIF_INTD_SYSIRQ |
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90 | }; |
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91 | |
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92 | /* Driver private data struture */ |
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93 | struct pcif_priv { |
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94 | struct drvmgr_dev *dev; |
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95 | struct pcif_regs *regs; |
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96 | int irq; |
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97 | int minor; |
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98 | int irq_mask; |
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99 | |
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100 | unsigned int pci_area; |
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101 | unsigned int pci_area_end; |
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102 | unsigned int pci_io; |
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103 | unsigned int pci_conf; |
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104 | unsigned int pci_conf_end; |
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105 | |
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106 | uint32_t devVend; /* Host PCI Vendor/Device ID */ |
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107 | uint32_t bar1_size; |
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108 | |
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109 | struct drvmgr_map_entry maps_up[2]; |
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110 | struct drvmgr_map_entry maps_down[2]; |
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111 | struct pcibus_config config; |
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112 | }; |
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113 | |
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114 | int pcif_init1(struct drvmgr_dev *dev); |
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115 | int pcif_init3(struct drvmgr_dev *dev); |
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116 | |
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117 | /* PCIF DRIVER */ |
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118 | |
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119 | struct drvmgr_drv_ops pcif_ops = |
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120 | { |
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121 | .init = {pcif_init1, NULL, pcif_init3, NULL}, |
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122 | .remove = NULL, |
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123 | .info = NULL |
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124 | }; |
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125 | |
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126 | struct amba_dev_id pcif_ids[] = |
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127 | { |
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128 | {VENDOR_GAISLER, GAISLER_PCIF}, |
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129 | {0, 0} /* Mark end of table */ |
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130 | }; |
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131 | |
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132 | struct amba_drv_info pcif_info = |
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133 | { |
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134 | { |
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135 | DRVMGR_OBJ_DRV, /* Driver */ |
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136 | NULL, /* Next driver */ |
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137 | NULL, /* Device list */ |
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138 | DRIVER_AMBAPP_GAISLER_PCIF_ID, /* Driver ID */ |
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139 | "PCIF_DRV", /* Driver Name */ |
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140 | DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */ |
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141 | &pcif_ops, |
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142 | NULL, /* Funcs */ |
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143 | 0, /* No devices yet */ |
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144 | sizeof(struct pcif_priv), /* Let drvmgr alloc private */ |
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145 | }, |
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146 | &pcif_ids[0] |
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147 | }; |
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148 | |
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149 | void pcif_register_drv(void) |
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150 | { |
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151 | DBG("Registering PCIF driver\n"); |
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152 | drvmgr_drv_register(&pcif_info.general); |
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153 | } |
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154 | |
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155 | static int pcif_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val) |
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156 | { |
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157 | struct pcif_priv *priv = pcifpriv; |
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158 | volatile uint32_t *pci_conf; |
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159 | uint32_t devfn; |
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160 | int retval; |
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161 | int bus = PCI_DEV_BUS(dev); |
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162 | |
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163 | if (ofs & 3) |
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164 | return PCISTS_EINVAL; |
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165 | |
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166 | if (PCI_DEV_SLOT(dev) > 15) { |
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167 | *val = 0xffffffff; |
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168 | return PCISTS_OK; |
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169 | } |
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170 | |
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171 | /* PCIF can access "non-standard" devices on bus0 (on AD11.AD16), |
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172 | * but we skip them. |
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173 | */ |
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174 | if (dev == HOST_TGT) |
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175 | bus = devfn = 0; |
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176 | else if (bus == 0) |
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177 | devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0); |
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178 | else |
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179 | devfn = PCI_DEV_DEVFUNC(dev); |
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180 | |
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181 | /* Select bus */ |
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182 | priv->regs->bus = bus << 16; |
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183 | |
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184 | pci_conf = (volatile uint32_t *)(priv->pci_conf | (devfn << 8) | ofs); |
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185 | |
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186 | *val = *pci_conf; |
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187 | |
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188 | if (priv->regs->status & 0x30000000) { |
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189 | *val = 0xffffffff; |
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190 | retval = PCISTS_MSTABRT; |
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191 | } else |
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192 | retval = PCISTS_OK; |
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193 | |
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194 | DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x\n", |
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195 | PCI_DEV_EXPAND(dev), ofs, pci_conf, *val); |
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196 | |
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197 | return retval; |
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198 | } |
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199 | |
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200 | static int pcif_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val) |
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201 | { |
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202 | uint32_t v; |
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203 | int retval; |
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204 | |
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205 | if (ofs & 1) |
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206 | return PCISTS_EINVAL; |
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207 | |
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208 | retval = pcif_cfg_r32(dev, ofs & ~0x3, &v); |
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209 | *val = 0xffff & (v >> (8*(ofs & 0x3))); |
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210 | |
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211 | return retval; |
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212 | } |
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213 | |
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214 | static int pcif_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val) |
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215 | { |
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216 | uint32_t v; |
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217 | int retval; |
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218 | |
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219 | retval = pcif_cfg_r32(dev, ofs & ~0x3, &v); |
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220 | |
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221 | *val = 0xff & (v >> (8*(ofs & 3))); |
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222 | |
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223 | return retval; |
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224 | } |
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225 | |
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226 | static int pcif_cfg_w32(pci_dev_t dev, int ofs, uint32_t val) |
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227 | { |
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228 | struct pcif_priv *priv = pcifpriv; |
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229 | volatile uint32_t *pci_conf; |
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230 | uint32_t devfn; |
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231 | int bus = PCI_DEV_BUS(dev); |
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232 | |
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233 | if (ofs & ~0xfc) |
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234 | return PCISTS_EINVAL; |
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235 | |
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236 | if (PCI_DEV_SLOT(dev) > 15) |
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237 | return PCISTS_MSTABRT; |
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238 | |
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239 | /* PCIF can access "non-standard" devices on bus0 (on AD11.AD16), |
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240 | * but we skip them. |
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241 | */ |
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242 | if (dev == HOST_TGT) |
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243 | bus = devfn = 0; |
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244 | else if (bus == 0) |
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245 | devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0); |
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246 | else |
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247 | devfn = PCI_DEV_DEVFUNC(dev); |
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248 | |
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249 | /* Select bus */ |
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250 | priv->regs->bus = bus << 16; |
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251 | |
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252 | pci_conf = (volatile uint32_t *)(priv->pci_conf | (devfn << 8) | ofs); |
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253 | |
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254 | *pci_conf = val; |
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255 | |
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256 | DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x\n", |
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257 | PCI_DEV_EXPAND(dev), ofs, pci_conf, value); |
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258 | |
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259 | return PCISTS_OK; |
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260 | } |
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261 | |
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262 | static int pcif_cfg_w16(pci_dev_t dev, int ofs, uint16_t val) |
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263 | { |
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264 | uint32_t v; |
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265 | int retval; |
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266 | |
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267 | if (ofs & 1) |
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268 | return PCISTS_EINVAL; |
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269 | |
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270 | retval = pcif_cfg_r32(dev, ofs & ~0x3, &v); |
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271 | if (retval != PCISTS_OK) |
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272 | return retval; |
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273 | |
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274 | v = (v & ~(0xffff << (8*(ofs&3)))) | ((0xffff&val) << (8*(ofs&3))); |
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275 | |
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276 | return pcif_cfg_w32(dev, ofs & ~0x3, v); |
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277 | } |
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278 | |
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279 | static int pcif_cfg_w8(pci_dev_t dev, int ofs, uint8_t val) |
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280 | { |
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281 | uint32_t v; |
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282 | int retval; |
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283 | |
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284 | retval = pcif_cfg_r32(dev, ofs & ~0x3, &v); |
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285 | if (retval != PCISTS_OK) |
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286 | return retval; |
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287 | |
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288 | v = (v & ~(0xff << (8*(ofs&3)))) | ((0xff&val) << (8*(ofs&3))); |
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289 | |
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290 | return pcif_cfg_w32(dev, ofs & ~0x3, v); |
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291 | } |
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292 | |
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293 | |
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294 | /* Return the assigned system IRQ number that corresponds to the PCI |
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295 | * "Interrupt Pin" information from configuration space. |
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296 | * |
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297 | * The IRQ information is stored in the pcif_pci_irq_table configurable |
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298 | * by the user. |
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299 | * |
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300 | * Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns |
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301 | * 0xff if not assigned. |
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302 | */ |
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303 | static uint8_t pcif_bus0_irq_map(pci_dev_t dev, int irq_pin) |
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304 | { |
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305 | uint8_t sysIrqNr = 0; /* not assigned */ |
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306 | int irq_group; |
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307 | |
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308 | if ( (irq_pin >= 1) && (irq_pin <= 4) ) { |
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309 | /* Use default IRQ decoding on PCI BUS0 according slot numbering */ |
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310 | irq_group = PCI_DEV_SLOT(dev) & 0x3; |
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311 | irq_pin = ((irq_pin - 1) + irq_group) & 0x3; |
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312 | /* Valid PCI "Interrupt Pin" number */ |
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313 | sysIrqNr = pcif_pci_irq_table[irq_pin]; |
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314 | } |
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315 | return sysIrqNr; |
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316 | } |
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317 | |
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318 | static int pcif_translate(uint32_t *address, int type, int dir) |
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319 | { |
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320 | /* No address translation implmented at this point */ |
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321 | return 0; |
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322 | } |
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323 | |
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324 | extern struct pci_memreg_ops pci_memreg_sparc_be_ops; |
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325 | |
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326 | /* PCIF Big-Endian PCI access routines */ |
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327 | struct pci_access_drv pcif_access_drv = { |
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328 | .cfg = |
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329 | { |
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330 | pcif_cfg_r8, |
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331 | pcif_cfg_r16, |
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332 | pcif_cfg_r32, |
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333 | pcif_cfg_w8, |
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334 | pcif_cfg_w16, |
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335 | pcif_cfg_w32, |
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336 | }, |
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337 | .io = /* PCIF only supports Big-endian */ |
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338 | { |
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339 | _ld8, |
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340 | _ld_be16, |
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341 | _ld_be32, |
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342 | _st8, |
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343 | _st_be16, |
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344 | _st_be32, |
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345 | }, |
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346 | .memreg = &pci_memreg_sparc_be_ops, |
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347 | .translate = pcif_translate, |
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348 | }; |
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349 | |
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350 | /* Initializes the PCIF core hardware |
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351 | * |
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352 | */ |
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353 | static int pcif_hw_init(struct pcif_priv *priv) |
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354 | { |
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355 | struct pcif_regs *regs; |
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356 | uint32_t data, size; |
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357 | int mst; |
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358 | pci_dev_t host = HOST_TGT; |
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359 | |
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360 | regs = priv->regs; |
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361 | |
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362 | /* Mask PCI interrupts */ |
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363 | regs->intr = 0; |
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364 | |
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365 | /* Get the PCIF Host PCI ID */ |
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366 | pcif_cfg_r32(host, PCIR_VENDOR, &priv->devVend); |
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367 | |
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368 | /* set 1:1 mapping between AHB -> PCI memory space, for all Master cores */ |
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369 | for ( mst=0; mst<16; mst++) { |
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370 | regs->maps[mst] = priv->pci_area; |
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371 | |
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372 | /* Check if this register is implemented */ |
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373 | if ( regs->maps[mst] != priv->pci_area ) |
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374 | break; |
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375 | } |
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376 | |
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377 | /* and map system RAM at pci address SYSTEM_MAINMEM_START. This way |
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378 | * PCI targets can do DMA directly into CPU main memory. |
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379 | */ |
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380 | regs->bars[0] = SYSTEM_MAINMEM_START; |
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381 | regs->bars[1] = 0; |
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382 | regs->bars[2] = 0; |
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383 | regs->bars[3] = 0; |
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384 | |
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385 | /* determine size of target BAR1 */ |
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386 | pcif_cfg_w32(host, PCIR_BAR(1), 0xffffffff); |
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387 | pcif_cfg_r32(host, PCIR_BAR(1), &size); |
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388 | priv->bar1_size = (~(size & ~0xf)) + 1; |
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389 | |
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390 | pcif_cfg_w32(host, PCIR_BAR(0), 0); |
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391 | pcif_cfg_w32(host, PCIR_BAR(1), SYSTEM_MAINMEM_START); |
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392 | pcif_cfg_w32(host, PCIR_BAR(2), 0); |
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393 | pcif_cfg_w32(host, PCIR_BAR(3), 0); |
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394 | pcif_cfg_w32(host, PCIR_BAR(4), 0); |
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395 | pcif_cfg_w32(host, PCIR_BAR(5), 0); |
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396 | |
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397 | /* set as bus master and enable pci memory responses */ |
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398 | pcif_cfg_r32(host, PCIR_COMMAND, &data); |
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399 | data |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); |
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400 | pcif_cfg_w32(host, PCIR_COMMAND, data); |
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401 | |
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402 | /* Successful */ |
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403 | return 0; |
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404 | } |
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405 | |
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406 | /* Initializes the PCIF core and driver, must be called before calling init_pci() |
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407 | * |
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408 | * Return values |
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409 | * 0 Successful initalization |
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410 | * -1 Error during initialization, for example "PCI core not found". |
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411 | * -2 Error PCI controller not HOST (targets not supported) |
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412 | * -3 Error due to PCIF hardware initialization |
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413 | * -4 Error registering driver to PCI layer |
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414 | */ |
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415 | static int pcif_init(struct pcif_priv *priv) |
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416 | { |
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417 | struct ambapp_apb_info *apb; |
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418 | struct ambapp_ahb_info *ahb; |
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419 | int pin; |
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420 | union drvmgr_key_value *value; |
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421 | char keyname[6]; |
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422 | struct amba_dev_info *ainfo = priv->dev->businfo; |
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423 | |
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424 | /* Find PCI core from Plug&Play information */ |
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425 | apb = ainfo->info.apb_slv; |
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426 | ahb = ainfo->info.ahb_slv; |
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427 | |
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428 | /* Found PCI core, init private structure */ |
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429 | priv->irq = apb->irq; |
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430 | priv->regs = (struct pcif_regs *)apb->start; |
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431 | |
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432 | /* Calculate the PCI windows |
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433 | * AMBA->PCI Window: AHB SLAVE AREA0 |
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434 | * AMBA->PCI I/O cycles Window: AHB SLAVE AREA1 Lower half |
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435 | * AMBA->PCI Configuration cycles Window: AHB SLAVE AREA1 Upper half |
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436 | */ |
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437 | priv->pci_area = ahb->start[0]; |
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438 | priv->pci_area_end = ahb->start[0] + ahb->mask[0]; |
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439 | priv->pci_io = ahb->start[1]; |
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440 | priv->pci_conf = ahb->start[1] + (ahb->mask[1] >> 1); |
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441 | priv->pci_conf_end = ahb->start[1] + ahb->mask[1]; |
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442 | |
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443 | /* On systems where PCI I/O area and configuration area is apart of the "PCI Window" |
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444 | * the PCI Window stops at the start of the PCI I/O area |
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445 | */ |
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446 | if ( (priv->pci_io > priv->pci_area) && (priv->pci_io < (priv->pci_area_end-1)) ) { |
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447 | priv->pci_area_end = priv->pci_io; |
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448 | } |
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449 | |
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450 | /* Init PCI interrupt assignment table to all use the interrupt routed through |
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451 | * the PCIF core. |
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452 | */ |
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453 | strcpy(keyname, "INTX#"); |
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454 | for (pin=1; pin<5; pin++) { |
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455 | if ( pcif_pci_irq_table[pin-1] == 0xff ) { |
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456 | pcif_pci_irq_table[pin-1] = priv->irq; |
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457 | |
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458 | /* User may override Plug & Play IRQ */ |
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459 | keyname[3] = 'A' + (pin-1); |
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460 | value = drvmgr_dev_key_get(priv->dev, keyname, KEY_TYPE_INT); |
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461 | if ( value ) |
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462 | pcif_pci_irq_table[pin-1] = value->i; |
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463 | } |
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464 | } |
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465 | |
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466 | priv->irq_mask = 0xf; |
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467 | value = drvmgr_dev_key_get(priv->dev, "", KEY_TYPE_INT); |
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468 | if ( value ) |
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469 | priv->irq_mask = value->i & 0xf; |
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470 | |
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471 | /* This driver only support HOST systems, we check for HOST */ |
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472 | if ( priv->regs->status & 0x00000001 ) { |
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473 | /* Target not supported */ |
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474 | return -2; |
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475 | } |
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476 | |
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477 | /* Init the PCI Core */ |
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478 | if ( pcif_hw_init(priv) ) { |
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479 | return -3; |
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480 | } |
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481 | |
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482 | /* Down streams translation table */ |
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483 | priv->maps_down[0].name = "AMBA -> PCI MEM Window"; |
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484 | priv->maps_down[0].size = priv->pci_area_end - priv->pci_area; |
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485 | priv->maps_down[0].from_adr = (void *)priv->pci_area; |
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486 | priv->maps_down[0].to_adr = (void *)priv->pci_area; |
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487 | /* End table */ |
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488 | priv->maps_down[1].size = 0; |
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489 | |
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490 | /* Up streams translation table */ |
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491 | priv->maps_up[0].name = "Target BAR1 -> AMBA"; |
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492 | priv->maps_up[0].size = priv->bar1_size; |
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493 | priv->maps_up[0].from_adr = (void *)SYSTEM_MAINMEM_START; |
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494 | priv->maps_up[0].to_adr = (void *)SYSTEM_MAINMEM_START; |
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495 | /* End table */ |
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496 | priv->maps_up[1].size = 0; |
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497 | |
---|
498 | return 0; |
---|
499 | } |
---|
500 | |
---|
501 | /* Called when a core is found with the AMBA device and vendor ID |
---|
502 | * given in pcif_ids[]. |
---|
503 | */ |
---|
504 | int pcif_init1(struct drvmgr_dev *dev) |
---|
505 | { |
---|
506 | struct pcif_priv *priv; |
---|
507 | struct pci_auto_setup pcif_auto_cfg; |
---|
508 | |
---|
509 | DBG("PCIF[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name); |
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510 | |
---|
511 | if ( pcif_minor != 0 ) { |
---|
512 | printf("Driver only supports one PCI core\n"); |
---|
513 | return DRVMGR_FAIL; |
---|
514 | } |
---|
515 | |
---|
516 | priv = dev->priv; |
---|
517 | if ( !priv ) |
---|
518 | return DRVMGR_NOMEM; |
---|
519 | |
---|
520 | dev->priv = priv; |
---|
521 | priv->dev = dev; |
---|
522 | priv->minor = pcif_minor++; |
---|
523 | |
---|
524 | pcifpriv = priv; |
---|
525 | if ( pcif_init(priv) ) { |
---|
526 | printf("Failed to initialize PCIF driver\n"); |
---|
527 | free(priv); |
---|
528 | dev->priv = NULL; |
---|
529 | return DRVMGR_FAIL; |
---|
530 | } |
---|
531 | |
---|
532 | /* Host is always Big-Endian */ |
---|
533 | pci_endian = PCI_BIG_ENDIAN; |
---|
534 | |
---|
535 | /* Register the PCI core at the PCI layer */ |
---|
536 | |
---|
537 | if (pci_access_drv_register(&pcif_access_drv)) { |
---|
538 | /* Access routines registration failed */ |
---|
539 | return DRVMGR_FAIL; |
---|
540 | } |
---|
541 | |
---|
542 | /* Prepare memory MAP */ |
---|
543 | pcif_auto_cfg.options = 0; |
---|
544 | pcif_auto_cfg.mem_start = 0; |
---|
545 | pcif_auto_cfg.mem_size = 0; |
---|
546 | pcif_auto_cfg.memio_start = priv->pci_area; |
---|
547 | pcif_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area; |
---|
548 | pcif_auto_cfg.io_start = priv->pci_io; |
---|
549 | pcif_auto_cfg.io_size = priv->pci_conf - priv->pci_io; |
---|
550 | pcif_auto_cfg.irq_map = pcif_bus0_irq_map; |
---|
551 | pcif_auto_cfg.irq_route = NULL; /* use standard routing */ |
---|
552 | pci_config_register(&pcif_auto_cfg); |
---|
553 | |
---|
554 | if (pci_config_init()) { |
---|
555 | /* PCI configuration failed */ |
---|
556 | return DRVMGR_FAIL; |
---|
557 | } |
---|
558 | |
---|
559 | priv->config.maps_down = &priv->maps_down[0]; |
---|
560 | priv->config.maps_up = &priv->maps_up[0]; |
---|
561 | return pcibus_register(dev, &priv->config); |
---|
562 | } |
---|
563 | |
---|
564 | int pcif_init3(struct drvmgr_dev *dev) |
---|
565 | { |
---|
566 | struct pcif_priv *priv = dev->priv; |
---|
567 | |
---|
568 | /* Unmask all interrupts, on some sytems this |
---|
569 | * might be problematic because all PCI IRQs are |
---|
570 | * not connected on the PCB or used for something |
---|
571 | * else. The irqMask driver resource can be used to |
---|
572 | * control which PCI IRQs are used to generate the |
---|
573 | * PCI system IRQ, example: |
---|
574 | * |
---|
575 | * 0xf - enable all (DEFAULT) |
---|
576 | * 0x8 - enable one PCI irq |
---|
577 | * |
---|
578 | * Before unmasking PCI IRQ, all PCI boards must |
---|
579 | * have been initialized and IRQ turned off to avoid |
---|
580 | * system hang. |
---|
581 | */ |
---|
582 | |
---|
583 | priv->regs->intr = priv->irq_mask; |
---|
584 | |
---|
585 | return DRVMGR_OK; |
---|
586 | } |
---|