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source: rtems/c/src/lib/libbsp/sparc/shared/pci/grpci2dma.c @ 93c5e63

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Last change on this file since 93c5e63 was 93c5e63, checked in by Javier Jalle <javier.jalle@…>, on 02/09/17 at 13:09:17
leon, grpci2dma: add GR740 PCI DMA driver
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File size: 56.9 KB

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1	/*
2	* GRPCI2 DMA Driver
3	*
4	* COPYRIGHT (c) 2017
5	* Cobham Gaisler AB
6	*
7	* The license and distribution terms for this file may be
8	* found in the file LICENSE in this distribution or at
9	* http://www.rtems.org/license/LICENSE.
10	*/
11
12	#include <stdlib.h>
13	#include <stddef.h>
14	#include <drvmgr/drvmgr.h>
15	#include <rtems.h>
16	#include <rtems/bspIo.h> /* for printk */
17	#include <bsp.h>
18	#include <bsp/grpci2dma.h>
19
20	/* This driver has been prepared for SMP operation
21	*/
22	/* Use interrupt lock privmitives compatible with SMP defined in
23	* RTEMS 4.11.99 and higher.
24	*/
25	#if (((__RTEMS_MAJOR__ << 16) \| (__RTEMS_MINOR__ << 8) \| __RTEMS_REVISION__) >= 0x040b63)
26
27	/* map via rtems_interrupt_lock_* API: */
28	#define SPIN_DECLARE(lock) RTEMS_INTERRUPT_LOCK_MEMBER(lock)
29	#define SPIN_INIT(lock, name) rtems_interrupt_lock_initialize(lock, name)
30	#define SPIN_LOCK(lock, level) rtems_interrupt_lock_acquire_isr(lock, &level)
31	#define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_lock_acquire(lock, &level)
32	#define SPIN_UNLOCK(lock, level) rtems_interrupt_lock_release_isr(lock, &level)
33	#define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_lock_release(lock, &level)
34	#define SPIN_IRQFLAGS(k) rtems_interrupt_lock_context k
35	#define SPIN_ISR_IRQFLAGS(k) SPIN_IRQFLAGS(k)
36
37	#else
38
39	/* maintain single-core compatibility with older versions of RTEMS: */
40	#define SPIN_DECLARE(name)
41	#define SPIN_INIT(lock, name)
42	#define SPIN_LOCK(lock, level)
43	#define SPIN_LOCK_IRQ(lock, level) rtems_interrupt_disable(level)
44	#define SPIN_UNLOCK(lock, level)
45	#define SPIN_UNLOCK_IRQ(lock, level) rtems_interrupt_enable(level)
46	#define SPIN_IRQFLAGS(k) rtems_interrupt_level k
47	#define SPIN_ISR_IRQFLAGS(k)
48
49	#ifdef RTEMS_SMP
50	#error SMP mode not compatible with these interrupt lock primitives
51	#endif
52
53	#endif
54
55	/#define STATIC/
56	#define STATIC static
57
58	/#define INLINE/
59	#define INLINE inline
60
61	/#define UNUSED/
62	#define UNUSED __attribute__((unused))
63
64	/#define DEBUG 1/
65
66	#ifdef DEBUG
67	#define DBG(x...) printf(x)
68	#else
69	#define DBG(x...)
70	#endif
71
72	#define BD_CHAN_EN (1<<BD_CHAN_EN_BIT)
73	#define BD_CHAN_ID (0x3<<BD_CHAN_ID_BIT)
74	#define BD_CHAN_TYPE (0x3<<BD_CHAN_TYPE_BIT)
75	#define BD_CHAN_TYPE_DMA (0x1<<BD_CHAN_TYPE_BIT)
76	#define BD_CHAN_BDCNT (0xffff<<BD_CHAN_BDCNT_BIT)
77	#define BD_CHAN_EN_BIT 31
78	#define BD_CHAN_ID_BIT 22
79	#define BD_CHAN_TYPE_BIT 20
80	#define BD_CHAN_BDCNT_BIT 0
81
82	#define BD_DATA_EN (0x1<<BD_DATA_EN_BIT)
83	#define BD_DATA_IE (0x1<<BD_DATA_IE_BIT)
84	#define BD_DATA_DR (0x1<<BD_DATA_DR_BIT)
85	#define BD_DATA_BE (0x1<<BD_DATA_BE_BIT)
86	#define BD_DATA_TYPE (0x3<<BD_DATA_TYPE_BIT)
87	#define BD_DATA_TYPE_DATA (0x0<<BD_DATA_TYPE_BIT)
88	#define BD_DATA_ER (0x1<<BD_DATA_ER_BIT)
89	#define BD_DATA_LEN (0xffff<<BD_DATA_LEN_BIT)
90	#define BD_DATA_EN_BIT 31
91	#define BD_DATA_IE_BIT 30
92	#define BD_DATA_DR_BIT 29
93	#define BD_DATA_BE_BIT 28
94	#define BD_DATA_TYPE_BIT 20
95	#define BD_DATA_ER_BIT 19
96	#define BD_DATA_LEN_BIT 0
97
98	#define DMACTRL_SAFE (0x1<<DMACTRL_SAFE_BIT)
99	#define DMACTRL_WCLEAR (0x1fff<<DMACTRL_ERR_BIT)
100	#define DMACTRL_ERR (0x1f<<DMACTRL_ERR_BIT)
101	#define DMACTRL_CHIRQ (0xff<<DMACTRL_CHIRQ_BIT)
102	#define DMACTRL_ERR (0x1f<<DMACTRL_ERR_BIT)
103	#define DMACTRL_NUMCH (0x7<<DMACTRL_NUMCH_BIT)
104	#define DMACTRL_DIS (0x1<<DMACTRL_DIS_BIT)
105	#define DMACTRL_IE (0x1<<DMACTRL_IE_BIT)
106	#define DMACTRL_ACT (0x1<<DMACTRL_ACT_BIT)
107	#define DMACTRL_EN (0x1<<DMACTRL_EN_BIT)
108
109	#define DMACTRL_SAFE_BIT 31
110	#define DMACTRL_CHIRQ_BIT 12
111	#define DMACTRL_ERR_BIT 7
112	#define DMACTRL_NUMCH_BIT 4
113	#define DMACTRL_DIS_BIT 2
114	#define DMACTRL_IE_BIT 1
115	#define DMACTRL_ACT_BIT 3
116	#define DMACTRL_EN_BIT 0
117
118	/* GRPCI2 DMA does not allow more than 8 DMA chans */
119	#define MAX_DMA_CHANS 8
120
121	/* GRPCI2 DMA does not allow transfer of more than 0x10000 words */
122	#define MAX_DMA_TRANSFER_SIZE (0x10000*4)
123
124	/* We use the following limits as default */
125	#define MAX_DMA_DATA 128
126
127	/* Memory and HW Registers Access routines. All 32-bit access routines */
128	#define BD_WRITE(addr, val) ((volatile unsigned int )(addr) = (unsigned int)(val))
129	/#define BD_READ(addr) ((volatile unsigned int )(addr))/
130	#define BD_READ(addr) leon_r32_no_cache((unsigned long)(addr))
131	#define REG_WRITE(addr, val) ((volatile unsigned int )(addr) = (unsigned int)(val))
132	#define REG_READ(addr) ((volatile unsigned int )(addr))
133
134	/*
135	* GRPCI2 DMA Channel descriptor
136	*/
137	struct grpci2_bd_chan {
138	volatile unsigned int ctrl; /* 0x00 DMA Control */
139	volatile unsigned int nchan; /* 0x04 Next DMA Channel Address */
140	volatile unsigned int nbd; /* 0x08 Next Data Descriptor in channel */
141	volatile unsigned int res; /* 0x0C Reserved */
142	};
143
144	/*
145	* GRPCI2 DMA Data descriptor
146	*/
147	struct grpci2_bd_data {
148	volatile unsigned int ctrl; /* 0x00 DMA Data Control */
149	volatile unsigned int pci_adr; /* 0x04 PCI Start Address */
150	volatile unsigned int ahb_adr; /* 0x08 AHB Start address */
151	volatile unsigned int next; /* 0x0C Next Data Descriptor in channel */
152	};
153
154
155	/*
156	* GRPCI2 DMA APB Register MAP
157	*/
158	struct grpci2dma_regs {
159	volatile unsigned int dma_ctrl; /* 0x00 */
160	volatile unsigned int dma_bdbase; /* 0x04 */
161	volatile unsigned int dma_chact; /* 0x08 */
162	};
163
164	#define DEVNAME_LEN 11
165	/*
166	* GRPCI2 DMA Driver private data struture
167	*/
168	struct grpci2dma_priv {
169	/* DMA control registers */
170	struct grpci2dma_regs *regs;
171	char devname[DEVNAME_LEN];
172
173	/* Channel info */
174	struct {
175	/* Channel pointer. Indicates the assigned channel
176	* for a given cid (used as index). NULL if not assigned.
177	*/
178	struct grpci2_bd_chan * ptr;
179	/* Is this channel allocated by the driver */
180	int allocated;
181	/* Last added data descriptor for each channel.
182	* This simplifies/speeds up adding data descriptors
183	* to the channel*/
184	struct grpci2_bd_data * lastdata;
185	/* Is this channel active */
186	int active;
187	/* Interrupt-code Handling
188	* - isr: Holds the ISR for each channel
189	* - isr_arg: Holds the ISR arg for each channel
190	*/
191	grpci2dma_isr_t isr;
192	void * isr_arg;
193
194	/* DMA Channel Semaphore */
195	rtems_id sem;
196	} channel[MAX_DMA_CHANS];
197
198	/* Indicates the number of channels. */
199	int nchans;
200
201	/* Indicates the number of active channels. */
202	int nactive;
203
204	/* Indicates if the number of DMA ISR that have been registered
205	* into the GRPCI2 DRIVER */
206	int isr_registered;
207
208	/* Callback to register the DMA ISR into the GRPCI2 DRIVER */
209	void (isr_register)( void (isr)(void), void arg);
210
211	/* Spin-lock ISR protection */
212	SPIN_DECLARE(devlock);
213	};
214
215	/* The GRPCI2 DMA semaphore */
216	rtems_id grpci2dma_sem;
217
218	/*
219	* GRPCI2 DMA internal prototypes
220	*/
221	/* -Descriptor linked-list functions*/
222	STATIC int grpci2dma_channel_list_add(struct grpci2_bd_chan * list,
223	struct grpci2_bd_chan * chan);
224	STATIC int grpci2dma_channel_list_remove(struct grpci2_bd_chan * chan);
225	STATIC int grpci2dma_data_list_add(struct grpci2_bd_chan * chan,
226	struct grpci2_bd_data * data, struct grpci2_bd_data * last_chan_data);
227	STATIC int grpci2dma_data_list_remove(struct grpci2_bd_chan * chan,
228	struct grpci2_bd_data * data);
229	STATIC int grpci2dma_channel_list_foreach(struct grpci2_bd_chan * chan,
230	int func( struct grpci2_bd_chan * chan), int maxindex);
231	STATIC int grpci2dma_data_list_foreach(struct grpci2_bd_data * data,
232	int func( struct grpci2_bd_data * data), int maxindex);
233
234	/* -DMA ctrl access functions */
235	STATIC INLINE int grpci2dma_ctrl_init(void);
236	STATIC INLINE int grpci2dma_ctrl_start(struct grpci2_bd_chan * chan);
237	STATIC INLINE int grpci2dma_ctrl_stop(void);
238	STATIC INLINE int grpci2dma_ctrl_resume(void);
239	STATIC INLINE unsigned int grpci2dma_ctrl_status(void);
240	STATIC INLINE unsigned int grpci2dma_ctrl_base(void);
241	STATIC INLINE unsigned int grpci2dma_ctrl_active(void);
242	STATIC INLINE int grpci2dma_ctrl_numch_set(int numch);
243	STATIC INLINE int grpci2dma_ctrl_interrupt_status(void);
244	STATIC INLINE int grpci2dma_ctrl_interrupt_enable(void);
245	STATIC INLINE int grpci2dma_ctrl_interrupt_disable(void);
246	STATIC INLINE int grpci2dma_ctrl_interrupt_clear(void);
247
248	/* -Descriptor access functions */
249	STATIC int grpci2dma_channel_bd_init(struct grpci2_bd_chan * chan);
250	STATIC int grpci2dma_data_bd_init(struct grpci2_bd_data * data,
251	uint32_t pci_adr, uint32_t ahb_adr, int dir, int endianness,
252	int size, struct grpci2_bd_data * next);
253	STATIC int grpci2dma_channel_bd_enable(struct grpci2_bd_chan * chan,
254	unsigned int options);
255	STATIC int grpci2dma_channel_bd_disable(struct grpci2_bd_chan * chan);
256	STATIC void grpci2dma_channel_bd_set_cid(struct grpci2_bd_chan * chan,
257	int cid);
258	STATIC int grpci2dma_channel_bd_get_cid(struct grpci2_bd_chan * chan);
259	STATIC int grpci2dma_data_bd_status(struct grpci2_bd_data *data);
260	STATIC int grpci2dma_data_bd_disable(struct grpci2_bd_data *desc);
261	STATIC int grpci2dma_data_bd_interrupt_enable(struct grpci2_bd_data * data);
262	STATIC struct grpci2_bd_data * grpci2dma_channel_bd_get_data(
263	struct grpci2_bd_chan * chan);
264	STATIC void grpci2dma_channel_bd_set_data(struct grpci2_bd_chan * chan,
265	struct grpci2_bd_data * data);
266	STATIC struct grpci2_bd_chan * grpci2dma_channel_bd_get_next(
267	struct grpci2_bd_chan * chan);
268	STATIC struct grpci2_bd_data * grpci2dma_data_bd_get_next(
269	struct grpci2_bd_data * data);
270	STATIC void grpci2dma_channel_bd_set_next(struct grpci2_bd_chan * chan,
271	struct grpci2_bd_chan * next);
272	STATIC void grpci2dma_data_bd_set_next(struct grpci2_bd_data * data,
273	struct grpci2_bd_data * next);
274
275	/* -Channel functions */
276	STATIC int grpci2dma_channel_open(struct grpci2_bd_chan * chan, int cid);
277	STATIC int grpci2dma_channel_free_id(void);
278	STATIC struct grpci2_bd_chan * grpci2dma_channel_get_active_list(void);
279	STATIC int grpci2dma_channel_start(int chan_no, int options);
280	STATIC int grpci2dma_channel_stop(int chan_no);
281	STATIC int grpci2dma_channel_push(int chan_no, void *dataptr, int index,
282	int ndata);
283	STATIC int grpci2dma_channel_close(int chan_no);
284	STATIC int grpci2dma_channel_isr_unregister(int chan_no);
285
286	/* -ISR functions*/
287	STATIC void grpci2dma_isr(void *arg);
288
289	/* -Init function called by GRPCI2*/
290	int grpci2dma_init(void * regs,
291	void isr_register( void (isr)(void), void * arg));
292
293
294	#ifdef DEBUG
295	STATIC int grpci2dma_channel_print(struct grpci2_bd_chan * chan);
296	STATIC int grpci2dma_data_print(struct grpci2_bd_data * data);
297	#endif
298
299	static struct grpci2dma_priv *grpci2dmapriv = NULL;
300
301	/* All data linked list must point to a disabled descriptor at the end.
302	* We use this DISABLED_DESCRIPTOR as a list end for all channels.
303	*/
304	#define ALIGNED __attribute__((aligned(GRPCI2DMA_BD_DATA_ALIGN)))
305	static ALIGNED struct grpci2_bd_data disabled_data = {
306	/.ctrl=/0,
307	/.pci_adr=/0,
308	/.ahb_adr=/0,
309	/.next=/0
310	};
311	#define DISABLED_DESCRIPTOR (&disabled_data)
312
313	/* START OF DESCRIPTOR LINKED-LIST HELPER FUNCTIONS */
314
315	/* This functions adds a channel descriptor to the DMA channel
316	* linked list. It assumes that someone has check the input
317	* parameters already.
318	*/
319	STATIC int grpci2dma_channel_list_add(struct grpci2_bd_chan * list,
320	struct grpci2_bd_chan * chan)
321	{
322	DBG("Adding channel (0x%08x) to GRPCI2 DMA driver\n", (unsigned int) chan);
323
324	/* Add channel to the linnked list */
325	if (list == chan) {
326	/* No previous channels. Finish. */
327	return GRPCI2DMA_ERR_OK;
328	} else {
329	/* Get next chan from list */
330	struct grpci2_bd_chan * nchan = grpci2dma_channel_bd_get_next(list);
331	/* Close the circular linked list */
332	grpci2dma_channel_bd_set_next(chan,nchan);
333	/* Attach the new channel in the middle */
334	grpci2dma_channel_bd_set_next(list, chan);
335	return GRPCI2DMA_ERR_OK;
336	}
337	}
338
339	/* This functions removes a channel descriptor from the DMA channel
340	* linked list. It assumes that someone has check the input
341	* parameters already.
342	* It returns 0 if successfull. Otherwise,
343	* it can return:
344	* - ERROR: Different causes:
345	* x Number of channels is corrupted.
346	*/
347	STATIC int grpci2dma_channel_list_remove(struct grpci2_bd_chan * chan)
348	{
349	DBG("Removing channel (0x%08x) from GRPCI2 DMA driver\n",
350	(unsigned int) chan);
351
352	/* Remove channel from the linnked list */
353	struct grpci2_bd_chan * nchan = grpci2dma_channel_bd_get_next(chan);
354	if (nchan != chan){
355	/* There are more channels */
356	/* Since this is a circular linked list, we need to find last channel
357	* and update the pointer to the next element */
358	/* Use index to avoid having an infinite loop in case of corrupted
359	* channels */
360	struct grpci2_bd_chan * new_first_chan = nchan;
361	struct grpci2_bd_chan * curr_chan;
362	int i=1;
363	while((nchan != chan) && (i<MAX_DMA_CHANS)){
364	curr_chan = nchan;
365	nchan = grpci2dma_channel_bd_get_next(curr_chan);
366	i++;
367	}
368	if (nchan != chan) {
369	DBG("Maximum DMA channels exceeded. Maybe corrupted?\n");
370	return GRPCI2DMA_ERR_ERROR;
371	} else {
372	/* Update the pointer */
373	grpci2dma_channel_bd_set_next(curr_chan, new_first_chan);
374	return GRPCI2DMA_ERR_OK;
375	}
376	}else{
377	/* There are no more channels */
378	return GRPCI2DMA_ERR_OK;
379	}
380	}
381
382	/* This functions adds a data descriptor to the channel's data
383	* linked list. The function assumes, that the data descriptor
384	* points to either a DISABLED_DESCRIPTOR or to linked list of
385	* data descriptors that ends with a DISABLED_DESCRIPTOR.
386	* It returns the number of active data descriptors
387	* if successfull. Otherwise, it can return:
388	* - ERROR: Different causes:
389	* x Number of channels is corrupted.
390	* x Last linked list element is not pointing to the first.
391	*/
392	STATIC int grpci2dma_data_list_add(struct grpci2_bd_chan * chan,
393	struct grpci2_bd_data * data, struct grpci2_bd_data * last_chan_data)
394	{
395	DBG("Adding data (0x%08x) to channel (0x%08x)\n",
396	(unsigned int) data, (unsigned int) chan);
397
398	/* Add data to the linnked list */
399	/* 1st- Get current data */
400	struct grpci2_bd_data * first_data = grpci2dma_channel_bd_get_data(chan);
401	if (first_data == NULL) {
402	/* Channel should always be pointing to a disabled descriptor */
403	DBG("Channel not pointing to disabled descpriptor\n");
404	return GRPCI2DMA_ERR_ERROR;
405	} else if (first_data == DISABLED_DESCRIPTOR){
406	/* No previous data. Assign this one and finish. */
407	grpci2dma_channel_bd_set_data(chan, data);
408	return GRPCI2DMA_ERR_OK;
409	} else {
410	/* Let's add the data to the last data pointer added to this channel */
411	/* Attach the new data */
412	grpci2dma_data_bd_set_next(last_chan_data, data);
413	/* 2nd- Let's check again to make sure that the DMA did not finished
414	* while we were inserting the new data */
415	first_data = grpci2dma_channel_bd_get_data(chan);
416	if (first_data == DISABLED_DESCRIPTOR){
417	grpci2dma_channel_bd_set_data(chan, data);
418	}
419	return GRPCI2DMA_ERR_OK;
420	}
421	}
422
423	/* This functions removes a data descriptor from the channel's data
424	* linked list. Note that in a normal execution, the DMA will remove
425	* the data descriptors from the linked list, so there is no need to
426	* use this function. It returns 0 if successfull. Otherwise,
427	* it can return:
428	* - WRONGPTR: The chan (or data) pointer is either NULL or not aligned to
429	* 0x10.
430	* - STOPDMA: The DMA is running, cannot add channels while DMA is running.
431	* - TOOMANY: The max number of data is reached.
432	* - ERROR: Different causes:
433	* x There are no free channel id numbers.
434	* x Number of channels is corrupted.
435	* x Last linked list element is not pointing to the first.
436	*/
437	UNUSED STATIC int grpci2dma_data_list_remove(struct grpci2_bd_chan * chan,
438	struct grpci2_bd_data * data)
439	{
440	DBG("Removing data (0x%08x) from channel (0x%08x)\n",
441	(unsigned int) data, (unsigned int) chan);
442
443	/* Remove data from the linked list */
444	/* 1st- Get current DMA data */
445	struct grpci2_bd_data * first_data = grpci2dma_channel_bd_get_data(chan);
446	if (first_data == NULL) {
447	/* Channel should always be pointing to a disabled descriptor */
448	DBG("Channel not pointing to disabled descpriptor\n");
449	return GRPCI2DMA_ERR_ERROR;
450	} else if (first_data == DISABLED_DESCRIPTOR){
451	/* No previous data. Cannot detach */
452	DBG("No data to detach.\n");
453	return GRPCI2DMA_ERR_NOTFOUND;
454	} else {
455	/* 2nd- Already available data, let's find the data */
456	if (first_data == data) {
457	/* 3rd- It is the first one. */
458	struct grpci2_bd_data *current = first_data;
459	struct grpci2_bd_data *next = grpci2dma_data_bd_get_next(current);
460	if (next != DISABLED_DESCRIPTOR){
461	/* There are more data */
462	/* Set channel next data descriptor to data*/
463	grpci2dma_channel_bd_set_data(chan, next);
464	/* Update the removed data */
465	grpci2dma_data_bd_set_next(data, DISABLED_DESCRIPTOR);
466	return GRPCI2DMA_ERR_OK;
467	}else{
468	/* No more data */
469	/* Clear DMA NBD */
470	grpci2dma_channel_bd_set_data(chan, DISABLED_DESCRIPTOR);
471	/* Update the removed data */
472	grpci2dma_data_bd_set_next(data, DISABLED_DESCRIPTOR);
473	return GRPCI2DMA_ERR_OK;
474	}
475	} else {
476	/* It is not the first data. Let's find it */
477	struct grpci2_bd_data * current = first_data;
478	struct grpci2_bd_data * next = grpci2dma_data_bd_get_next(current);
479	while( (next != data) && (next != DISABLED_DESCRIPTOR) &&
480	(next != NULL)){
481	current = next;
482	next = grpci2dma_data_bd_get_next(current);
483	}
484	if (next != data) {
485	DBG("Maximum DMA data exceeded. Maybe corrupted?\n");
486	return GRPCI2DMA_ERR_NOTFOUND;
487	} else {
488	/* Detach the data */
489	next = grpci2dma_data_bd_get_next(data);
490	grpci2dma_data_bd_set_next(current, next);
491	/* Update the removed data */
492	grpci2dma_data_bd_set_next(data, DISABLED_DESCRIPTOR);
493	return GRPCI2DMA_ERR_OK;
494	}
495	}
496	}
497	}
498
499	/* Iterate through all channel starting in FIRST_CHAN up to MAXINDEX
500	* and execute FUNC*/
501	UNUSED STATIC int grpci2dma_channel_list_foreach(
502	struct grpci2_bd_chan * first_chan,
503	int func( struct grpci2_bd_chan * chan), int maxindex)
504	{
505	if (maxindex <= 0) return 0;
506	if (first_chan == NULL) {
507	/* No previous channels */
508	return 0;
509	} else {
510	/* Available channels */
511	/* Iterate through next channels */
512	/* Use index to avoid having an infinite loop in case of corrupted
513	* channels */
514	int i=0;
515	int ret;
516	struct grpci2_bd_chan * curr_chan = first_chan;
517	struct grpci2_bd_chan * nchan;
518	do{
519	if (curr_chan == NULL) return GRPCI2DMA_ERR_WRONGPTR;
520	ret = func(curr_chan);
521	if (ret < 0){
522	/* error */
523	return ret;
524	}
525	nchan = grpci2dma_channel_bd_get_next(curr_chan);
526	curr_chan = nchan;
527	i++;
528	}while((curr_chan != first_chan) && (i < maxindex));
529	}
530	return 0;
531	}
532
533	/* Iterate through all data starting in FIRST_DATA up to MAXINDEX
534	* and execute FUNC*/
535	STATIC int grpci2dma_data_list_foreach(struct grpci2_bd_data * first_data,
536	int func( struct grpci2_bd_data * data), int maxindex)
537	{
538	if (maxindex <= 0) return 0;
539	if (first_data == NULL) return GRPCI2DMA_ERR_WRONGPTR;
540	/* Available data */
541	/* Iterate through next data */
542	/* Use index to avoid having an infinite loop in case of corrupted
543	* channels */
544	int i=0;
545	int ret;
546	struct grpci2_bd_data * curr_data = first_data;
547	struct grpci2_bd_data * ndata;
548	while((curr_data != DISABLED_DESCRIPTOR) && (i < maxindex)){
549	if (curr_data == NULL) return GRPCI2DMA_ERR_WRONGPTR;
550	ret = func(curr_data);
551	if (ret < 0){
552	/* error */
553	return ret;
554	}
555	ndata = grpci2dma_data_bd_get_next(curr_data);
556	curr_data = ndata;
557	i++;
558	}
559	return 0;
560	}
561
562
563	/* END OF DESCRIPTOR LINKED-LIST HELPER FUNCTIONS */
564
565	/* START OF DMACTRL ACCESS FUNCTIONS */
566
567	/* Initialize the DMA Ctrl*/
568	STATIC INLINE int grpci2dma_ctrl_init()
569	{
570	struct grpci2dma_priv *priv = grpci2dmapriv;
571
572	/* Clear DMA Control: clear IRQ and ERR status */
573	REG_WRITE(&priv->regs->dma_ctrl, 0\|DMACTRL_SAFE\|DMACTRL_CHIRQ\|DMACTRL_ERR);
574
575	/* Clear DMA BASE */
576	REG_WRITE(&priv->regs->dma_bdbase, 0);
577
578	/* Clear DMA Chan */
579	REG_WRITE(&priv->regs->dma_chact, 0);
580
581	return 0;
582	}
583
584
585	/* Stop the DMA */
586	STATIC INLINE int grpci2dma_ctrl_stop( void )
587	{
588	struct grpci2dma_priv *priv = grpci2dmapriv;
589
590	/* Stop DMA */
591	unsigned int ctrl = REG_READ(&priv->regs->dma_ctrl);
592	REG_WRITE(&priv->regs->dma_ctrl, (ctrl & ~(DMACTRL_WCLEAR \| DMACTRL_EN)) \|
593	DMACTRL_DIS);
594
595	return 0;
596	}
597
598	/* Start the DMA */
599	STATIC INLINE int grpci2dma_ctrl_start( struct grpci2_bd_chan * chan)
600	{
601	struct grpci2dma_priv *priv = grpci2dmapriv;
602
603	/* Set BDBASE to linked list of chans */
604	REG_WRITE(&priv->regs->dma_bdbase, (unsigned int) chan);
605
606	/* Start DMA */
607	unsigned int ctrl = REG_READ(&priv->regs->dma_ctrl);
608	REG_WRITE(&priv->regs->dma_ctrl, (ctrl & ~(DMACTRL_WCLEAR \| DMACTRL_DIS)) \|
609	DMACTRL_EN);
610
611	return 0;
612	}
613
614	/* Resume the DMA */
615	STATIC INLINE int grpci2dma_ctrl_resume( void )
616	{
617	struct grpci2dma_priv *priv = grpci2dmapriv;
618
619	/* Resume DMA */
620	unsigned int ctrl = REG_READ(&priv->regs->dma_ctrl);
621	REG_WRITE(&priv->regs->dma_ctrl, (ctrl & ~(DMACTRL_WCLEAR \| DMACTRL_DIS)) \|
622	DMACTRL_EN);
623
624	return 0;
625	}
626
627	/* Interrupt status*/
628	STATIC INLINE int grpci2dma_ctrl_interrupt_status(void)
629	{
630	struct grpci2dma_priv *priv = grpci2dmapriv;
631
632	unsigned int ctrl = REG_READ(&priv->regs->dma_ctrl);
633	return (ctrl & DMACTRL_IE);
634	}
635
636	/* Enable interrupts */
637	STATIC INLINE int grpci2dma_ctrl_interrupt_enable(void)
638	{
639	struct grpci2dma_priv *priv = grpci2dmapriv;
640
641	unsigned int ctrl = REG_READ(&priv->regs->dma_ctrl);
642	if (ctrl & DMACTRL_IE){
643	/* Nothing to do. Already enabled */
644	return 0;
645	}
646
647	/* Clear pending CHIRQ and errors */
648	ctrl = ctrl \| (DMACTRL_CHIRQ \| DMACTRL_ERR);
649
650	/* Enable interrupts */
651	ctrl = ctrl \| DMACTRL_IE;
652
653	REG_WRITE(&priv->regs->dma_ctrl, ctrl );
654	return 0;
655	}
656
657	/* Disable interrupts */
658	STATIC INLINE int grpci2dma_ctrl_interrupt_disable(void)
659	{
660	struct grpci2dma_priv *priv = grpci2dmapriv;
661
662	unsigned int ctrl = REG_READ(&priv->regs->dma_ctrl);
663	if ((ctrl & DMACTRL_IE) == 0){
664	/* Nothing to do. Already disabled */
665	return 0;
666	}
667
668	/* Clear pending CHIRQ and errors */
669	ctrl = ctrl \| (DMACTRL_CHIRQ \| DMACTRL_ERR);
670
671	/* Disable interrupts */
672	ctrl = ctrl & ~(DMACTRL_IE);
673
674	REG_WRITE(&priv->regs->dma_ctrl, ctrl );
675	return 0;
676	}
677
678	/* Clear interrupts */
679	STATIC INLINE int grpci2dma_ctrl_interrupt_clear(void)
680	{
681	struct grpci2dma_priv *priv = grpci2dmapriv;
682
683	unsigned int ctrl = REG_READ(&priv->regs->dma_ctrl);
684	REG_WRITE(&priv->regs->dma_ctrl, (ctrl \| DMACTRL_ERR \| DMACTRL_CHIRQ));
685	return 0;
686	}
687
688	STATIC INLINE unsigned int grpci2dma_ctrl_status()
689	{
690	struct grpci2dma_priv *priv = grpci2dmapriv;
691
692	/* Read DMA */
693	return (REG_READ(&priv->regs->dma_ctrl));
694	}
695
696	STATIC INLINE unsigned int grpci2dma_ctrl_base()
697	{
698	struct grpci2dma_priv *priv = grpci2dmapriv;
699
700	/* Read DMA */
701	return (REG_READ(&priv->regs->dma_bdbase));
702	}
703
704	UNUSED STATIC INLINE unsigned int grpci2dma_ctrl_active()
705	{
706	struct grpci2dma_priv *priv = grpci2dmapriv;
707
708	/* Read DMA */
709	return (REG_READ(&priv->regs->dma_chact));
710	}
711
712	/* Set the DMA CTRL register NUMCH field */
713	STATIC INLINE int grpci2dma_ctrl_numch_set(int numch)
714	{
715	struct grpci2dma_priv *priv = grpci2dmapriv;
716
717	unsigned int ctrl = REG_READ(&priv->regs->dma_ctrl);
718
719	/* Clear old value */
720	ctrl = (ctrl & ~(DMACTRL_NUMCH));
721
722	/* Put new value */
723	ctrl = (ctrl \| ( (numch << DMACTRL_NUMCH_BIT) & DMACTRL_NUMCH));
724
725	REG_WRITE(&priv->regs->dma_ctrl, ctrl & ~(DMACTRL_WCLEAR));
726	return 0;
727	}
728
729	/* END OF DMACTRL ACCESS FUNCTIONS */
730
731	/* START OF DESCRIPTOR ACCESS FUNCTIONS */
732
733	STATIC int grpci2dma_data_bd_init(struct grpci2_bd_data * data,
734	uint32_t pci_adr, uint32_t ahb_adr, int dir, int endianness, int size,
735	struct grpci2_bd_data * next)
736	{
737	BD_WRITE(&data->ctrl, 0 \|
738	(BD_DATA_EN) \|
739	(BD_DATA_TYPE_DATA) \|
740	(dir == GRPCI2DMA_AHBTOPCI? BD_DATA_DR:0) \|
741	(endianness == GRPCI2DMA_LITTLEENDIAN? BD_DATA_BE:0) \|
742	( (size << BD_DATA_LEN_BIT) & BD_DATA_LEN )
743	);
744	BD_WRITE(&data->pci_adr, pci_adr);
745	BD_WRITE(&data->ahb_adr, ahb_adr);
746	BD_WRITE(&data->next, (unsigned int) next);
747	return 0;
748	}
749
750	STATIC int grpci2dma_channel_bd_init(struct grpci2_bd_chan * chan)
751	{
752	BD_WRITE(&chan->ctrl, 0 \| BD_CHAN_TYPE_DMA \| BD_CHAN_EN);
753	BD_WRITE(&chan->nchan, (unsigned int) chan);
754	BD_WRITE(&chan->nbd, (unsigned int) DISABLED_DESCRIPTOR);
755	return 0;
756	}
757
758	/* Enable a channel with options.
759	* options include:
760	* - options & 0xFFFF: Maximum data descriptor count before
761	* moving to next DMA channel.
762	*/
763	STATIC int grpci2dma_channel_bd_enable(struct grpci2_bd_chan * chan,
764	unsigned int options)
765	{
766	unsigned int ctrl = BD_READ(&chan->ctrl);
767	ctrl = (ctrl & ~(BD_CHAN_BDCNT));
768	BD_WRITE(&chan->ctrl, (ctrl \| BD_CHAN_EN \|
769	( (options << BD_CHAN_BDCNT_BIT) & BD_CHAN_BDCNT)));
770	return 0;
771	}
772
773	/* Disable channel.
774	*/
775	STATIC int grpci2dma_channel_bd_disable(struct grpci2_bd_chan * chan)
776	{
777	unsigned int ctrl = BD_READ(&chan->ctrl);
778	BD_WRITE(&chan->ctrl, (ctrl & ~(BD_CHAN_EN)));
779	return 0;
780	}
781
782	/* Get the CID of a channel.
783	*/
784	UNUSED STATIC int grpci2dma_channel_bd_get_cid(struct grpci2_bd_chan * chan)
785	{
786	/* Get cid from chan */
787	unsigned ctrl = BD_READ(&chan->ctrl);
788	unsigned cid = (ctrl & (BD_CHAN_ID)) >> BD_CHAN_ID_BIT;
789	return cid;
790	}
791
792	/* Set the CID of a channel. */
793	STATIC void grpci2dma_channel_bd_set_cid(struct grpci2_bd_chan * chan, int cid)
794	{
795	/* Set cid from chan */
796	unsigned ctrl = BD_READ(&chan->ctrl);
797	ctrl = (ctrl & ~(BD_CHAN_ID)) \| ((cid << BD_CHAN_ID_BIT) & BD_CHAN_ID);
798	BD_WRITE(&chan->ctrl,ctrl);
799	return;
800	}
801
802	/* Disable data descriptor*/
803	UNUSED STATIC int grpci2dma_data_bd_disable(struct grpci2_bd_data *desc)
804	{
805	BD_WRITE(&desc->ctrl,0);
806	return 0;
807	}
808
809	/* Return status of data descriptor*/
810	STATIC int grpci2dma_data_bd_status(struct grpci2_bd_data *desc)
811	{
812	int status = BD_READ(&desc->ctrl);
813	if (status & BD_DATA_ER) {
814	return GRPCI2DMA_BD_STATUS_ERR;
815	}else if (status & BD_DATA_EN) {
816	return GRPCI2DMA_BD_STATUS_ENABLED;
817	}else {
818	return GRPCI2DMA_BD_STATUS_DISABLED;
819	}
820	return GRPCI2DMA_BD_STATUS_ERR;
821	}
822
823	/* Enable interrupts in data descriptor*/
824	STATIC int grpci2dma_data_bd_interrupt_enable(struct grpci2_bd_data * data)
825	{
826	unsigned int ctrl = BD_READ(&data->ctrl);
827	BD_WRITE(&data->ctrl, ctrl \| BD_DATA_IE);
828	return 0;
829	}
830
831	/* Get data descriptor */
832	STATIC struct grpci2_bd_data * grpci2dma_channel_bd_get_data(
833	struct grpci2_bd_chan * chan)
834	{
835	return (struct grpci2_bd_data *) BD_READ(&chan->nbd);
836	}
837
838	/* Set data descriptorl */
839	STATIC void grpci2dma_channel_bd_set_data(struct grpci2_bd_chan * chan,
840	struct grpci2_bd_data * data)
841	{
842	BD_WRITE(&chan->nbd, (unsigned int) data);
843	}
844
845	/* Get next channel */
846	STATIC struct grpci2_bd_chan * grpci2dma_channel_bd_get_next(
847	struct grpci2_bd_chan * chan)
848	{
849	return (struct grpci2_bd_chan *) BD_READ(&chan->nchan);
850	}
851
852	/* Get next data */
853	STATIC struct grpci2_bd_data * grpci2dma_data_bd_get_next(
854	struct grpci2_bd_data * data)
855	{
856	return (struct grpci2_bd_data *) BD_READ(&data->next);
857	}
858
859	/* Set next channel */
860	STATIC void grpci2dma_channel_bd_set_next(struct grpci2_bd_chan * chan,
861	struct grpci2_bd_chan * next)
862	{
863	BD_WRITE(&chan->nchan,(unsigned int) next);
864	}
865
866	/* Set next data */
867	STATIC void grpci2dma_data_bd_set_next(struct grpci2_bd_data * data,
868	struct grpci2_bd_data * next)
869	{
870	BD_WRITE(&data->next,(unsigned int) next);
871	}
872
873	/* END OF DESCRIPTOR ACCESS FUNCTIONS */
874
875	/* START OF CHANNEL FUNCTIONS */
876
877	STATIC int grpci2dma_channel_open(struct grpci2_bd_chan * chan, int cid)
878	{
879	struct grpci2dma_priv *priv = grpci2dmapriv;
880	int allocated = 0;
881
882	/* Get pointer */
883	if (chan == NULL) {
884	/* User does not provide channel, let's create it */
885	chan = grpci2dma_channel_new(1);
886	allocated = 1;
887	}else{
888	/* Make sure the pointer is not already on the linked list */
889	int i;
890	for (i=0; i<MAX_DMA_CHANS; i++){
891	if (priv->channel[i].ptr == chan){
892	return GRPCI2DMA_ERR_WRONGPTR;
893	}
894	}
895	}
896
897	DBG("Opening channel %d (0x%08x)\n", cid, (unsigned int) chan);
898
899	/* Init channel descriptor */
900	grpci2dma_channel_bd_init(chan);
901
902	/* Assign cid to chan */
903	priv->channel[cid].ptr = chan;
904	grpci2dma_channel_bd_set_cid(chan, cid);
905
906	/* Increase number of channels */
907	priv->nchans++;
908
909	DBG("number of channels: %d\n", priv->nchans);
910
911	/* Initialize channel data */
912	priv->channel[cid].allocated = allocated;
913	priv->channel[cid].active = 0;
914
915	/* Initialize record of last added data */
916	priv->channel[cid].lastdata = DISABLED_DESCRIPTOR;
917
918	return cid;
919	}
920
921	/* Get first free CID.
922	*/
923	STATIC int grpci2dma_channel_free_id()
924	{
925	struct grpci2dma_priv *priv = grpci2dmapriv;
926
927	/* Find the first free CID */
928	int i;
929	for (i=0; i<MAX_DMA_CHANS; i++){
930	if (priv->channel[i].ptr == NULL){
931	return i;
932	}
933	}
934	return GRPCI2DMA_ERR_TOOMANY;
935	}
936
937	/* Get the active channel circular linked list */
938	STATIC struct grpci2_bd_chan * grpci2dma_channel_get_active_list()
939	{
940	struct grpci2dma_priv *priv = grpci2dmapriv;
941	int i;
942	/* Just get the first non NULL associated cid */
943	for (i=0; i< MAX_DMA_CHANS; i++){
944	if ((priv->channel[i].ptr != NULL) && (priv->channel[i].active)){
945	return priv->channel[i].ptr;
946	}
947	}
948	return NULL;
949	}
950
951	/* Start a channel */
952	STATIC int grpci2dma_channel_start(int chan_no, int options)
953	{
954	struct grpci2dma_priv *priv = grpci2dmapriv;
955	struct grpci2_bd_chan *chan;
956	SPIN_IRQFLAGS(irqflags);
957
958	/* Get chan pointer */
959	chan = priv->channel[chan_no].ptr;
960
961	/* Check if channel is active */
962	if (priv->channel[chan_no].active){
963	/* nothing to do */
964	return GRPCI2DMA_ERR_OK;
965	}
966
967	/* Get the max descriptor count */
968	unsigned int desccnt;
969	if (options == 0){
970	/* Default */
971	desccnt = 0xffff;
972	}else{
973	desccnt = options & 0xffff;
974	}
975
976	/* Start the channel by enabling it.
977	* HWNOTE: In GRPCI2 this bit does not work as it is supposed.
978	* So we better add/remove the channel from the active linked
979	* list. */
980	grpci2dma_channel_bd_enable(chan, desccnt);
981	priv->channel[chan_no].active = 1;
982	priv->nactive++;
983	/* Get active linked list */
984	struct grpci2_bd_chan * list = grpci2dma_channel_get_active_list();
985	if (list == NULL){
986	/* No previous channels. New list */
987	list = chan;
988	}
989	/* Add channel from the linked list */
990	if (grpci2dma_channel_list_add(list, chan) < 0){
991	return GRPCI2DMA_ERR_ERROR;
992	}
993
994	/* Increase NUMCH in DMA ctrl */
995	SPIN_LOCK_IRQ(&priv->devlock, irqflags);
996	grpci2dma_ctrl_numch_set( (priv->nactive? priv->nactive -1:0));
997
998	/* Check if DMA is active */
999	if (!grpci2dma_active()){
1000	/* Start DMA */
1001	grpci2dma_ctrl_start(chan);
1002	}
1003	SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
1004
1005	DBG("Channel %d started (0x%08x)\n", chan_no, (unsigned int) chan);
1006
1007	return GRPCI2DMA_ERR_OK;
1008	}
1009
1010	/* Stop a channel */
1011	STATIC int grpci2dma_channel_stop(int chan_no)
1012	{
1013	struct grpci2dma_priv *priv = grpci2dmapriv;
1014	struct grpci2_bd_chan *chan;
1015	SPIN_IRQFLAGS(irqflags);
1016	int resume;
1017
1018	/* Get chan pointer */
1019	chan = priv->channel[chan_no].ptr;
1020
1021	/* Check if channel is active */
1022	if (!priv->channel[chan_no].active){
1023	/* nothing to do */
1024	return GRPCI2DMA_ERR_OK;
1025	}
1026
1027	/* First remove channel from the linked list */
1028	if (grpci2dma_channel_list_remove(chan) < 0){
1029	return GRPCI2DMA_ERR_ERROR;
1030	}
1031
1032	/* Update driver struct */
1033	priv->channel[chan_no].active = 0;
1034	priv->nactive--;
1035
1036	/* Check if DMA is active and it the removed
1037	* channel is the active */
1038	resume = 0;
1039	SPIN_LOCK_IRQ(&priv->devlock, irqflags);
1040	if (grpci2dma_active() && (grpci2dma_ctrl_active() == (unsigned int)chan)){
1041	/* We need to stop the DMA */
1042	grpci2dma_ctrl_stop();
1043	SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
1044	/* Wait until DMA stops */
1045	while (grpci2dma_active()){}
1046	/* We need to check later to resume the DMA */
1047	resume = 1;
1048	}else{
1049	SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
1050	}
1051
1052
1053	/* Now either the DMA is stopped, or it is processing
1054	* a different channel and the removed channel is no
1055	* longer in the linked list */
1056
1057	/* Now is safe to update the removed channel */
1058	grpci2dma_channel_bd_set_next(chan, chan);
1059
1060	/* Stop the channel by disabling it.
1061	* HWNOTE: In GRPCI2 this bit does not work as it is supposed.
1062	* So we better remove the channel from the active linked
1063	* list. */
1064	grpci2dma_channel_bd_disable(chan);
1065
1066	/* Point channel to disabled descriptor */
1067	grpci2dma_channel_bd_set_data(chan, DISABLED_DESCRIPTOR);
1068
1069	DBG("Channel %d stoped (0x%08x)\n", chan_no, (unsigned int) chan);
1070
1071	/* Decrease NUMCH in DMA ctrl */
1072	SPIN_LOCK_IRQ(&priv->devlock, irqflags);
1073	grpci2dma_ctrl_numch_set( (priv->nactive? priv->nactive -1:0));
1074
1075	/* Reactivate DMA only if we stopped */
1076	if (resume){
1077	/* We have two options, either we stopped when the active
1078	* channel was still the active one, or we stopped when
1079	* the active channel was a different one */
1080	if (grpci2dma_ctrl_active() == (unsigned int) chan){
1081	/* In this case, we need to start the DMA with
1082	* any active channel on the list */
1083	int i;
1084	for (i=0; i<MAX_DMA_CHANS; i++){
1085	if (priv->channel[i].active){
1086	grpci2dma_ctrl_start(priv->channel[i].ptr);
1087	break;
1088	}
1089	}
1090	}else{
1091	/* In this case, we need to resume the DMA operation */
1092	/* HWNOTE: The GRPCI2 core does not update the channel next
1093	* data descriptor if we stopped a channel. This means that
1094	* we need to resume the DMA from the descriptor is was,
1095	* by only setting the enable bit, and not changing the
1096	* base register */
1097	grpci2dma_ctrl_resume();
1098	}
1099	}
1100	SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
1101
1102	return GRPCI2DMA_ERR_OK;
1103	}
1104
1105	STATIC int grpci2dma_channel_push(int chan_no, void *dataptr, int index,
1106	int ndata)
1107	{
1108	struct grpci2dma_priv *priv = grpci2dmapriv;
1109	struct grpci2_bd_chan * chan;
1110	struct grpci2_bd_data * data = dataptr;
1111
1112	/* Get channel */
1113	chan = priv->channel[chan_no].ptr;
1114
1115	DBG("Pushing %d data (starting at 0x%08x) to channel %d (0x%08x)\n",
1116	ndata, (unsigned int) &data[index], chan_no, (unsigned int) chan);
1117
1118	/* Get last added data */
1119	struct grpci2_bd_data * last_added = priv->channel[chan_no].lastdata;
1120
1121	/* Add data to channel */
1122	grpci2dma_data_list_add(chan, &data[index], last_added);
1123
1124	/* Update last added */
1125	priv->channel[chan_no].lastdata = &data[index + ndata-1];
1126
1127	return GRPCI2DMA_ERR_OK;
1128	}
1129
1130	STATIC int grpci2dma_channel_close(int chan_no)
1131	{
1132	struct grpci2dma_priv *priv = grpci2dmapriv;
1133	struct grpci2_bd_chan * chan;
1134
1135	/* Get channel */
1136	chan = priv->channel[chan_no].ptr;
1137
1138	DBG("Closing channel %d (0x%08x)\n", chan_no, (unsigned int) chan);
1139
1140	/* Stop channel */
1141	if (grpci2dma_channel_stop(chan_no) != GRPCI2DMA_ERR_OK ){
1142	DBG("Cannot stop channel!.\n");
1143	return GRPCI2DMA_ERR_STOPDMA;
1144	}
1145
1146	/* Unregister channel ISR */
1147	grpci2dma_channel_isr_unregister(chan_no);
1148
1149	/* Free the cid */
1150	priv->channel[chan_no].ptr = NULL;
1151
1152	/* Remove the ISR */
1153	priv->channel[chan_no].isr = NULL;
1154	priv->channel[chan_no].isr_arg = NULL;
1155
1156	/* Deallocate channel if needed */
1157	if (priv->channel[chan_no].allocated){
1158	grpci2dma_channel_delete((void *)chan);
1159	}
1160
1161	/* Decrease number of channels */
1162	priv->nchans--;
1163
1164	DBG("number of channels: %d\n", priv->nchans);
1165
1166	/* Everything OK */
1167	return GRPCI2DMA_ERR_OK;
1168	}
1169
1170	/* Register channel ISR */
1171	STATIC int grpci2dma_channel_isr_unregister(int chan_no)
1172	{
1173	struct grpci2dma_priv *priv = grpci2dmapriv;
1174	SPIN_IRQFLAGS(irqflags);
1175
1176	/* Unregister channel ISR */
1177	priv->channel[chan_no].isr = NULL;
1178	priv->channel[chan_no].isr_arg = NULL;
1179
1180	/* Unregister DMA ISR in GRPCI2 if needed */
1181	priv->isr_registered--;
1182	if(priv->isr_registered == 0){
1183	/* Disable DMA Interrupts */
1184	SPIN_LOCK_IRQ(&priv->devlock, irqflags);
1185	grpci2dma_ctrl_interrupt_disable();
1186	SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
1187	(priv->isr_register)( NULL, NULL);
1188	}
1189
1190	/* Everything OK */
1191	return GRPCI2DMA_ERR_OK;
1192	}
1193
1194	/* END OF CHANNEL FUNCTIONS */
1195
1196	/* START OF ISR FUNCTIONS */
1197
1198	/* PCI DMA Interrupt handler, called when there is a PCI DMA interrupt */
1199	STATIC void grpci2dma_isr(void *arg)
1200	{
1201	struct grpci2dma_priv *priv = arg;
1202	SPIN_ISR_IRQFLAGS(irqflags);
1203	unsigned int ctrl = grpci2dma_ctrl_status();
1204	/* Clear Interrupts */
1205	SPIN_LOCK(&priv->devlock, irqflags);
1206	grpci2dma_ctrl_interrupt_clear();
1207	SPIN_UNLOCK(&priv->devlock, irqflags);
1208	unsigned int sts = (ctrl & DMACTRL_CHIRQ) >> DMACTRL_CHIRQ_BIT;
1209	unsigned int errsts = (ctrl & DMACTRL_ERR);
1210
1211	/* Error interrupt */
1212	if(errsts){
1213	/* Find which channels had the error.
1214	* The GRPCI2DMA core does not indicate which channel
1215	* had the error, so we need to get 1st the base descriptor register
1216	* and see if it a channel. If is not a channel, then the active
1217	* channel register tells us which channel is.
1218	* After having the channel we need to find out which channel was. */
1219	struct grpci2_bd_chan * chan =
1220	(struct grpci2_bd_chan *) grpci2dma_ctrl_base();
1221	/* Check if the base is a channel descriptor */
1222	if ((BD_READ(&chan->ctrl) & BD_CHAN_TYPE) != BD_CHAN_TYPE_DMA){
1223	/* Is not a channel, so the channel is in the channel active
1224	* register */
1225	chan = (struct grpci2_bd_chan *) grpci2dma_ctrl_active();
1226	}
1227	int i;
1228	for (i=0; i<MAX_DMA_CHANS; i++){
1229	if (chan == priv->channel[i].ptr){
1230	/* Found */
1231	if (priv->channel[i].isr != NULL){
1232	(priv->channel[i].isr)(priv->channel[i].isr_arg,i,errsts);
1233	}else{
1234	printk("Unhandled GRPCI2 DMA error interrupt, sts:0x%02x\n", errsts);
1235	}
1236	break;
1237	}
1238	}
1239	if (i == MAX_DMA_CHANS){
1240	printk("Unhandled GRPCI2 DMA error interrupt , sts:0x%02x\n", errsts);
1241	}
1242	}
1243
1244	/* Normal packet interrupt */
1245	int cid=0;
1246	/* Find which channels have interrupts */
1247	while(sts){
1248	/* Find if current channel has an interrupt*/
1249	if(sts & 0x1){
1250	/* Find if current channel has an ISR */
1251	if (priv->channel[cid].isr != NULL){
1252	(priv->channel[cid].isr)(
1253	priv->channel[cid].isr_arg, cid, errsts);
1254	}else{
1255	printk("Unhandled GRPCI2 DMA interrupt in channel %d, sts:0x%02x\n", cid, 0);
1256	}
1257	}
1258	/* Next channel */
1259	sts = sts >> 1;
1260	cid++;
1261	}
1262	}
1263
1264	/* END OF ISR FUNCTIONS */
1265
1266	/* START OF DEBUG HELPERS */
1267	#ifdef DEBUG
1268	STATIC int grpci2dma_channel_print(struct grpci2_bd_chan * chan)
1269	{
1270	printf(" GRPCI2 DMA channel descriptor\n");
1271	printf(" 0x%08x DMA channel control 0x%08x\n", (unsigned int) chan, chan->ctrl);
1272	printf(" 31 en 0x%01x Channel descriptor enable.\n", (chan->ctrl >> 31) & (0x1));
1273	printf(" 24:22 cid 0x%01x Channel ID.\n", (chan->ctrl >> 22) & (0x7));
1274	printf(" 21:20 type 0x%01x Descriptor type. 01=DMA channel descriptor.\n", (chan->ctrl >> 20) & (0x3));
1275	printf(" 15:0 dlen 0x%04x Data descriptor count.\n", (chan->ctrl >> 0) & (0xffff));
1276	printf("\n");
1277	printf(" 0x%08x Next DMA channel 0x%08x\n", (unsigned int) &(chan->nchan), chan->nchan);
1278	printf(" 31:0 nc 0x%08x Next DMA channel.\n", chan->nchan);
1279	printf("\n");
1280	printf(" 0x%08x Next data descriptor 0x%08x\n" , (unsigned int) &(chan->nbd), chan->nbd);
1281	printf(" 31:0 nd 0x%08x Next data descriptor.\n", chan->nbd);
1282	printf("\n");
1283	return 0;
1284	}
1285
1286	STATIC int grpci2dma_data_print(struct grpci2_bd_data * data)
1287	{
1288	printf(" GRPCI2 DMA data descriptor\n");
1289	printf(" 0x%08x DMA data control 0x%08x\n", (unsigned int) data, data->ctrl);
1290	printf(" 31 en 0x%01x Data descriptor enable.\n" , (data->ctrl >> 31) & (0x1));
1291	printf(" 30 ie 0x%01x Interrupt generation enable.\n" , (data->ctrl >> 30) & (0x1));
1292	printf(" 29 dr 0x%01x Tranfer direction.\n" , (data->ctrl >> 29) & (0x1));
1293	printf(" 28 be 0x%01x Bus endianess.\n" , (data->ctrl >> 28) & (0x1));
1294	printf(" 21:20 type 0x%01x Descriptor type. 00=DMA data descriptor.\n" , (data->ctrl >> 20) & (0x3));
1295	printf(" 19 er 0x%01x Error status.\n" , (data->ctrl >> 19) & (0x1));
1296	printf(" 15:0 len 0x%04x Transfer lenght (in words) - 1.\n" , (data->ctrl >> 0) & (0xffff));
1297	printf("\n");
1298	printf(" 0x%08x 32-bit PCI start address 0x%08x\n" , (unsigned int) &(data->pci_adr), data->pci_adr);
1299	printf(" 31:0 pa 0x%08x PCI address.\n" , data->pci_adr);
1300	printf("\n");
1301	printf(" 0x%08x 32-bit AHB start address 0x%08x\n" , (unsigned int) &(data->ahb_adr), data->ahb_adr);
1302	printf(" 31:0 aa 0x%08x AHB address.\n" , data->ahb_adr);
1303	printf("\n");
1304	printf(" 0x%08x Next data descriptor 0x%08x\n" , (unsigned int) &(data->next), data->next);
1305	printf(" 31:0 nd 0x%08x Next data descriptor.\n" , data->next);
1306	printf("\n");
1307	return 0;
1308	}
1309	#endif
1310	/* END OF DEBUG HELPERS */
1311
1312	/* START OF MEMORY ALLOCATION FUNCTIONS */
1313
1314	void * grpci2dma_channel_new(int number)
1315	{
1316	/* Allocate memory */
1317	unsigned int * orig_ptr = (unsigned int *) malloc(
1318	(GRPCI2DMA_BD_CHAN_SIZE)*number + GRPCI2DMA_BD_CHAN_ALIGN);
1319	if (orig_ptr == NULL) return NULL;
1320
1321	/* Get the aligned pointer */
1322	unsigned int aligned_ptr = (
1323	((unsigned int) orig_ptr + GRPCI2DMA_BD_CHAN_ALIGN) &
1324	~(GRPCI2DMA_BD_CHAN_ALIGN - 1));
1325
1326	/* Save the original pointer just before the aligned pointer */
1327	unsigned int ** tmp_ptr =
1328	(unsigned int **) (aligned_ptr - sizeof(orig_ptr));
1329	*tmp_ptr= orig_ptr;
1330
1331	/* Return aligned pointer */
1332	return (void *) aligned_ptr;
1333	}
1334
1335	void grpci2dma_channel_delete(void * chan)
1336	{
1337	/* Recover orignal pointer placed just before the aligned pointer */
1338	unsigned int * orig_ptr;
1339	unsigned int tmp_ptr = (unsigned int ) (chan - sizeof(orig_ptr));
1340	orig_ptr = *tmp_ptr;
1341
1342	/* Deallocate memory */
1343	free(orig_ptr);
1344	}
1345
1346	void * grpci2dma_data_new(int number)
1347	{
1348	/* Allocate memory */
1349	unsigned int * orig_ptr = (unsigned int *) malloc(
1350	(GRPCI2DMA_BD_DATA_SIZE)*number + GRPCI2DMA_BD_DATA_ALIGN);
1351	if (orig_ptr == NULL) return NULL;
1352
1353	/* Get the aligned pointer */
1354	unsigned int aligned_ptr = (
1355	((unsigned int) orig_ptr + GRPCI2DMA_BD_DATA_ALIGN) &
1356	~(GRPCI2DMA_BD_DATA_ALIGN - 1));
1357
1358	/* Save the original pointer before the aligned pointer */
1359	unsigned int ** tmp_ptr =
1360	(unsigned int **) (aligned_ptr - sizeof(orig_ptr));
1361	*tmp_ptr= orig_ptr;
1362
1363	/* Return aligned pointer */
1364	return (void *) aligned_ptr;
1365	}
1366
1367	void grpci2dma_data_delete(void * data)
1368	{
1369	/* Recover orignal pointer placed just before the aligned pointer */
1370	unsigned int * orig_ptr;
1371	unsigned int tmp_ptr = (unsigned int ) (data - sizeof(orig_ptr));
1372	orig_ptr = *tmp_ptr;
1373
1374	/* Deallocate memory */
1375	free(orig_ptr);
1376	}
1377
1378	/* END OF MEMORY ALLOCATION FUNCTIONS */
1379
1380	/* START OF USER API */
1381
1382	/* Initialize GRPCI2 DMA: GRPCI2 DRIVER calls this
1383	* using a weak function definition */
1384	int grpci2dma_init(
1385	void * regs, void isr_register( void (isr)(void), void * arg))
1386	{
1387	struct grpci2dma_priv *priv;
1388	int i;
1389
1390	DBG("Registering GRPCI2 DMA driver with arg: 0x%08x\n",
1391	(unsigned int) regs);
1392
1393	/* We only allow one GRPCI2 DMA */
1394	if (grpci2dmapriv) {
1395	DBG("Driver only supports one PCI DMA core\n");
1396	return DRVMGR_FAIL;
1397	}
1398
1399	/* Device Semaphore created with count = 1 */
1400	if (rtems_semaphore_create(rtems_build_name('G', 'P', '2', 'D'), 1,
1401	RTEMS_FIFO \| RTEMS_SIMPLE_BINARY_SEMAPHORE \| \
1402	RTEMS_NO_INHERIT_PRIORITY \| RTEMS_LOCAL \| \
1403	RTEMS_NO_PRIORITY_CEILING, 0, &grpci2dma_sem) != RTEMS_SUCCESSFUL)
1404	return -1;
1405
1406	/* Allocate and init Memory for DMA */
1407	int size = sizeof(struct grpci2dma_priv);
1408	priv = (struct grpci2dma_priv *) malloc(size);
1409	if (priv == NULL)
1410	return DRVMGR_NOMEM;
1411
1412	/* Initialize all fields */
1413	memset(priv, 0, size);
1414	priv->regs = regs;
1415	strncpy(&priv->devname[0], "grpci2dma0", DEVNAME_LEN);
1416
1417	/* Initialize Spin-lock for GRPCI2dma Device. */
1418	SPIN_INIT(&priv->devlock, priv->devname);
1419
1420	/* Channel Sempahores */
1421	for (i=0; i<MAX_DMA_CHANS; i++){
1422	/* set to NULL, they are created when openning channels */
1423	priv->channel[i].sem = RTEMS_ID_NONE;
1424	}
1425
1426	/* Register device */
1427	grpci2dmapriv = priv;
1428
1429	/* Initialize Ctrl regs */
1430	grpci2dma_ctrl_init();
1431
1432	/* Install DMA ISR */
1433	priv->isr_register = isr_register;
1434
1435	/* Startup actions:
1436	* - stop DMA
1437	*/
1438	grpci2dma_ctrl_stop();
1439
1440	return DRVMGR_OK;
1441	}
1442
1443	/* Assign ISR Function to DMA IRQ */
1444	int grpci2dma_isr_register(int chan_no, grpci2dma_isr_t dmaisr, void *data)
1445	{
1446	struct grpci2dma_priv *priv = grpci2dmapriv;
1447	SPIN_IRQFLAGS(irqflags);
1448
1449	if (!priv){
1450	/* DMA not initialized */
1451	return GRPCI2DMA_ERR_NOINIT;
1452	}
1453
1454	/* Check isr */
1455	if (dmaisr == NULL){
1456	/* No ISR */
1457	return GRPCI2DMA_ERR_WRONGPTR;
1458	}
1459
1460	/* Get chan pointer */
1461	if ((chan_no < 0 ) \|\| (chan_no >= MAX_DMA_CHANS)) {
1462	/* Wrong channel id */
1463	return GRPCI2DMA_ERR_WRONGPTR;
1464	}
1465
1466	/* Check chan is open */
1467	if (priv->channel[chan_no].ptr == NULL){
1468	/* No channel */
1469	return GRPCI2DMA_ERR_NOTFOUND;
1470	}
1471
1472	/* Take driver lock - Wait until we get semaphore */
1473	if (rtems_semaphore_obtain(grpci2dma_sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1474	!= RTEMS_SUCCESSFUL){
1475	return GRPCI2DMA_ERR_ERROR;
1476	}
1477
1478	/* Take channel lock - Wait until we get semaphore */
1479	if (rtems_semaphore_obtain(priv->channel[chan_no].sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1480	!= RTEMS_SUCCESSFUL){
1481	rtems_semaphore_release(grpci2dma_sem);
1482	return GRPCI2DMA_ERR_ERROR;
1483	}
1484
1485	/* Register channel ISR */
1486	priv->channel[chan_no].isr_arg = data;
1487	priv->channel[chan_no].isr = dmaisr;
1488
1489	/* Register DMA ISR in GRPCI2 if not done yet */
1490	if(priv->isr_registered == 0){
1491	(priv->isr_register)( grpci2dma_isr, (void *) priv);
1492	/* Enable DMA Interrupts */
1493	SPIN_LOCK_IRQ(&priv->devlock, irqflags);
1494	grpci2dma_ctrl_interrupt_enable();
1495	SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
1496	}
1497	priv->isr_registered++;
1498
1499	/* Release channel sempahore */
1500	rtems_semaphore_release(priv->channel[chan_no].sem);
1501
1502	/* Release driver sempahore */
1503	rtems_semaphore_release(grpci2dma_sem);
1504
1505	return GRPCI2DMA_ERR_OK;
1506	}
1507
1508	/* Assign ISR Function to DMA IRQ */
1509	int grpci2dma_isr_unregister(int chan_no)
1510	{
1511	struct grpci2dma_priv *priv = grpci2dmapriv;
1512	int ret;
1513
1514	if (!priv){
1515	/* DMA not initialized */
1516	return GRPCI2DMA_ERR_NOINIT;
1517	}
1518
1519	/* Get chan pointer */
1520	if ((chan_no < 0 ) \|\| (chan_no >= MAX_DMA_CHANS)) {
1521	/* Wrong channel id */
1522	return GRPCI2DMA_ERR_WRONGPTR;
1523	}
1524
1525	/* Check chan is open */
1526	if (priv->channel[chan_no].ptr == NULL){
1527	/* No channel */
1528	return GRPCI2DMA_ERR_NOTFOUND;
1529	}
1530
1531	/* Get chan ISR */
1532	if (priv->channel[chan_no].isr == NULL){
1533	/* Nothing to do */
1534	return GRPCI2DMA_ERR_OK;
1535	}
1536
1537	/* Take driver lock - Wait until we get semaphore */
1538	if (rtems_semaphore_obtain(grpci2dma_sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1539	!= RTEMS_SUCCESSFUL){
1540	return GRPCI2DMA_ERR_ERROR;
1541	}
1542
1543	/* Take channel lock - Wait until we get semaphore */
1544	if (rtems_semaphore_obtain(priv->channel[chan_no].sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1545	!= RTEMS_SUCCESSFUL){
1546	rtems_semaphore_release(grpci2dma_sem);
1547	return GRPCI2DMA_ERR_ERROR;
1548	}
1549
1550	/* Unregister channel ISR */
1551	ret = grpci2dma_channel_isr_unregister(chan_no);
1552
1553	/* Release channel sempahore */
1554	rtems_semaphore_release(priv->channel[chan_no].sem);
1555
1556	/* Release driver sempahore */
1557	rtems_semaphore_release(grpci2dma_sem);
1558
1559	return ret;
1560	}
1561
1562	int grpci2dma_open(void * chanptr)
1563	{
1564	struct grpci2dma_priv *priv = grpci2dmapriv;
1565	int cid;
1566	int ret;
1567
1568	if (!priv){
1569	/* DMA not initialized */
1570	return GRPCI2DMA_ERR_NOINIT;
1571	}
1572
1573	/* Check alignment */
1574	if (((unsigned int ) chanptr) & (GRPCI2DMA_BD_CHAN_ALIGN-1)) {
1575	/* Channel is not properly aligned */
1576	return GRPCI2DMA_ERR_WRONGPTR;
1577	}
1578
1579	/* Take driver lock - Wait until we get semaphore */
1580	if (rtems_semaphore_obtain(grpci2dma_sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1581	!= RTEMS_SUCCESSFUL){
1582	return GRPCI2DMA_ERR_ERROR;
1583	}
1584
1585	/* Get free channel id */
1586	cid = grpci2dma_channel_free_id();
1587	if (cid < 0 ){
1588	rtems_semaphore_release(grpci2dma_sem);
1589	return GRPCI2DMA_ERR_TOOMANY;
1590	}
1591
1592	/* Open channel */
1593	ret = grpci2dma_channel_open((struct grpci2_bd_chan *) chanptr, cid);
1594
1595	/* Create channel semaphore with count = 1 */
1596	if (ret >= 0){
1597	if (rtems_semaphore_create(
1598	rtems_build_name('P', 'D', '0', '0' + cid), 1,
1599	RTEMS_FIFO \| RTEMS_SIMPLE_BINARY_SEMAPHORE \| \
1600	RTEMS_NO_INHERIT_PRIORITY \| RTEMS_LOCAL \| \
1601	RTEMS_NO_PRIORITY_CEILING, 0, &priv->channel[cid].sem
1602	) != RTEMS_SUCCESSFUL) {
1603	priv->channel[cid].sem = RTEMS_ID_NONE;
1604	rtems_semaphore_release(grpci2dma_sem);
1605	return GRPCI2DMA_ERR_ERROR;
1606	}
1607	}
1608
1609	/* Release driver semaphore */
1610	rtems_semaphore_release(grpci2dma_sem);
1611
1612	/* Return channel id */
1613	return ret;
1614	}
1615
1616	int grpci2dma_close(int chan_no)
1617	{
1618	struct grpci2dma_priv *priv = grpci2dmapriv;
1619	int ret;
1620
1621	if (!priv){
1622	/* DMA not initialized */
1623	return GRPCI2DMA_ERR_NOINIT;
1624	}
1625
1626	/* Get chan pointer */
1627	if ((chan_no < 0) \|\| (chan_no >= MAX_DMA_CHANS)){
1628	/* Wrong channel id */
1629	return GRPCI2DMA_ERR_WRONGPTR;
1630	}
1631
1632	/* Check chan is open */
1633	if (priv->channel[chan_no].ptr == NULL){
1634	/* No channel */
1635	return GRPCI2DMA_ERR_NOTFOUND;
1636	}
1637
1638	/* Take driver lock - Wait until we get semaphore */
1639	if (rtems_semaphore_obtain(grpci2dma_sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1640	!= RTEMS_SUCCESSFUL){
1641	return GRPCI2DMA_ERR_ERROR;
1642	}
1643
1644	/* Take channel lock - Wait until we get semaphore */
1645	if (rtems_semaphore_obtain(priv->channel[chan_no].sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1646	!= RTEMS_SUCCESSFUL){
1647	rtems_semaphore_release(grpci2dma_sem);
1648	return GRPCI2DMA_ERR_ERROR;
1649	}
1650
1651	/* Close channel */
1652	ret = grpci2dma_channel_close(chan_no);
1653
1654	/* Release channel sempahore */
1655	rtems_semaphore_release(priv->channel[chan_no].sem);
1656
1657	/* Delete channel semaphore */
1658	if (ret == GRPCI2DMA_ERR_OK){
1659	if (rtems_semaphore_delete(priv->channel[chan_no].sem)
1660	!= RTEMS_SUCCESSFUL){
1661	/* Release driver semaphore */
1662	rtems_semaphore_release(grpci2dma_sem);
1663	return GRPCI2DMA_ERR_ERROR;
1664	}
1665	}
1666
1667	/* Release driver semaphore */
1668	rtems_semaphore_release(grpci2dma_sem);
1669
1670	return ret;
1671	}
1672
1673	/* Transfer_size =0 means maximum */
1674	int grpci2dma_prepare(
1675	uint32_t pci_start, uint32_t ahb_start, int dir, int endianness,
1676	int size, void * dataptr, int index, int ndata, int transfer_size)
1677	{
1678	struct grpci2_bd_data * data = dataptr;
1679
1680	/* Check data pointer */
1681	if ((data == NULL) \|\|
1682	(((unsigned int ) data) & (GRPCI2DMA_BD_DATA_ALIGN-1))){
1683	return GRPCI2DMA_ERR_WRONGPTR;
1684	}
1685
1686	/* Check indexes */
1687	int maxdata = ndata - index;
1688	if ((maxdata < 1) \|\| (index < 0)){
1689	/* No data descriptors to use */
1690	return GRPCI2DMA_ERR_WRONGPTR;
1691	}
1692
1693	/* Check PCI transfer size */
1694	if ( (transfer_size < 0) \|\|
1695	(transfer_size > MAX_DMA_TRANSFER_SIZE) \|\|
1696	(transfer_size%4 != 0) ) {
1697	return GRPCI2DMA_ERR_WRONGPTR;
1698	}
1699	if (transfer_size == 0){
1700	transfer_size = MAX_DMA_TRANSFER_SIZE;
1701	}
1702
1703	/* Check total size */
1704	if ( (size <=0) \|\| (size % 4 != 0)){
1705	return GRPCI2DMA_ERR_WRONGPTR;
1706	}
1707
1708	/* Calculate number of data descriptors needed */
1709	int words = size/4;
1710	int blocksize = transfer_size/4;
1711	int datacnt = words/blocksize + (words%blocksize != 0? 1: 0);
1712	/* Check that we can transfer the data */
1713	if (datacnt > maxdata) {
1714	return GRPCI2DMA_ERR_TOOMANY;
1715	}
1716
1717	/* Prepare data descriptors */
1718	int i;
1719	uint32_t pci_adr;
1720	uint32_t ahb_adr;
1721	int remaining=words;
1722	int datasize;
1723	struct grpci2_bd_data * next;
1724	for (i=0; i<datacnt; i++){
1725	/* Get PCI and AHB start addresses */
1726	pci_adr = pci_start + i*blocksize;
1727	ahb_adr = ahb_start + i*blocksize;
1728	/* Get current data size */
1729	if (remaining >= blocksize){
1730	datasize = blocksize - 1;
1731	remaining -= blocksize;
1732	} else {
1733	datasize = remaining -1;
1734	remaining = 0;
1735	}
1736	/* Get linked list pointers */
1737	if (i == datacnt - 1){
1738	/* Last transfer */
1739	next = DISABLED_DESCRIPTOR;
1740	}else{
1741	next = &data[i+index+1];
1742	}
1743	/* Set Data descriptor */
1744	grpci2dma_data_bd_init(&data[i+index], pci_adr, ahb_adr, dir, endianness, datasize, next);
1745	}
1746	/* Return number of transfers used */
1747	return datacnt;
1748	}
1749
1750	int grpci2dma_status(void *dataptr, int index, int ndata)
1751	{
1752	struct grpci2_bd_data * data = dataptr;
1753	int i;
1754
1755	/* Check data pointer */
1756	if ((data == NULL) \|\|
1757	(((unsigned int ) data) & (GRPCI2DMA_BD_DATA_ALIGN-1))){
1758	return GRPCI2DMA_ERR_WRONGPTR;
1759	}
1760
1761	/* Check maxdata */
1762	int maxdata = ndata - index;
1763	if ((maxdata < 1) \|\| (index < 0)){
1764	/* No data descriptors to use */
1765	return GRPCI2DMA_ERR_WRONGPTR;
1766	}
1767
1768	/* Check status of all packets in transfer */
1769	int status;
1770	for (i=0; i< maxdata; i++){
1771	status = grpci2dma_data_bd_status(&data[i+index]);
1772	if (status == GRPCI2DMA_BD_STATUS_ERR){
1773	/* Error in one packet, means error in transfer */
1774	return status;
1775	} else if (status == GRPCI2DMA_BD_STATUS_ENABLED){
1776	/* If one packet is enabled, means transfer is not done */
1777	return status;
1778	}
1779	}
1780
1781	/* If we reach here it means they are all disabled */
1782	return status;
1783	}
1784
1785	int grpci2dma_print(int chan_no)
1786	{
1787	struct grpci2dma_priv *priv = grpci2dmapriv;
1788	struct grpci2_bd_chan * chan;
1789
1790	if (!priv){
1791	/* DMA not initialized */
1792	DBG("DMA not initialized.\n");
1793	return GRPCI2DMA_ERR_NOINIT;
1794	}
1795
1796	if ( (chan_no < 0) \|\| (chan_no >= MAX_DMA_CHANS )){
1797	/* Wrong chan no*/
1798	return GRPCI2DMA_ERR_WRONGPTR;
1799	}
1800
1801	chan = priv->channel[chan_no].ptr;
1802	if (chan == NULL) {
1803	return GRPCI2DMA_ERR_WRONGPTR;
1804	}
1805
1806	#ifdef DEBUG
1807	/* Print channel state */
1808	grpci2dma_channel_print(chan);
1809
1810	/* Get current DATA desc */
1811	struct grpci2_bd_data * first_data = (struct grpci2_bd_data *) BD_READ(&chan->nbd);
1812
1813	/* Print data state */
1814	grpci2dma_data_list_foreach(first_data, grpci2dma_data_print, MAX_DMA_DATA);
1815	#endif
1816	return GRPCI2DMA_ERR_OK;
1817	}
1818
1819	int grpci2dma_print_bd(void * dataptr)
1820	{
1821	struct grpci2dma_priv *priv = grpci2dmapriv;
1822	struct grpci2_bd_data * data = (struct grpci2_bd_data *) dataptr;
1823
1824	if (!priv){
1825	/* DMA not initialized */
1826	DBG("DMA not initialized.\n");
1827	return GRPCI2DMA_ERR_NOINIT;
1828	}
1829
1830	if ( data == NULL ){
1831	/* Wrong chan no*/
1832	return GRPCI2DMA_ERR_WRONGPTR;
1833	}
1834
1835	#ifdef DEBUG
1836	/* Print data state */
1837	grpci2dma_data_list_foreach(data, grpci2dma_data_print, MAX_DMA_DATA);
1838	#endif
1839	return GRPCI2DMA_ERR_OK;
1840	}
1841
1842	int grpci2dma_interrupt_enable(
1843	void *dataptr, int index, int maxindex, int options)
1844	{
1845	struct grpci2_bd_data * data = dataptr;
1846	struct grpci2dma_priv *priv = grpci2dmapriv;
1847	SPIN_IRQFLAGS(irqflags);
1848
1849	if (!priv){
1850	/* DMA not initialized */
1851	return GRPCI2DMA_ERR_NOINIT;
1852	}
1853
1854	/* Check data pointer */
1855	if ((data == NULL) \|\|
1856	(((unsigned int ) data) & (GRPCI2DMA_BD_DATA_ALIGN-1))){
1857	return GRPCI2DMA_ERR_WRONGPTR;
1858	}
1859
1860	/* Check index */
1861	if ((index < 0) \|\| (maxindex < 1) \|\| (index >= maxindex)){
1862	/* No data descriptors to use */
1863	return GRPCI2DMA_ERR_WRONGPTR;
1864	}
1865
1866	if (options & GRPCI2DMA_OPTIONS_ALL){
1867	/* Enable all interrupts */
1868	if (grpci2dma_data_list_foreach(
1869	&data[index],
1870	grpci2dma_data_bd_interrupt_enable, maxindex -index)){
1871	return GRPCI2DMA_ERR_ERROR;
1872	}
1873	}else{
1874	/* Enable one packet interrupts */
1875	grpci2dma_data_bd_interrupt_enable(&data[index]);
1876	}
1877
1878	/* Finally enable DMA interrupts if they are not already enabled */
1879	if (grpci2dma_ctrl_interrupt_status()==0){
1880	SPIN_LOCK_IRQ(&priv->devlock, irqflags);
1881	grpci2dma_ctrl_interrupt_enable();
1882	SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
1883	}
1884
1885	DBG("Interrupts enabled for data (0x%08x), index:%d, maxindex:%d, %s.\n",
1886	(unsigned int) data, index, maxindex,
1887	(options & GRPCI2DMA_OPTIONS_ALL)? "ALL":"ONE" );
1888
1889	return GRPCI2DMA_ERR_OK;
1890	}
1891
1892	int grpci2dma_push(int chan_no, void *dataptr, int index, int ndata)
1893	{
1894	struct grpci2dma_priv *priv = grpci2dmapriv;
1895	SPIN_IRQFLAGS(irqflags);
1896	int ret;
1897
1898	if (!priv){
1899	/* DMA not initialized */
1900	return GRPCI2DMA_ERR_NOINIT;
1901	}
1902
1903	/* Check data pointer */
1904	if ((dataptr == NULL) \|\|
1905	(((unsigned int ) dataptr) & (GRPCI2DMA_BD_DATA_ALIGN-1))){
1906	return GRPCI2DMA_ERR_WRONGPTR;
1907	}
1908
1909	/* Check index */
1910	if ((ndata < 1) \|\| (index < 0)){
1911	/* No data descriptors to use */
1912	return GRPCI2DMA_ERR_WRONGPTR;
1913	}
1914
1915	/* Check chan_no */
1916	if ( (chan_no < 0) \|\| (chan_no >= MAX_DMA_CHANS )){
1917	/* Wrong chan no*/
1918	return GRPCI2DMA_ERR_WRONGPTR;
1919	}
1920
1921	/* Check chan is open */
1922	if (priv->channel[chan_no].ptr == NULL){
1923	/* No channel */
1924	return GRPCI2DMA_ERR_NOTFOUND;
1925	}
1926
1927	/* Take channel lock - Wait until we get semaphore */
1928	if (rtems_semaphore_obtain(priv->channel[chan_no].sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1929	!= RTEMS_SUCCESSFUL){
1930	return GRPCI2DMA_ERR_ERROR;
1931	}
1932
1933	/* push data to channel */
1934	ret = grpci2dma_channel_push(chan_no, dataptr, index, ndata);
1935
1936	if (ret != GRPCI2DMA_ERR_OK){
1937	/* Release channel lock */
1938	rtems_semaphore_release(priv->channel[chan_no].sem);
1939	return ret;
1940	}
1941
1942	/* Start DMA if it is not active and channel is active*/
1943	SPIN_LOCK_IRQ(&priv->devlock, irqflags);
1944	if ((!grpci2dma_active()) && (priv->channel[chan_no].active)){
1945	grpci2dma_ctrl_start(priv->channel[chan_no].ptr);
1946	}
1947	SPIN_UNLOCK_IRQ(&priv->devlock, irqflags);
1948
1949	/* Release channel lock */
1950	rtems_semaphore_release(priv->channel[chan_no].sem);
1951
1952	return ret;
1953	}
1954
1955	/* Start the channel */
1956	int grpci2dma_start(int chan_no, int options)
1957	{
1958	struct grpci2dma_priv *priv = grpci2dmapriv;
1959	int ret;
1960
1961	if (!priv){
1962	/* DMA not initialized */
1963	return GRPCI2DMA_ERR_NOINIT;
1964	}
1965
1966	if ((chan_no < 0 ) \|\| (chan_no >= MAX_DMA_CHANS )) {
1967	/* Wrong channel id */
1968	return GRPCI2DMA_ERR_WRONGPTR;
1969	}
1970
1971	if ( options < 0 ) {
1972	/* Wrong options */
1973	return GRPCI2DMA_ERR_WRONGPTR;
1974	}
1975
1976	/* Check chan is open */
1977	if (priv->channel[chan_no].ptr == NULL){
1978	/* No channel */
1979	return GRPCI2DMA_ERR_NOTFOUND;
1980	}
1981
1982	/* Take driver lock - Wait until we get semaphore */
1983	if (rtems_semaphore_obtain(grpci2dma_sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1984	!= RTEMS_SUCCESSFUL){
1985	return GRPCI2DMA_ERR_ERROR;
1986	}
1987
1988	/* Take channel lock - Wait until we get semaphore */
1989	if (rtems_semaphore_obtain(priv->channel[chan_no].sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
1990	!= RTEMS_SUCCESSFUL){
1991	rtems_semaphore_release(grpci2dma_sem);
1992	return GRPCI2DMA_ERR_ERROR;
1993	}
1994
1995	/* Start the channel */
1996	ret = grpci2dma_channel_start(chan_no, options);
1997
1998	/* Release channel lock */
1999	rtems_semaphore_release(priv->channel[chan_no].sem);
2000
2001	/* Release driver lock */
2002	rtems_semaphore_release(grpci2dma_sem);
2003
2004	return ret;
2005	}
2006
2007	/* Stop the channel, but don't stop ongoing transfers! */
2008	int grpci2dma_stop(int chan_no)
2009	{
2010	struct grpci2dma_priv *priv = grpci2dmapriv;
2011	int ret;
2012
2013	if (!priv){
2014	/* DMA not initialized */
2015	return GRPCI2DMA_ERR_NOINIT;
2016	}
2017
2018	if ((chan_no < 0 ) \|\| (chan_no >= MAX_DMA_CHANS)) {
2019	/* Wrong channel id */
2020	return GRPCI2DMA_ERR_WRONGPTR;
2021	}
2022
2023	/* Check chan is open */
2024	if (priv->channel[chan_no].ptr == NULL){
2025	/* No channel */
2026	return GRPCI2DMA_ERR_NOTFOUND;
2027	}
2028
2029	/* Take driver lock - Wait until we get semaphore */
2030	if (rtems_semaphore_obtain(grpci2dma_sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
2031	!= RTEMS_SUCCESSFUL){
2032	return GRPCI2DMA_ERR_ERROR;
2033	}
2034
2035	/* Take channel lock - Wait until we get semaphore */
2036	if (rtems_semaphore_obtain(priv->channel[chan_no].sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT)
2037	!= RTEMS_SUCCESSFUL){
2038	rtems_semaphore_release(grpci2dma_sem);
2039	return GRPCI2DMA_ERR_ERROR;
2040	}
2041
2042	/* Stop the channel */
2043	ret = grpci2dma_channel_stop(chan_no);
2044
2045	/* Release channel lock */
2046	rtems_semaphore_release(priv->channel[chan_no].sem);
2047
2048	/* Release driver lock */
2049	rtems_semaphore_release(grpci2dma_sem);
2050
2051	return ret;
2052	}
2053
2054	int grpci2dma_active()
2055	{
2056	return ((grpci2dma_ctrl_status()) & DMACTRL_ACT) >> DMACTRL_ACT_BIT;
2057	}
2058

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