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source: rtems/c/src/lib/libbsp/sparc/shared/pci/grpci2.c @ f46f5f84

5

Last change on this file since f46f5f84 was f46f5f84, checked in by Javier Jalle <javier.jalle@…>, on 02/13/17 at 09:16:14
leon, grpci2: latency timer user configurable (default 64)
Property mode set to `100644`
File size: 24.9 KB

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1	/* GRLIB GRPCI2 PCI HOST driver.
2	*
3	* COPYRIGHT (c) 2011
4	* Cobham Gaisler AB.
5	*
6	* The license and distribution terms for this file may be
7	* found in found in the file LICENSE in this distribution or at
8	* http://www.rtems.org/license/LICENSE.
9	*/
10
11	/* Configures the GRPCI2 core and initialize,
12	* - the PCI Library (pci.c)
13	* - the general part of the PCI Bus driver (pci_bus.c)
14	*
15	* System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
16	* default taken from Plug and Play, but may be overridden by the
17	* driver resources INTA#..INTD#. GRPCI2 handles differently depending
18	* on the design (4 different ways).
19	*
20	* GRPCI2 IRQ implementation notes
21	* -------------------------------
22	* Since the Driver Manager pci_bus layer implements IRQ by calling
23	* pci_interrupt_* which translates into BSP_shared_interrupt_*, and the
24	* root-bus also relies on BSP_shared_interrupt_*, it is safe for the GRPCI2
25	* driver to use the drvmgr_interrupt_* routines since they will be
26	* accessing the same routines in the end. Otherwise the GRPCI2 driver must
27	* have used the pci_interrupt_* routines.
28	*/
29
30	#include <stdlib.h>
31	#include <stdio.h>
32	#include <string.h>
33	#include <rtems/bspIo.h>
34	#include <libcpu/byteorder.h>
35	#include <libcpu/access.h>
36	#include <pci.h>
37	#include <pci/cfg.h>
38
39	#include <drvmgr/drvmgr.h>
40	#include <drvmgr/ambapp_bus.h>
41	#include <ambapp.h>
42	#include <drvmgr/pci_bus.h>
43	#include <bsp/grpci2.h>
44
45	#ifndef IRQ_GLOBAL_PREPARE
46	#define IRQ_GLOBAL_PREPARE(level) rtems_interrupt_level level
47	#endif
48
49	#ifndef IRQ_GLOBAL_DISABLE
50	#define IRQ_GLOBAL_DISABLE(level) rtems_interrupt_disable(level)
51	#endif
52
53	#ifndef IRQ_GLOBAL_ENABLE
54	#define IRQ_GLOBAL_ENABLE(level) rtems_interrupt_enable(level)
55	#endif
56
57	/* If defined to 1 - byte twisting is enabled by default */
58	#define DEFAULT_BT_ENABLED 0
59
60	/* If defined to 64 - Latency timer is 64 by default */
61	#define DEFAULT_LATENCY_TIMER 64
62
63	/* Interrupt assignment. Set to other value than 0xff in order to
64	* override defaults and plug&play information
65	*/
66	#ifndef GRPCI2_INTA_SYSIRQ
67	#define GRPCI2_INTA_SYSIRQ 0xff
68	#endif
69	#ifndef GRPCI2_INTB_SYSIRQ
70	#define GRPCI2_INTB_SYSIRQ 0xff
71	#endif
72	#ifndef GRPCI2_INTC_SYSIRQ
73	#define GRPCI2_INTC_SYSIRQ 0xff
74	#endif
75	#ifndef GRPCI2_INTD_SYSIRQ
76	#define GRPCI2_INTD_SYSIRQ 0xff
77	#endif
78
79	/#define DEBUG 1/
80
81	#ifdef DEBUG
82	#define DBG(x...) printk(x)
83	#else
84	#define DBG(x...)
85	#endif
86
87	/*
88	* GRPCI2 APB Register MAP
89	*/
90	struct grpci2_regs {
91	volatile unsigned int ctrl; /* 0x00 */
92	volatile unsigned int sts_cap; /* 0x04 */
93	volatile unsigned int ppref; /* 0x08 */
94	volatile unsigned int io_map; /* 0x0C */
95	volatile unsigned int dma_ctrl; /* 0x10 */
96	volatile unsigned int dma_bdbase; /* 0x14 */
97	volatile unsigned int dma_chact; /* 0x18 */
98	int res1; /* 0x1C */
99	volatile unsigned int bars[6]; /* 0x20 */
100	int res2[2]; /* 0x38 */
101	volatile unsigned int ahbmst_map[16]; /* 0x40 */
102	};
103
104	#define CTRL_BUS_BIT 16
105
106	#define CTRL_SI (1<<27)
107	#define CTRL_PE (1<<26)
108	#define CTRL_ER (1<<25)
109	#define CTRL_EI (1<<24)
110	#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
111	#define CTRL_HOSTINT 0xf
112
113	#define STS_HOST_BIT 31
114	#define STS_MST_BIT 30
115	#define STS_TAR_BIT 29
116	#define STS_DMA_BIT 28
117	#define STS_DI_BIT 27
118	#define STS_HI_BIT 26
119	#define STS_IRQMODE_BIT 24
120	#define STS_TRACE_BIT 23
121	#define STS_CFGERRVALID_BIT 20
122	#define STS_CFGERR_BIT 19
123	#define STS_INTTYPE_BIT 12
124	#define STS_INTSTS_BIT 8
125	#define STS_FDEPTH_BIT 2
126	#define STS_FNUM_BIT 0
127
128	#define STS_HOST (1<<STS_HOST_BIT)
129	#define STS_MST (1<<STS_MST_BIT)
130	#define STS_TAR (1<<STS_TAR_BIT)
131	#define STS_DMA (1<<STS_DMA_BIT)
132	#define STS_DI (1<<STS_DI_BIT)
133	#define STS_HI (1<<STS_HI_BIT)
134	#define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
135	#define STS_TRACE (1<<STS_TRACE_BIT)
136	#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
137	#define STS_CFGERR (1<<STS_CFGERR_BIT)
138	#define STS_INTTYPE (0x7f<<STS_INTTYPE_BIT)
139	#define STS_INTSTS (0xf<<STS_INTSTS_BIT)
140	#define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
141	#define STS_FNUM (0x3<<STS_FNUM_BIT)
142
143	#define STS_ITIMEOUT (1<<18)
144	#define STS_ISYSERR (1<<17)
145	#define STS_IDMA (1<<16)
146	#define STS_IDMAERR (1<<15)
147	#define STS_IMSTABRT (1<<14)
148	#define STS_ITGTABRT (1<<13)
149	#define STS_IPARERR (1<<12)
150
151	struct grpci2_bd_chan {
152	volatile unsigned int ctrl; /* 0x00 DMA Control */
153	volatile unsigned int nchan; /* 0x04 Next DMA Channel Address */
154	volatile unsigned int nbd; /* 0x08 Next Data Descriptor in channel */
155	volatile unsigned int res; /* 0x0C Reserved */
156	};
157
158	#define BD_CHAN_EN (1<<BD_CHAN_EN_BIT)
159	#define BD_CHAN_ID (0x3<<BD_CHAN_ID_BIT)
160	#define BD_CHAN_TYPE (0x3<<BD_CHAN_TYPE_BIT)
161	#define BD_CHAN_BDCNT (0xffff<<BD_CHAN_BDCNT_BIT)
162	#define BD_CHAN_EN_BIT 31
163	#define BD_CHAN_ID_BIT 22
164	#define BD_CHAN_TYPE_BIT 20
165	#define BD_CHAN_BDCNT_BIT 0
166
167	struct grpci2_bd_data {
168	volatile unsigned int ctrl; /* 0x00 DMA Data Control */
169	volatile unsigned int pci_adr; /* 0x04 PCI Start Address */
170	volatile unsigned int ahb_adr; /* 0x08 AHB Start address */
171	volatile unsigned int next; /* 0x0C Next Data Descriptor in channel */
172	};
173
174	#define BD_DATA_EN (0x1<<BD_DATA_EN_BIT)
175	#define BD_DATA_IE (0x1<<BD_DATA_IE_BIT)
176	#define BD_DATA_DR (0x1<<BD_DATA_DR_BIT)
177	#define BD_DATA_BE (0x1<<BD_DATA_BE_BIT)
178	#define BD_DATA_TYPE (0x3<<BD_DATA_TYPE_BIT)
179	#define BD_DATA_ER (0x1<<BD_DATA_ER_BIT)
180	#define BD_DATA_LEN (0xffff<<BD_DATA_LEN_BIT)
181	#define BD_DATA_EN_BIT 31
182	#define BD_DATA_IE_BIT 30
183	#define BD_DATA_DR_BIT 29
184	#define BD_DATA_BE_BIT 28
185	#define BD_DATA_TYPE_BIT 20
186	#define BD_DATA_ER_BIT 19
187	#define BD_DATA_LEN_BIT 0
188
189	/* GRPCI2 Capability */
190	struct grpci2_cap_first {
191	unsigned int ctrl;
192	unsigned int pci2ahb_map[6];
193	unsigned int ext2ahb_map;
194	unsigned int io_map;
195	unsigned int pcibar_size[6];
196	unsigned int ahb_pref;
197	};
198	#define CAP9_CTRL_OFS 0
199	#define CAP9_BAR_OFS 0x4
200	#define CAP9_IOMAP_OFS 0x20
201	#define CAP9_BARSIZE_OFS 0x24
202	#define CAP9_AHBPREF_OFS 0x3C
203
204	/* Used internally for accessing the PCI bridge's configuration space itself */
205	#define HOST_TGT PCI_DEV(0xff, 0, 0)
206
207	struct grpci2_priv *grpci2priv = NULL;
208
209	/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
210	* to a system interrupt number.
211	*/
212	unsigned char grpci2_pci_irq_table[4] =
213	{
214	/* INTA# */ GRPCI2_INTA_SYSIRQ,
215	/* INTB# */ GRPCI2_INTB_SYSIRQ,
216	/* INTC# */ GRPCI2_INTC_SYSIRQ,
217	/* INTD# */ GRPCI2_INTD_SYSIRQ
218	};
219
220	/* Start of workspace/dynamical area */
221	extern unsigned int _end;
222	#define DMA_START ((unsigned int) &_end)
223
224	/* Default BAR mapping, set BAR0 256MB 1:1 mapped base of CPU RAM */
225	struct grpci2_pcibar_cfg grpci2_default_bar_mapping[6] = {
226	/* BAR0 */ {DMA_START, DMA_START, 0x10000000},
227	/* BAR1 */ {0, 0, 0},
228	/* BAR2 */ {0, 0, 0},
229	/* BAR3 */ {0, 0, 0},
230	/* BAR4 */ {0, 0, 0},
231	/* BAR5 */ {0, 0, 0},
232	};
233
234	/* Driver private data struture */
235	struct grpci2_priv {
236	struct drvmgr_dev *dev;
237	struct grpci2_regs *regs;
238	unsigned char ver;
239	char irq;
240	char irq_mode; /* IRQ Mode from CAPSTS REG */
241	char bt_enabled;
242	unsigned int irq_mask;
243	unsigned int latency_timer;
244
245	struct grpci2_pcibar_cfg *barcfg;
246
247	unsigned int pci_area;
248	unsigned int pci_area_end;
249	unsigned int pci_io;
250	unsigned int pci_conf;
251	unsigned int pci_conf_end;
252
253	uint32_t devVend; /* Host PCI Device/Vendor ID */
254
255	struct drvmgr_map_entry maps_up[7];
256	struct drvmgr_map_entry maps_down[2];
257	struct pcibus_config config;
258	};
259
260	int grpci2_init1(struct drvmgr_dev *dev);
261	int grpci2_init3(struct drvmgr_dev *dev);
262	void grpci2_err_isr(void *arg);
263
264	/* GRPCI2 DRIVER */
265
266	struct drvmgr_drv_ops grpci2_ops =
267	{
268	.init = {grpci2_init1, NULL, grpci2_init3, NULL},
269	.remove = NULL,
270	.info = NULL
271	};
272
273	struct amba_dev_id grpci2_ids[] =
274	{
275	{VENDOR_GAISLER, GAISLER_GRPCI2},
276	{0, 0} /* Mark end of table */
277	};
278
279	struct amba_drv_info grpci2_info =
280	{
281	{
282	DRVMGR_OBJ_DRV, /* Driver */
283	NULL, /* Next driver */
284	NULL, /* Device list */
285	DRIVER_AMBAPP_GAISLER_GRPCI2_ID,/* Driver ID */
286	"GRPCI2_DRV", /* Driver Name */
287	DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
288	&grpci2_ops,
289	NULL, /* Funcs */
290	0, /* No devices yet */
291	sizeof(struct grpci2_priv), /* Make drvmgr alloc private */
292	},
293	&grpci2_ids[0]
294	};
295
296	void grpci2_register_drv(void)
297	{
298	DBG("Registering GRPCI2 driver\n");
299	drvmgr_drv_register(&grpci2_info.general);
300	}
301
302	static int grpci2_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val)
303	{
304	struct grpci2_priv *priv = grpci2priv;
305	volatile uint32_t *pci_conf;
306	unsigned int tmp, devfn;
307	IRQ_GLOBAL_PREPARE(oldLevel);
308	int retval, bus = PCI_DEV_BUS(dev);
309
310	if ((unsigned int)ofs & 0xffffff03) {
311	retval = PCISTS_EINVAL;
312	goto out2;
313	}
314
315	if (PCI_DEV_SLOT(dev) > 15) {
316	retval = PCISTS_MSTABRT;
317	goto out;
318	}
319
320	/* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
321	* we skip them.
322	*/
323	if (dev == HOST_TGT)
324	bus = devfn = 0;
325	else if (bus == 0)
326	devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
327	else
328	devfn = PCI_DEV_DEVFUNC(dev);
329
330	pci_conf = (volatile uint32_t *) (priv->pci_conf \| (devfn << 8) \| ofs);
331
332	IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
333
334	/* Select bus */
335	priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) \| (bus<<16);
336	/* clear old status */
337	priv->regs->sts_cap = (STS_CFGERR \| STS_CFGERRVALID);
338
339	tmp = *pci_conf;
340
341	/* Wait until GRPCI2 signals that CFG access is done, it should be
342	* done instantaneously unless a DMA operation is ongoing...
343	*/
344	while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
345	;
346
347	if (priv->regs->sts_cap & STS_CFGERR) {
348	retval = PCISTS_MSTABRT;
349	} else {
350	/* Bus always little endian (unaffected by byte-swapping) */
351	*val = CPU_swap_u32(tmp);
352	retval = PCISTS_OK;
353	}
354
355	IRQ_GLOBAL_ENABLE(oldLevel);
356
357	out:
358	if (retval != PCISTS_OK)
359	*val = 0xffffffff;
360
361	DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
362	PCI_DEV_EXPAND(dev), ofs, pci_conf, *val, retval);
363
364	out2:
365	return retval;
366	}
367
368	static int grpci2_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
369	{
370	uint32_t v;
371	int retval;
372
373	if (ofs & 1)
374	return PCISTS_EINVAL;
375
376	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
377	val = 0xffff & (v >> (8(ofs & 0x3)));
378
379	return retval;
380	}
381
382	static int grpci2_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
383	{
384	uint32_t v;
385	int retval;
386
387	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
388
389	val = 0xff & (v >> (8(ofs & 3)));
390
391	return retval;
392	}
393
394	static int grpci2_cfg_w32(pci_dev_t dev, int ofs, uint32_t val)
395	{
396	struct grpci2_priv *priv = grpci2priv;
397	volatile uint32_t *pci_conf;
398	uint32_t value, devfn;
399	int retval, bus = PCI_DEV_BUS(dev);
400	IRQ_GLOBAL_PREPARE(oldLevel);
401
402	if ((unsigned int)ofs & 0xffffff03)
403	return PCISTS_EINVAL;
404
405	if (PCI_DEV_SLOT(dev) > 15)
406	return PCISTS_MSTABRT;
407
408	value = CPU_swap_u32(val);
409
410	/* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
411	* we skip them.
412	*/
413	if (dev == HOST_TGT)
414	bus = devfn = 0;
415	else if (bus == 0)
416	devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
417	else
418	devfn = PCI_DEV_DEVFUNC(dev);
419
420	pci_conf = (volatile uint32_t *) (priv->pci_conf \| (devfn << 8) \| ofs);
421
422	IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
423
424	/* Select bus */
425	priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) \| (bus<<16);
426	/* clear old status */
427	priv->regs->sts_cap = (STS_CFGERR \| STS_CFGERRVALID);
428
429	*pci_conf = value;
430
431	/* Wait until GRPCI2 signals that CFG access is done, it should be
432	* done instantaneously unless a DMA operation is ongoing...
433	*/
434	while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
435	;
436
437	if (priv->regs->sts_cap & STS_CFGERR)
438	retval = PCISTS_MSTABRT;
439	else
440	retval = PCISTS_OK;
441
442	IRQ_GLOBAL_ENABLE(oldLevel);
443
444	DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
445	PCI_DEV_EXPAND(dev), ofs, pci_conf, value, retval);
446
447	return retval;
448	}
449
450	static int grpci2_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
451	{
452	uint32_t v;
453	int retval;
454
455	if (ofs & 1)
456	return PCISTS_EINVAL;
457
458	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
459	if (retval != PCISTS_OK)
460	return retval;
461
462	v = (v & ~(0xffff << (8(ofs&3)))) \| ((0xffff&val) << (8(ofs&3)));
463
464	return grpci2_cfg_w32(dev, ofs & ~0x3, v);
465	}
466
467	static int grpci2_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
468	{
469	uint32_t v;
470	int retval;
471
472	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
473	if (retval != PCISTS_OK)
474	return retval;
475
476	v = (v & ~(0xff << (8(ofs&3)))) \| ((0xff&val) << (8(ofs&3)));
477
478	return grpci2_cfg_w32(dev, ofs & ~0x3, v);
479	}
480
481	/* Return the assigned system IRQ number that corresponds to the PCI
482	* "Interrupt Pin" information from configuration space.
483	*
484	* The IRQ information is stored in the grpci2_pci_irq_table configurable
485	* by the user.
486	*
487	* Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
488	* 0xff if not assigned.
489	*/
490	static uint8_t grpci2_bus0_irq_map(pci_dev_t dev, int irq_pin)
491	{
492	uint8_t sysIrqNr = 0; /* not assigned */
493	int irq_group;
494
495	if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
496	/* Use default IRQ decoding on PCI BUS0 according slot numbering */
497	irq_group = PCI_DEV_SLOT(dev) & 0x3;
498	irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
499	/* Valid PCI "Interrupt Pin" number */
500	sysIrqNr = grpci2_pci_irq_table[irq_pin];
501	}
502	return sysIrqNr;
503	}
504
505	static int grpci2_translate(uint32_t *address, int type, int dir)
506	{
507	uint32_t adr, start, end;
508	struct grpci2_priv *priv = grpci2priv;
509	int i;
510
511	if (type == 1) {
512	/* I/O */
513	if (dir != 0) {
514	/* The PCI bus can not access the CPU bus from I/O
515	* because GRPCI2 core does not support I/O BARs
516	*/
517	return -1;
518	}
519
520	/* We have got a PCI IO BAR address that the CPU want to access.
521	* Check that it is within the PCI I/O window, I/O adresses
522	* are NOT mapped 1:1 with GRPCI2 driver... translation needed.
523	*/
524	adr = (uint32_t )address;
525	if (adr < 0x100 \|\| adr > 0x10000)
526	return -1;
527	*address = adr + priv->pci_io;
528	} else {
529	/* MEMIO and MEM.
530	* Memory space is mapped 1:1 so no translation is needed.
531	* Check that address is within accessible windows.
532	*/
533	adr = (uint32_t )address;
534	if (dir == 0) {
535	/* PCI BAR to AMBA-CPU address.. check that it is
536	* located within GRPCI2 PCI Memory Window
537	* adr = PCI address.
538	*/
539	if (adr < priv->pci_area \|\| adr >= priv->pci_area_end)
540	return -1;
541	} else {
542	/* We have a CPU address and want to get access to it
543	* from PCI space, typically when doing DMA into CPU
544	* RAM. The GRPCI2 core may have multiple target BARs
545	* that PCI masters can access, the BARs are user
546	* configurable in the following ways:
547	* BAR_SIZE, PCI_BAR Address and MAPPING (AMBA ADR)
548	*
549	* The below code tries to find a BAR for which the
550	* AMBA bar may have been mapped onto, and translate
551	* the AMBA-CPU address into a PCI address using the
552	* given mapping.
553	*
554	* adr = AMBA address.
555	*/
556	for(i=0; i<6; i++) {
557	start = priv->barcfg[i].ahbadr;
558	end = priv->barcfg[i].ahbadr +
559	priv->barcfg[i].barsize;
560	if (adr >= start && adr < end) {
561	/* BAR match: Translate address */
562	*address = (adr - start) +
563	priv->barcfg[i].pciadr;
564	return 0;
565	}
566	}
567	return -1;
568	}
569	}
570
571	return 0;
572	}
573
574	extern struct pci_memreg_ops pci_memreg_sparc_le_ops;
575	extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
576
577	/* GRPCI2 PCI access routines, default to Little-endian PCI Bus */
578	struct pci_access_drv grpci2_access_drv = {
579	.cfg =
580	{
581	grpci2_cfg_r8,
582	grpci2_cfg_r16,
583	grpci2_cfg_r32,
584	grpci2_cfg_w8,
585	grpci2_cfg_w16,
586	grpci2_cfg_w32,
587	},
588	.io =
589	{
590	_ld8,
591	_ld_le16,
592	_ld_le32,
593	_st8,
594	_st_le16,
595	_st_le32,
596	},
597	.memreg = &pci_memreg_sparc_le_ops,
598	.translate = grpci2_translate,
599	};
600
601	struct pci_io_ops grpci2_io_ops_be =
602	{
603	_ld8,
604	_ld_be16,
605	_ld_be32,
606	_st8,
607	_st_be16,
608	_st_be32,
609	};
610
611	/* PCI Error Interrupt handler, called when there may be a PCI Target/Master
612	* Abort.
613	*/
614	void grpci2_err_isr(void *arg)
615	{
616	struct grpci2_priv *priv = arg;
617	unsigned int sts = priv->regs->sts_cap;
618
619	if (sts & (STS_IMSTABRT \| STS_ITGTABRT \| STS_IPARERR \| STS_ISYSERR \| STS_ITIMEOUT)) {
620	/* A PCI error IRQ ... Error handler unimplemented
621	* add your code here...
622	*/
623	if (sts & STS_IMSTABRT) {
624	printk("GRPCI2: unhandled Master Abort IRQ\n");
625	}
626	if (sts & STS_ITGTABRT) {
627	printk("GRPCI2: unhandled Target Abort IRQ\n");
628	}
629	if (sts & STS_IPARERR) {
630	printk("GRPCI2: unhandled Parity Error IRQ\n");
631	}
632	if (sts & STS_ISYSERR) {
633	printk("GRPCI2: unhandled System Error IRQ\n");
634	}
635	if (sts & STS_ITIMEOUT) {
636	printk("GRPCI2: unhandled PCI target access timeout IRQ\n");
637	}
638	}
639	}
640
641	static int grpci2_hw_init(struct grpci2_priv *priv)
642	{
643	struct grpci2_regs *regs = priv->regs;
644	int i;
645	uint8_t capptr;
646	uint32_t data, io_map, ahbadr, pciadr, size;
647	pci_dev_t host = HOST_TGT;
648	struct grpci2_pcibar_cfg *barcfg = priv->barcfg;
649
650	/* Reset any earlier setup */
651	regs->ctrl = 0;
652	regs->sts_cap = ~0; /* Clear Status */
653	regs->dma_ctrl = 0;
654	regs->dma_bdbase = 0;
655
656	/* Translate I/O accesses 1:1, (will not work for PCI 2.3) */
657	regs->io_map = priv->pci_io & 0xffff0000;
658
659	/* set 1:1 mapping between AHB -> PCI memory space, for all Masters
660	* Each AHB master has it's own mapping registers. Max 16 AHB masters.
661	*/
662	for (i=0; i<16; i++)
663	regs->ahbmst_map[i] = priv->pci_area;
664
665	/* Get the GRPCI2 Host PCI ID */
666	grpci2_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
667
668	/* Get address to first (always defined) capability structure */
669	grpci2_cfg_r8(host, PCIR_CAP_PTR, &capptr);
670	if (capptr == 0)
671	return -1;
672
673	/* Limit the prefetch for GRPCI2 version 0. */
674	if (priv->ver == 0)
675	grpci2_cfg_w32(host, capptr+CAP9_AHBPREF_OFS, 0);
676
677	/* Enable/Disable Byte twisting */
678	grpci2_cfg_r32(host, capptr+CAP9_IOMAP_OFS, &io_map);
679	io_map = (io_map & ~0x1) \| (priv->bt_enabled ? 1 : 0);
680	grpci2_cfg_w32(host, capptr+CAP9_IOMAP_OFS, io_map);
681
682	/* Setup the Host's PCI Target BARs for others to access (DMA) */
683	for (i=0; i<6; i++) {
684	/* Make sure address is properly aligned */
685	size = ~(barcfg[i].barsize-1);
686	barcfg[i].pciadr &= size;
687	barcfg[i].ahbadr &= size;
688
689	pciadr = barcfg[i].pciadr;
690	ahbadr = barcfg[i].ahbadr;
691	size \|= PCIM_BAR_MEM_PREFETCH;
692
693	grpci2_cfg_w32(host, capptr+CAP9_BARSIZE_OFS+i*4, size);
694	grpci2_cfg_w32(host, capptr+CAP9_BAR_OFS+i*4, ahbadr);
695	grpci2_cfg_w32(host, PCIR_BAR(0)+i*4, pciadr);
696	}
697
698	/* set as bus master and enable pci memory responses */
699	grpci2_cfg_r32(host, PCIR_COMMAND, &data);
700	data \|= (PCIM_CMD_MEMEN \| PCIM_CMD_BUSMASTEREN);
701	grpci2_cfg_w32(host, PCIR_COMMAND, data);
702
703	/* set latency timer */
704	grpci2_cfg_r32(host, PCIR_CACHELNSZ, &data);
705	data &= ~0xff00;
706	data \|= ((priv->latency_timer & 0xff) << 8);
707	grpci2_cfg_w32(host, PCIR_CACHELNSZ, data);
708
709	/* Enable Error respone (CPU-TRAP) on illegal memory access */
710	regs->ctrl = CTRL_ER \| CTRL_PE;
711
712	/* Successful */
713	return 0;
714	}
715
716	/* Initializes the GRPCI2 core and driver, must be called before calling
717	* init_pci()
718	*
719	* Return values
720	* 0 Successful initalization
721	* -1 Error during initialization, for example "PCI core not found".
722	* -2 Error PCI controller not HOST (targets not supported)
723	* -3 Error due to GRPCI2 hardware initialization
724	*/
725	static int grpci2_init(struct grpci2_priv *priv)
726	{
727	struct ambapp_apb_info *apb;
728	struct ambapp_ahb_info *ahb;
729	int pin, i, j;
730	union drvmgr_key_value *value;
731	char keyname[6];
732	struct amba_dev_info *ainfo = priv->dev->businfo;
733	struct grpci2_pcibar_cfg *barcfg;
734	unsigned int size;
735
736	/* Find PCI core from Plug&Play information */
737	apb = ainfo->info.apb_slv;
738	ahb = ainfo->info.ahb_slv;
739
740	/* Found PCI core, init private structure */
741	priv->irq = apb->irq;
742	priv->ver = apb->ver;
743	priv->regs = (struct grpci2_regs *)apb->start;
744	priv->bt_enabled = DEFAULT_BT_ENABLED;
745	priv->irq_mode = (priv->regs->sts_cap & STS_IRQMODE) >> STS_IRQMODE_BIT;
746	priv->latency_timer = DEFAULT_LATENCY_TIMER;
747
748	/* Calculate the PCI windows
749	* AMBA->PCI Window: AHB SLAVE AREA0
750	* AMBA->PCI I/O cycles Window: AHB SLAVE AREA1 Lower half
751	* AMBA->PCI Configuration cycles Window: AHB SLAVE AREA1 Upper half
752	*/
753	priv->pci_area = ahb->start[0];
754	priv->pci_area_end = ahb->start[0] + ahb->mask[0];
755	priv->pci_io = ahb->start[1];
756	priv->pci_conf = ahb->start[1] + 0x10000;
757	priv->pci_conf_end = priv->pci_conf + 0x10000;
758
759	/* On systems where PCI I/O area and configuration area is apart of the
760	* "PCI Window" the PCI Window stops at the start of the PCI I/O area
761	*/
762	if ((priv->pci_io > priv->pci_area) &&
763	(priv->pci_io < (priv->pci_area_end-1))) {
764	priv->pci_area_end = priv->pci_io;
765	}
766
767	/* Init PCI interrupt assignment table to all use the interrupt routed
768	* through the GRPCI2 core.
769	*/
770	strcpy(keyname, "INTX#");
771	for (pin=1; pin<5; pin++) {
772	if (grpci2_pci_irq_table[pin-1] == 0xff) {
773	if (priv->irq_mode < 2) {
774	/* PCI Interrupts are shared */
775	grpci2_pci_irq_table[pin-1] = priv->irq;
776	} else {
777	/* Unique IRQ per PCI INT Pin */
778	grpci2_pci_irq_table[pin-1] = priv->irq + pin-1;
779	}
780
781	/* User may override Both hardcoded IRQ setup and Plug & Play IRQ */
782	keyname[3] = 'A' + (pin-1);
783	value = drvmgr_dev_key_get(priv->dev, keyname, DRVMGR_KT_INT);
784	if (value)
785	grpci2_pci_irq_table[pin-1] = value->i;
786	}
787
788	/* Remember which IRQs are enabled */
789	if (grpci2_pci_irq_table[pin-1] != 0)
790	priv->irq_mask \|= 1 << (pin-1);
791	}
792
793	/* User may override DEFAULT_BT_ENABLED to enable/disable byte twisting */
794	value = drvmgr_dev_key_get(priv->dev, "byteTwisting", DRVMGR_KT_INT);
795	if (value)
796	priv->bt_enabled = value->i;
797
798	/* Let user Configure the 6 target BARs */
799	value = drvmgr_dev_key_get(priv->dev, "tgtBarCfg", DRVMGR_KT_POINTER);
800	if (value)
801	priv->barcfg = value->ptr;
802	else
803	priv->barcfg = grpci2_default_bar_mapping;
804
805	/* User may override DEFAULT_LATENCY_TIMER */
806	value = drvmgr_dev_key_get(priv->dev, "latencyTimer", DRVMGR_KT_INT);
807	if (value)
808	priv->latency_timer = value->i;
809
810	/* This driver only support HOST systems, we check that it can act as a
811	* PCI Master and that it is in the Host slot. */
812	if ((priv->regs->sts_cap&STS_HOST) \|\| !(priv->regs->sts_cap&STS_MST))
813	return -2; /* Target not supported */
814
815	/* Init the PCI Core */
816	if (grpci2_hw_init(priv))
817	return -3;
818
819	/* Down streams translation table */
820	priv->maps_down[0].name = "AMBA -> PCI MEM Window";
821	priv->maps_down[0].size = priv->pci_area_end - priv->pci_area;
822	priv->maps_down[0].from_adr = (void *)priv->pci_area;
823	priv->maps_down[0].to_adr = (void *)priv->pci_area;
824	/* End table */
825	priv->maps_down[1].size = 0;
826
827	/* Up streams translation table */
828	/* Setup the Host's PCI Target BARs for others to access (DMA) */
829	barcfg = priv->barcfg;
830	for (i=0,j=0; i<6; i++) {
831	size = barcfg[i].barsize;
832	if (size == 0)
833	continue;
834
835	/* Make sure address is properly aligned */
836	priv->maps_up[j].name = "Target BAR[I] -> AMBA";
837	priv->maps_up[j].size = size;
838	priv->maps_up[j].from_adr = (void *)
839	(barcfg[i].pciadr & ~(size - 1));
840	priv->maps_up[j].to_adr = (void *)
841	(barcfg[i].ahbadr & ~(size - 1));
842	j++;
843	}
844
845	/* End table */
846	priv->maps_up[j].size = 0;
847
848	return 0;
849	}
850
851	/* Called when a core is found with the AMBA device and vendor ID
852	* given in grpci2_ids[]. IRQ, Console does not work here
853	*/
854	int grpci2_init1(struct drvmgr_dev *dev)
855	{
856	int status;
857	struct grpci2_priv *priv;
858	struct pci_auto_setup grpci2_auto_cfg;
859
860	DBG("GRPCI2[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
861
862	if (grpci2priv) {
863	DBG("Driver only supports one PCI core\n");
864	return DRVMGR_FAIL;
865	}
866
867	if ((strcmp(dev->parent->dev->drv->name, "AMBAPP_GRLIB_DRV") != 0) &&
868	(strcmp(dev->parent->dev->drv->name, "AMBAPP_LEON2_DRV") != 0)) {
869	/* We only support GRPCI2 driver on local bus */
870	return DRVMGR_FAIL;
871	}
872
873	priv = dev->priv;
874	if (!priv)
875	return DRVMGR_NOMEM;
876
877	priv->dev = dev;
878	grpci2priv = priv;
879
880	/* Initialize GRPCI2 Hardware */
881	status = grpci2_init(priv);
882	if (status) {
883	printf("Failed to initialize grpci2 driver %d\n", status);
884	return -1;
885	}
886
887	/* Register the PCI core at the PCI layers */
888
889	if (priv->bt_enabled == 0) {
890	/* Host is Big-Endian */
891	pci_endian = PCI_BIG_ENDIAN;
892
893	memcpy(&grpci2_access_drv.io, &grpci2_io_ops_be,
894	sizeof(grpci2_io_ops_be));
895	grpci2_access_drv.memreg = &pci_memreg_sparc_be_ops;
896	}
897
898	if (pci_access_drv_register(&grpci2_access_drv)) {
899	/* Access routines registration failed */
900	return DRVMGR_FAIL;
901	}
902
903	/* Prepare memory MAP */
904	grpci2_auto_cfg.options = 0;
905	grpci2_auto_cfg.mem_start = 0;
906	grpci2_auto_cfg.mem_size = 0;
907	grpci2_auto_cfg.memio_start = priv->pci_area;
908	grpci2_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area;
909	grpci2_auto_cfg.io_start = 0x100; /* avoid PCI address 0 */
910	grpci2_auto_cfg.io_size = 0x10000 - 0x100; /* lower 64kB I/O 16 */
911	grpci2_auto_cfg.irq_map = grpci2_bus0_irq_map;
912	grpci2_auto_cfg.irq_route = NULL; /* use standard routing */
913	pci_config_register(&grpci2_auto_cfg);
914
915	if (pci_config_init()) {
916	/* PCI configuration failed */
917	return DRVMGR_FAIL;
918	}
919
920	/* Initialize/Register Driver Manager PCI Bus */
921	priv->config.maps_down = &priv->maps_down[0];
922	priv->config.maps_up = &priv->maps_up[0];
923	return pcibus_register(dev, &priv->config);
924	}
925
926	int grpci2_init3(struct drvmgr_dev *dev)
927	{
928	struct grpci2_priv *priv = dev->priv;
929
930	/* Install and Enable PCI Error interrupt handler */
931	drvmgr_interrupt_register(dev, 0, "grpci2", grpci2_err_isr, priv);
932
933	/* Unmask Error IRQ and all PCI interrupts at PCI Core. For this to be
934	* safe every PCI board have to be resetted (no IRQ generation) before
935	* Global IRQs are enabled (Init is reached or similar)
936	*/
937	priv->regs->ctrl \|= (CTRL_EI \| priv->irq_mask);
938
939	return DRVMGR_OK;
940	}

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