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source: rtems/c/src/lib/libbsp/sparc/shared/pci/grpci2.c @ ecbd577

4.115

Last change on this file since ecbd577 was 175b9a64, checked in by Daniel Hellstrom <daniel@…>, on 04/24/13 at 15:36:44
GRPCI2: work-around for rev0 bug by limiting prefetching
Property mode set to `100644`
File size: 23.8 KB

Line
1	/* GRLIB GRPCI2 PCI HOST driver.
2	*
3	* COPYRIGHT (c) 2011
4	* Cobham Gaisler AB.
5	*
6	* The license and distribution terms for this file may be
7	* found in found in the file LICENSE in this distribution or at
8	* http://www.rtems.com/license/LICENSE.
9	*/
10
11	/* Configures the GRPCI2 core and initialize,
12	* - the PCI Library (pci.c)
13	* - the general part of the PCI Bus driver (pci_bus.c)
14	*
15	* System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
16	* default taken from Plug and Play, but may be overridden by the
17	* driver resources INTA#..INTD#. GRPCI2 handles differently depending
18	* on the design (4 different ways).
19	*
20	* GRPCI2 IRQ implementation notes
21	* -------------------------------
22	* Since the Driver Manager pci_bus layer implements IRQ by calling
23	* pci_interrupt_* which translates into BSP_shared_interrupt_*, and the
24	* root-bus also relies on BSP_shared_interrupt_*, it is safe for the GRPCI2
25	* driver to use the drvmgr_interrupt_* routines since they will be
26	* accessing the same routines in the end. Otherwise the GRPCI2 driver must
27	* have used the pci_interrupt_* routines.
28	*/
29
30	#include <stdlib.h>
31	#include <stdio.h>
32	#include <string.h>
33	#include <rtems/bspIo.h>
34	#include <libcpu/byteorder.h>
35	#include <libcpu/access.h>
36	#include <pci.h>
37	#include <pci/cfg.h>
38
39	#include <drvmgr/drvmgr.h>
40	#include <drvmgr/ambapp_bus.h>
41	#include <ambapp.h>
42	#include <drvmgr/pci_bus.h>
43	#include <grpci2.h>
44
45	#ifndef IRQ_GLOBAL_PREPARE
46	#define IRQ_GLOBAL_PREPARE(level) rtems_interrupt_level level
47	#endif
48
49	#ifndef IRQ_GLOBAL_DISABLE
50	#define IRQ_GLOBAL_DISABLE(level) rtems_interrupt_disable(level)
51	#endif
52
53	#ifndef IRQ_GLOBAL_ENABLE
54	#define IRQ_GLOBAL_ENABLE(level) rtems_interrupt_enable(level)
55	#endif
56
57	/* If defined to 1 - byte twisting is enabled by default */
58	#define DEFAULT_BT_ENABLED 0
59
60	/* Interrupt assignment. Set to other value than 0xff in order to
61	* override defaults and plug&play information
62	*/
63	#ifndef GRPCI2_INTA_SYSIRQ
64	#define GRPCI2_INTA_SYSIRQ 0xff
65	#endif
66	#ifndef GRPCI2_INTB_SYSIRQ
67	#define GRPCI2_INTB_SYSIRQ 0xff
68	#endif
69	#ifndef GRPCI2_INTC_SYSIRQ
70	#define GRPCI2_INTC_SYSIRQ 0xff
71	#endif
72	#ifndef GRPCI2_INTD_SYSIRQ
73	#define GRPCI2_INTD_SYSIRQ 0xff
74	#endif
75
76	/#define DEBUG 1/
77
78	#ifdef DEBUG
79	#define DBG(x...) printk(x)
80	#else
81	#define DBG(x...)
82	#endif
83
84	#define PCI_INVALID_VENDORDEVICEID 0xffffffff
85	#define PCI_MULTI_FUNCTION 0x80
86
87	/*
88	* GRPCI2 APB Register MAP
89	*/
90	struct grpci2_regs {
91	volatile unsigned int ctrl; /* 0x00 */
92	volatile unsigned int sts_cap; /* 0x04 */
93	int res1; /* 0x08 */
94	volatile unsigned int io_map; /* 0x0C */
95	volatile unsigned int dma_ctrl; /* 0x10 */
96	volatile unsigned int dma_bdbase; /* 0x14 */
97	int res2[2]; /* 0x18 */
98	volatile unsigned int bars[6]; /* 0x20 */
99	int res3[2]; /* 0x38 */
100	volatile unsigned int ahbmst_map[16]; /* 0x40 */
101	};
102
103	#define CTRL_BUS_BIT 16
104
105	#define CTRL_SI (1<<27)
106	#define CTRL_PE (1<<26)
107	#define CTRL_EI (1<<25)
108	#define CTRL_ER (1<<24)
109	#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
110	#define CTRL_HOSTINT 0xf
111
112	#define STS_HOST_BIT 31
113	#define STS_MST_BIT 30
114	#define STS_TAR_BIT 29
115	#define STS_DMA_BIT 28
116	#define STS_DI_BIT 27
117	#define STS_HI_BIT 26
118	#define STS_IRQMODE_BIT 24
119	#define STS_TRACE_BIT 23
120	#define STS_CFGERRVALID_BIT 20
121	#define STS_CFGERR_BIT 19
122	#define STS_INTTYPE_BIT 12
123	#define STS_INTSTS_BIT 8
124	#define STS_FDEPTH_BIT 2
125	#define STS_FNUM_BIT 0
126
127	#define STS_HOST (1<<STS_HOST_BIT)
128	#define STS_MST (1<<STS_MST_BIT)
129	#define STS_TAR (1<<STS_TAR_BIT)
130	#define STS_DMA (1<<STS_DMA_BIT)
131	#define STS_DI (1<<STS_DI_BIT)
132	#define STS_HI (1<<STS_HI_BIT)
133	#define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
134	#define STS_TRACE (1<<STS_TRACE_BIT)
135	#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
136	#define STS_CFGERR (1<<STS_CFGERR_BIT)
137	#define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT)
138	#define STS_INTSTS (0xf<<STS_INTSTS_BIT)
139	#define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
140	#define STS_FNUM (0x3<<STS_FNUM_BIT)
141
142	#define STS_ISYSERR (1<<17)
143	#define STS_IDMA (1<<16)
144	#define STS_IDMAERR (1<<15)
145	#define STS_IMSTABRT (1<<14)
146	#define STS_ITGTABRT (1<<13)
147	#define STS_IPARERR (1<<12)
148
149	struct grpci2_bd_chan {
150	volatile unsigned int ctrl; /* 0x00 DMA Control */
151	volatile unsigned int nchan; /* 0x04 Next DMA Channel Address */
152	volatile unsigned int nbd; /* 0x08 Next Data Descriptor in channel */
153	volatile unsigned int res; /* 0x0C Reserved */
154	};
155
156	#define BD_CHAN_EN 0x80000000
157	#define BD_CHAN_TYPE 0x00300000
158	#define BD_CHAN_BDCNT 0x0000ffff
159	#define BD_CHAN_EN_BIT 31
160	#define BD_CHAN_TYPE_BIT 20
161	#define BD_CHAN_BDCNT_BIT 0
162
163	struct grpci2_bd_data {
164	volatile unsigned int ctrl; /* 0x00 DMA Data Control */
165	volatile unsigned int pci_adr; /* 0x04 PCI Start Address */
166	volatile unsigned int ahb_adr; /* 0x08 AHB Start address */
167	volatile unsigned int next; /* 0x0C Next Data Descriptor in channel */
168	};
169
170	#define BD_DATA_EN 0x80000000
171	#define BD_DATA_IE 0x40000000
172	#define BD_DATA_DR 0x20000000
173	#define BD_DATA_TYPE 0x00300000
174	#define BD_DATA_ER 0x00080000
175	#define BD_DATA_LEN 0x0000ffff
176	#define BD_DATA_EN_BIT 31
177	#define BD_DATA_IE_BIT 30
178	#define BD_DATA_DR_BIT 29
179	#define BD_DATA_TYPE_BIT 20
180	#define BD_DATA_ER_BIT 19
181	#define BD_DATA_LEN_BIT 0
182
183	/* GRPCI2 Capability */
184	struct grpci2_cap_first {
185	unsigned int ctrl;
186	unsigned int pci2ahb_map[6];
187	unsigned int ext2ahb_map;
188	unsigned int io_map;
189	unsigned int pcibar_size[6];
190	unsigned int ahb_pref;
191	};
192	#define CAP9_CTRL_OFS 0
193	#define CAP9_BAR_OFS 0x4
194	#define CAP9_IOMAP_OFS 0x20
195	#define CAP9_BARSIZE_OFS 0x24
196	#define CAP9_AHBPREF_OFS 0x3C
197
198	struct grpci2_priv *grpci2priv = NULL;
199
200	/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
201	* to a system interrupt number.
202	*/
203	unsigned char grpci2_pci_irq_table[4] =
204	{
205	/* INTA# */ GRPCI2_INTA_SYSIRQ,
206	/* INTB# */ GRPCI2_INTB_SYSIRQ,
207	/* INTC# */ GRPCI2_INTC_SYSIRQ,
208	/* INTD# */ GRPCI2_INTD_SYSIRQ
209	};
210
211	/* Start of workspace/dynamical area */
212	extern unsigned int _end;
213	#define DMA_START ((unsigned int) &_end)
214
215	/* Default BAR mapping, set BAR0 256MB 1:1 mapped base of CPU RAM */
216	struct grpci2_pcibar_cfg grpci2_default_bar_mapping[6] = {
217	/* BAR0 */ {DMA_START, DMA_START, 0x10000000},
218	/* BAR1 */ {0, 0, 0},
219	/* BAR2 */ {0, 0, 0},
220	/* BAR3 */ {0, 0, 0},
221	/* BAR4 */ {0, 0, 0},
222	/* BAR5 */ {0, 0, 0},
223	};
224
225	/* Driver private data struture */
226	struct grpci2_priv {
227	struct drvmgr_dev *dev;
228	struct grpci2_regs *regs;
229	unsigned char ver;
230	char irq;
231	char irq_mode; /* IRQ Mode from CAPSTS REG */
232	char bt_enabled;
233	unsigned int irq_mask;
234
235	struct grpci2_pcibar_cfg *barcfg;
236
237	unsigned int pci_area;
238	unsigned int pci_area_end;
239	unsigned int pci_io;
240	unsigned int pci_conf;
241	unsigned int pci_conf_end;
242
243	uint32_t devVend; /* Host PCI Device/Vendor ID */
244
245	struct drvmgr_map_entry maps_up[7];
246	struct drvmgr_map_entry maps_down[2];
247	struct pcibus_config config;
248	};
249
250	int grpci2_init1(struct drvmgr_dev *dev);
251	int grpci2_init3(struct drvmgr_dev *dev);
252
253	/* GRPCI2 DRIVER */
254
255	struct drvmgr_drv_ops grpci2_ops =
256	{
257	.init = {grpci2_init1, NULL, grpci2_init3, NULL},
258	.remove = NULL,
259	.info = NULL
260	};
261
262	struct amba_dev_id grpci2_ids[] =
263	{
264	{VENDOR_GAISLER, GAISLER_GRPCI2},
265	{0, 0} /* Mark end of table */
266	};
267
268	struct amba_drv_info grpci2_info =
269	{
270	{
271	DRVMGR_OBJ_DRV, /* Driver */
272	NULL, /* Next driver */
273	NULL, /* Device list */
274	DRIVER_AMBAPP_GAISLER_GRPCI2_ID,/* Driver ID */
275	"GRPCI2_DRV", /* Driver Name */
276	DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
277	&grpci2_ops,
278	NULL, /* Funcs */
279	0, /* No devices yet */
280	sizeof(struct grpci2_priv), /* Make drvmgr alloc private */
281	},
282	&grpci2_ids[0]
283	};
284
285	void grpci2_register_drv(void)
286	{
287	DBG("Registering GRPCI2 driver\n");
288	drvmgr_drv_register(&grpci2_info.general);
289	}
290
291	int grpci2_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val)
292	{
293	struct grpci2_priv *priv = grpci2priv;
294	volatile uint32_t *pci_conf;
295	unsigned int tmp, devfn;
296	IRQ_GLOBAL_PREPARE(oldLevel);
297	int retval, bus = PCI_DEV_BUS(dev);
298
299	if ((unsigned int)ofs & 0xffffff03) {
300	retval = PCISTS_EINVAL;
301	goto out2;
302	}
303
304	if (PCI_DEV_SLOT(dev) > 15) {
305	retval = PCISTS_MSTABRT;
306	goto out;
307	}
308
309	/* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
310	* we skip them.
311	*/
312	if (bus == 0 && PCI_DEV_SLOT(dev) != 0)
313	devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
314	else
315	devfn = PCI_DEV_DEVFUNC(dev);
316
317	pci_conf = (volatile uint32_t *) (priv->pci_conf \| (devfn << 8) \| ofs);
318
319	IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
320
321	/* Select bus */
322	priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) \| (bus<<16);
323	/* clear old status */
324	priv->regs->sts_cap = (STS_CFGERR \| STS_CFGERRVALID);
325
326	tmp = *pci_conf;
327
328	/* Wait until GRPCI2 signals that CFG access is done, it should be
329	* done instantaneously unless a DMA operation is ongoing...
330	*/
331	while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
332	;
333
334	if (priv->regs->sts_cap & STS_CFGERR) {
335	retval = PCISTS_MSTABRT;
336	} else {
337	/* Bus always little endian (unaffected by byte-swapping) */
338	*val = CPU_swap_u32(tmp);
339	retval = PCISTS_OK;
340	}
341
342	IRQ_GLOBAL_ENABLE(oldLevel);
343
344	out:
345	if (retval != PCISTS_OK)
346	*val = 0xffffffff;
347
348	DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
349	PCI_DEV_EXPAND(dev), ofs, pci_conf, *val, retval);
350
351	out2:
352	return retval;
353	}
354
355	int grpci2_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
356	{
357	uint32_t v;
358	int retval;
359
360	if (ofs & 1)
361	return PCISTS_EINVAL;
362
363	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
364	val = 0xffff & (v >> (8(ofs & 0x3)));
365
366	return retval;
367	}
368
369	int grpci2_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
370	{
371	uint32_t v;
372	int retval;
373
374	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
375
376	val = 0xff & (v >> (8(ofs & 3)));
377
378	return retval;
379	}
380
381	int grpci2_cfg_w32(pci_dev_t dev, int ofs, uint32_t val)
382	{
383	struct grpci2_priv *priv = grpci2priv;
384	volatile uint32_t *pci_conf;
385	uint32_t value, devfn;
386	int retval, bus = PCI_DEV_BUS(dev);
387	IRQ_GLOBAL_PREPARE(oldLevel);
388
389	if ((unsigned int)ofs & 0xffffff03)
390	return PCISTS_EINVAL;
391
392	if (PCI_DEV_SLOT(dev) > 15)
393	return PCISTS_MSTABRT;
394
395	value = CPU_swap_u32(val);
396
397	/* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
398	* we skip them.
399	*/
400	if (bus == 0 && PCI_DEV_SLOT(dev) != 0)
401	devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
402	else
403	devfn = PCI_DEV_DEVFUNC(dev);
404
405	pci_conf = (volatile uint32_t *) (priv->pci_conf \| (devfn << 8) \| ofs);
406
407	IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
408
409	/* Select bus */
410	priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) \| (bus<<16);
411	/* clear old status */
412	priv->regs->sts_cap = (STS_CFGERR \| STS_CFGERRVALID);
413
414	*pci_conf = value;
415
416	/* Wait until GRPCI2 signals that CFG access is done, it should be
417	* done instantaneously unless a DMA operation is ongoing...
418	*/
419	while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
420	;
421
422	if (priv->regs->sts_cap & STS_CFGERR)
423	retval = PCISTS_MSTABRT;
424	else
425	retval = PCISTS_OK;
426
427	IRQ_GLOBAL_ENABLE(oldLevel);
428
429	DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
430	PCI_DEV_EXPAND(dev), ofs, pci_conf, value, retval);
431
432	return retval;
433	}
434
435	int grpci2_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
436	{
437	uint32_t v;
438	int retval;
439
440	if (ofs & 1)
441	return PCISTS_EINVAL;
442
443	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
444	if (retval != PCISTS_OK)
445	return retval;
446
447	v = (v & ~(0xffff << (8(ofs&3)))) \| ((0xffff&val) << (8(ofs&3)));
448
449	return grpci2_cfg_w32(dev, ofs & ~0x3, v);
450	}
451
452	int grpci2_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
453	{
454	uint32_t v;
455	int retval;
456
457	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
458	if (retval != PCISTS_OK)
459	return retval;
460
461	v = (v & ~(0xff << (8(ofs&3)))) \| ((0xff&val) << (8(ofs&3)));
462
463	return grpci2_cfg_w32(dev, ofs & ~0x3, v);
464	}
465
466	/* Return the assigned system IRQ number that corresponds to the PCI
467	* "Interrupt Pin" information from configuration space.
468	*
469	* The IRQ information is stored in the grpci2_pci_irq_table configurable
470	* by the user.
471	*
472	* Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
473	* 0xff if not assigned.
474	*/
475	uint8_t grpci2_bus0_irq_map(pci_dev_t dev, int irq_pin)
476	{
477	uint8_t sysIrqNr = 0; /* not assigned */
478	int irq_group;
479
480	if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
481	/* Use default IRQ decoding on PCI BUS0 according slot numbering */
482	irq_group = PCI_DEV_SLOT(dev) & 0x3;
483	irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
484	/* Valid PCI "Interrupt Pin" number */
485	sysIrqNr = grpci2_pci_irq_table[irq_pin];
486	}
487	return sysIrqNr;
488	}
489
490	int grpci2_translate(uint32_t *address, int type, int dir)
491	{
492	uint32_t adr, start, end;
493	struct grpci2_priv *priv = grpci2priv;
494	int i;
495
496	if (type == 1) {
497	/* I/O */
498	if (dir != 0) {
499	/* The PCI bus can not access the CPU bus from I/O
500	* because GRPCI2 core does not support I/O BARs
501	*/
502	return -1;
503	}
504
505	/* We have got a PCI IO BAR address that the CPU want to access.
506	* Check that it is within the PCI I/O window, I/O adresses
507	* are NOT mapped 1:1 with GRPCI2 driver... translation needed.
508	*/
509	adr = (uint32_t )address;
510	if (adr < 0x100 \|\| adr > 0x10000)
511	return -1;
512	*address = adr + priv->pci_io;
513	} else {
514	/* MEMIO and MEM.
515	* Memory space is mapped 1:1 so no translation is needed.
516	* Check that address is within accessible windows.
517	*/
518	adr = (uint32_t )address;
519	if (dir == 0) {
520	/* PCI BAR to AMBA-CPU address.. check that it is
521	* located within GRPCI2 PCI Memory Window
522	* adr = PCI address.
523	*/
524	if (adr < priv->pci_area \|\| adr >= priv->pci_area_end)
525	return -1;
526	} else {
527	/* We have a CPU address and want to get access to it
528	* from PCI space, typically when doing DMA into CPU
529	* RAM. The GRPCI2 core may have multiple target BARs
530	* that PCI masters can access, the BARs are user
531	* configurable in the following ways:
532	* BAR_SIZE, PCI_BAR Address and MAPPING (AMBA ADR)
533	*
534	* The below code tries to find a BAR for which the
535	* AMBA bar may have been mapped onto, and translate
536	* the AMBA-CPU address into a PCI address using the
537	* given mapping.
538	*
539	* adr = AMBA address.
540	*/
541	for(i=0; i<6; i++) {
542	start = priv->barcfg[i].ahbadr;
543	end = priv->barcfg[i].ahbadr +
544	priv->barcfg[i].barsize;
545	if (adr >= start && adr < end) {
546	/* BAR match: Translate address */
547	*address = (adr - start) +
548	priv->barcfg[i].pciadr;
549	return 0;
550	}
551	}
552	return -1;
553	}
554	}
555
556	return 0;
557	}
558
559	extern struct pci_memreg_ops pci_memreg_sparc_le_ops;
560	extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
561
562	/* GRPCI2 PCI access routines, default to Little-endian PCI Bus */
563	struct pci_access_drv grpci2_access_drv = {
564	.cfg =
565	{
566	grpci2_cfg_r8,
567	grpci2_cfg_r16,
568	grpci2_cfg_r32,
569	grpci2_cfg_w8,
570	grpci2_cfg_w16,
571	grpci2_cfg_w32,
572	},
573	.io =
574	{
575	_ld8,
576	_ld_le16,
577	_ld_le32,
578	_st8,
579	_st_le16,
580	_st_le32,
581	},
582	.memreg = &pci_memreg_sparc_le_ops,
583	.translate = grpci2_translate,
584	};
585
586	struct pci_io_ops grpci2_io_ops_be =
587	{
588	_ld8,
589	_ld_be16,
590	_ld_be32,
591	_st8,
592	_st_be16,
593	_st_be32,
594	};
595
596	/* PCI Error Interrupt handler, called when there may be a PCI Target/Master
597	* Abort.
598	*/
599	void grpci2_err_isr(void *arg)
600	{
601	struct grpci2_priv *priv = arg;
602	unsigned int sts = priv->regs->sts_cap;
603
604	if (sts & (STS_IMSTABRT \| STS_ITGTABRT \| STS_IPARERR \| STS_ISYSERR)) {
605	/* A PCI error IRQ ... Error handler unimplemented
606	* add your code here...
607	*/
608	if (sts & STS_IMSTABRT) {
609	printk("GRPCI2: unhandled Master Abort IRQ\n");
610	}
611	if (sts & STS_ITGTABRT) {
612	printk("GRPCI2: unhandled Target Abort IRQ\n");
613	}
614	if (sts & STS_IPARERR) {
615	printk("GRPCI2: unhandled Parity Error IRQ\n");
616	}
617	if (sts & STS_ISYSERR) {
618	printk("GRPCI2: unhandled System Error IRQ\n");
619	}
620	}
621	}
622
623	int grpci2_hw_init(struct grpci2_priv *priv)
624	{
625	struct grpci2_regs *regs = priv->regs;
626	int i;
627	uint8_t capptr;
628	uint32_t data, io_map, ahbadr, pciadr, size;
629	pci_dev_t host = PCI_DEV(0, 0, 0);
630	struct grpci2_pcibar_cfg *barcfg = priv->barcfg;
631
632	/* Reset any earlier setup */
633	regs->ctrl = 0;
634	regs->sts_cap = ~0; /* Clear Status */
635	regs->dma_ctrl = 0;
636	regs->dma_bdbase = 0;
637
638	/* Translate I/O accesses 1:1, (will not work for PCI 2.3) */
639	regs->io_map = priv->pci_io & 0xffff0000;
640
641	/* set 1:1 mapping between AHB -> PCI memory space, for all Masters
642	* Each AHB master has it's own mapping registers. Max 16 AHB masters.
643	*/
644	for (i=0; i<16; i++)
645	regs->ahbmst_map[i] = priv->pci_area;
646
647	/* Get the GRPCI2 Host PCI ID */
648	grpci2_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
649
650	/* Get address to first (always defined) capability structure */
651	grpci2_cfg_r8(host, PCI_CAP_PTR, &capptr);
652	if (capptr == 0)
653	return -1;
654
655	/* Limit the prefetch for GRPCI2 version 0. */
656	if (priv->ver == 0)
657	grpci2_cfg_w32(host, capptr+CAP9_AHBPREF_OFS, 0);
658
659	/* Enable/Disable Byte twisting */
660	grpci2_cfg_r32(host, capptr+CAP9_IOMAP_OFS, &io_map);
661	io_map = (io_map & ~0x1) \| (priv->bt_enabled ? 1 : 0);
662	grpci2_cfg_w32(host, capptr+CAP9_IOMAP_OFS, io_map);
663
664	/* Setup the Host's PCI Target BARs for others to access (DMA) */
665	for (i=0; i<6; i++) {
666	/* Make sure address is properly aligned */
667	size = ~(barcfg[i].barsize-1);
668	barcfg[i].pciadr &= size;
669	barcfg[i].ahbadr &= size;
670
671	pciadr = barcfg[i].pciadr;
672	ahbadr = barcfg[i].ahbadr;
673	size \|= PCI_BASE_ADDRESS_MEM_PREFETCH;
674
675	grpci2_cfg_w32(host, capptr+CAP9_BARSIZE_OFS+i*4, size);
676	grpci2_cfg_w32(host, capptr+CAP9_BAR_OFS+i*4, ahbadr);
677	grpci2_cfg_w32(host, PCI_BASE_ADDRESS_0+i*4, pciadr);
678	}
679
680	/* set as bus master and enable pci memory responses */
681	grpci2_cfg_r32(host, PCI_COMMAND, &data);
682	data \|= (PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
683	grpci2_cfg_w32(host, PCI_COMMAND, data);
684
685	/* Enable Error respone (CPU-TRAP) on illegal memory access */
686	regs->ctrl = CTRL_ER \| CTRL_PE;
687
688	/* Successful */
689	return 0;
690	}
691
692	/* Initializes the GRPCI2 core and driver, must be called before calling
693	* init_pci()
694	*
695	* Return values
696	* 0 Successful initalization
697	* -1 Error during initialization, for example "PCI core not found".
698	* -2 Error PCI controller not HOST (targets not supported)
699	* -3 Error due to GRPCI2 hardware initialization
700	*/
701	int grpci2_init(struct grpci2_priv *priv)
702	{
703	struct ambapp_apb_info *apb;
704	struct ambapp_ahb_info *ahb;
705	int pin, i, j;
706	union drvmgr_key_value *value;
707	char keyname[6];
708	struct amba_dev_info *ainfo = priv->dev->businfo;
709	struct grpci2_pcibar_cfg *barcfg;
710	unsigned int size;
711
712	/* Find PCI core from Plug&Play information */
713	apb = ainfo->info.apb_slv;
714	ahb = ainfo->info.ahb_slv;
715
716	/* Found PCI core, init private structure */
717	priv->irq = apb->irq;
718	priv->ver = apb->ver;
719	priv->regs = (struct grpci2_regs *)apb->start;
720	priv->bt_enabled = DEFAULT_BT_ENABLED;
721	priv->irq_mode = (priv->regs->sts_cap & STS_IRQMODE) >> STS_IRQMODE_BIT;
722
723	/* Calculate the PCI windows
724	* AMBA->PCI Window: AHB SLAVE AREA0
725	* AMBA->PCI I/O cycles Window: AHB SLAVE AREA1 Lower half
726	* AMBA->PCI Configuration cycles Window: AHB SLAVE AREA1 Upper half
727	*/
728	priv->pci_area = ahb->start[0];
729	priv->pci_area_end = ahb->start[0] + ahb->mask[0];
730	priv->pci_io = ahb->start[1];
731	priv->pci_conf = ahb->start[1] + 0x10000;
732	priv->pci_conf_end = priv->pci_conf + 0x10000;
733
734	/* On systems where PCI I/O area and configuration area is apart of the
735	* "PCI Window" the PCI Window stops at the start of the PCI I/O area
736	*/
737	if ((priv->pci_io > priv->pci_area) &&
738	(priv->pci_io < (priv->pci_area_end-1))) {
739	priv->pci_area_end = priv->pci_io;
740	}
741
742	/* Init PCI interrupt assignment table to all use the interrupt routed
743	* through the GRPCI2 core.
744	*/
745	strcpy(keyname, "INTX#");
746	for (pin=1; pin<5; pin++) {
747	if (grpci2_pci_irq_table[pin-1] == 0xff) {
748	if (priv->irq_mode < 2) {
749	/* PCI Interrupts are shared */
750	grpci2_pci_irq_table[pin-1] = priv->irq;
751	} else {
752	/* Unique IRQ per PCI INT Pin */
753	grpci2_pci_irq_table[pin-1] = priv->irq + pin-1;
754	}
755
756	/* User may override Both hardcoded IRQ setup and Plug & Play IRQ */
757	keyname[3] = 'A' + (pin-1);
758	value = drvmgr_dev_key_get(priv->dev, keyname, KEY_TYPE_INT);
759	if (value)
760	grpci2_pci_irq_table[pin-1] = value->i;
761	}
762
763	/* Remember which IRQs are enabled */
764	if (grpci2_pci_irq_table[pin-1] != 0)
765	priv->irq_mask \|= 1 << (pin-1);
766	}
767
768	/* User may override DEFAULT_BT_ENABLED to enable/disable byte twisting */
769	value = drvmgr_dev_key_get(priv->dev, "byteTwisting", KEY_TYPE_INT);
770	if (value)
771	priv->bt_enabled = value->i;
772
773	/* Let user Configure the 6 target BARs */
774	value = drvmgr_dev_key_get(priv->dev, "tgtBarCfg", KEY_TYPE_POINTER);
775	if (value)
776	priv->barcfg = value->ptr;
777	else
778	priv->barcfg = grpci2_default_bar_mapping;
779
780	/* This driver only support HOST systems, we check that it can act as a
781	* PCI Master and that it is in the Host slot. */
782	if ((priv->regs->sts_cap&STS_HOST) \|\| !(priv->regs->sts_cap&STS_MST))
783	return -2; /* Target not supported */
784
785	/* Init the PCI Core */
786	if (grpci2_hw_init(priv))
787	return -3;
788
789	/* Down streams translation table */
790	priv->maps_down[0].name = "AMBA -> PCI MEM Window";
791	priv->maps_down[0].size = priv->pci_area_end - priv->pci_area;
792	priv->maps_down[0].from_adr = (void *)priv->pci_area;
793	priv->maps_down[0].to_adr = (void *)priv->pci_area;
794	/* End table */
795	priv->maps_down[1].size = 0;
796
797	/* Up streams translation table */
798	/* Setup the Host's PCI Target BARs for others to access (DMA) */
799	barcfg = priv->barcfg;
800	for (i=0,j=0; i<6; i++) {
801	size = barcfg[i].barsize;
802	if (size == 0)
803	continue;
804
805	/* Make sure address is properly aligned */
806	priv->maps_up[j].name = "Target BAR[I] -> AMBA";
807	priv->maps_up[j].size = size;
808	priv->maps_up[j].from_adr = (void *)
809	(barcfg[i].pciadr & ~(size - 1));
810	priv->maps_up[j].to_adr = (void *)
811	(barcfg[i].ahbadr & ~(size - 1));
812	j++;
813	}
814
815	/* End table */
816	priv->maps_up[j].size = 0;
817
818	return 0;
819	}
820
821	/* Called when a core is found with the AMBA device and vendor ID
822	* given in grpci2_ids[]. IRQ, Console does not work here
823	*/
824	int grpci2_init1(struct drvmgr_dev *dev)
825	{
826	int status;
827	struct grpci2_priv *priv;
828	struct pci_auto_setup grpci2_auto_cfg;
829
830	DBG("GRPCI2[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
831
832	if (grpci2priv) {
833	DBG("Driver only supports one PCI core\n");
834	return DRVMGR_FAIL;
835	}
836
837	if ((strcmp(dev->parent->dev->drv->name, "AMBAPP_GRLIB_DRV") != 0) &&
838	(strcmp(dev->parent->dev->drv->name, "AMBAPP_LEON2_DRV") != 0)) {
839	/* We only support GRPCI2 driver on local bus */
840	return DRVMGR_FAIL;
841	}
842
843	priv = dev->priv;
844	if (!priv)
845	return DRVMGR_NOMEM;
846
847	priv->dev = dev;
848	grpci2priv = priv;
849
850	/* Initialize GRPCI2 Hardware */
851	status = grpci2_init(priv);
852	if (status) {
853	printf("Failed to initialize grpci2 driver %d\n", status);
854	return -1;
855	}
856
857	/* Register the PCI core at the PCI layers */
858
859	if (priv->bt_enabled == 0) {
860	/* Host is Big-Endian */
861	pci_endian = PCI_BIG_ENDIAN;
862
863	memcpy(&grpci2_access_drv.io, &grpci2_io_ops_be,
864	sizeof(grpci2_io_ops_be));
865	grpci2_access_drv.memreg = &pci_memreg_sparc_be_ops;
866	}
867
868	if (pci_access_drv_register(&grpci2_access_drv)) {
869	/* Access routines registration failed */
870	return DRVMGR_FAIL;
871	}
872
873	/* Prepare memory MAP */
874	grpci2_auto_cfg.options = 0;
875	grpci2_auto_cfg.mem_start = 0;
876	grpci2_auto_cfg.mem_size = 0;
877	grpci2_auto_cfg.memio_start = priv->pci_area;
878	grpci2_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area;
879	grpci2_auto_cfg.io_start = 0x100; /* avoid PCI address 0 */
880	grpci2_auto_cfg.io_size = 0x10000 - 0x100; /* lower 64kB I/O 16 */
881	grpci2_auto_cfg.irq_map = grpci2_bus0_irq_map;
882	grpci2_auto_cfg.irq_route = NULL; /* use standard routing */
883	pci_config_register(&grpci2_auto_cfg);
884
885	if (pci_config_init()) {
886	/* PCI configuration failed */
887	return DRVMGR_FAIL;
888	}
889
890	/* Initialize/Register Driver Manager PCI Bus */
891	priv->config.maps_down = &priv->maps_down[0];
892	priv->config.maps_up = &priv->maps_up[0];
893	return pcibus_register(dev, &priv->config);
894	}
895
896	int grpci2_init3(struct drvmgr_dev *dev)
897	{
898	struct grpci2_priv *priv = dev->priv;
899
900	/* Install and Enable PCI Error interrupt handler */
901	drvmgr_interrupt_register(dev, 0, "grpci2", grpci2_err_isr, priv);
902
903	/* Unmask Error IRQ and all PCI interrupts at PCI Core. For this to be
904	* safe every PCI board have to be resetted (no IRQ generation) before
905	* Global IRQs are enabled (Init is reached or similar)
906	*/
907	priv->regs->ctrl \|= (CTRL_EI \| priv->irq_mask);
908
909	return DRVMGR_OK;
910	}

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