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source: rtems/c/src/lib/libbsp/sparc/shared/pci/grpci2.c @ bb8e099

5

Last change on this file since bb8e099 was bb8e099, checked in by Javier Jalle <javier.jalle@…>, on 01/26/17 at 15:03:19
leon, grpci2: updated DMA descriptor layout
Property mode set to `100644`
File size: 24.4 KB

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1	/* GRLIB GRPCI2 PCI HOST driver.
2	*
3	* COPYRIGHT (c) 2011
4	* Cobham Gaisler AB.
5	*
6	* The license and distribution terms for this file may be
7	* found in found in the file LICENSE in this distribution or at
8	* http://www.rtems.org/license/LICENSE.
9	*/
10
11	/* Configures the GRPCI2 core and initialize,
12	* - the PCI Library (pci.c)
13	* - the general part of the PCI Bus driver (pci_bus.c)
14	*
15	* System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
16	* default taken from Plug and Play, but may be overridden by the
17	* driver resources INTA#..INTD#. GRPCI2 handles differently depending
18	* on the design (4 different ways).
19	*
20	* GRPCI2 IRQ implementation notes
21	* -------------------------------
22	* Since the Driver Manager pci_bus layer implements IRQ by calling
23	* pci_interrupt_* which translates into BSP_shared_interrupt_*, and the
24	* root-bus also relies on BSP_shared_interrupt_*, it is safe for the GRPCI2
25	* driver to use the drvmgr_interrupt_* routines since they will be
26	* accessing the same routines in the end. Otherwise the GRPCI2 driver must
27	* have used the pci_interrupt_* routines.
28	*/
29
30	#include <stdlib.h>
31	#include <stdio.h>
32	#include <string.h>
33	#include <rtems/bspIo.h>
34	#include <libcpu/byteorder.h>
35	#include <libcpu/access.h>
36	#include <pci.h>
37	#include <pci/cfg.h>
38
39	#include <drvmgr/drvmgr.h>
40	#include <drvmgr/ambapp_bus.h>
41	#include <ambapp.h>
42	#include <drvmgr/pci_bus.h>
43	#include <bsp/grpci2.h>
44
45	#ifndef IRQ_GLOBAL_PREPARE
46	#define IRQ_GLOBAL_PREPARE(level) rtems_interrupt_level level
47	#endif
48
49	#ifndef IRQ_GLOBAL_DISABLE
50	#define IRQ_GLOBAL_DISABLE(level) rtems_interrupt_disable(level)
51	#endif
52
53	#ifndef IRQ_GLOBAL_ENABLE
54	#define IRQ_GLOBAL_ENABLE(level) rtems_interrupt_enable(level)
55	#endif
56
57	/* If defined to 1 - byte twisting is enabled by default */
58	#define DEFAULT_BT_ENABLED 0
59
60	/* Interrupt assignment. Set to other value than 0xff in order to
61	* override defaults and plug&play information
62	*/
63	#ifndef GRPCI2_INTA_SYSIRQ
64	#define GRPCI2_INTA_SYSIRQ 0xff
65	#endif
66	#ifndef GRPCI2_INTB_SYSIRQ
67	#define GRPCI2_INTB_SYSIRQ 0xff
68	#endif
69	#ifndef GRPCI2_INTC_SYSIRQ
70	#define GRPCI2_INTC_SYSIRQ 0xff
71	#endif
72	#ifndef GRPCI2_INTD_SYSIRQ
73	#define GRPCI2_INTD_SYSIRQ 0xff
74	#endif
75
76	/#define DEBUG 1/
77
78	#ifdef DEBUG
79	#define DBG(x...) printk(x)
80	#else
81	#define DBG(x...)
82	#endif
83
84	/*
85	* GRPCI2 APB Register MAP
86	*/
87	struct grpci2_regs {
88	volatile unsigned int ctrl; /* 0x00 */
89	volatile unsigned int sts_cap; /* 0x04 */
90	volatile unsigned int ppref; /* 0x08 */
91	volatile unsigned int io_map; /* 0x0C */
92	volatile unsigned int dma_ctrl; /* 0x10 */
93	volatile unsigned int dma_bdbase; /* 0x14 */
94	volatile unsigned int dma_chact; /* 0x18 */
95	int res1; /* 0x1C */
96	volatile unsigned int bars[6]; /* 0x20 */
97	int res2[2]; /* 0x38 */
98	volatile unsigned int ahbmst_map[16]; /* 0x40 */
99	};
100
101	#define CTRL_BUS_BIT 16
102
103	#define CTRL_SI (1<<27)
104	#define CTRL_PE (1<<26)
105	#define CTRL_ER (1<<25)
106	#define CTRL_EI (1<<24)
107	#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
108	#define CTRL_HOSTINT 0xf
109
110	#define STS_HOST_BIT 31
111	#define STS_MST_BIT 30
112	#define STS_TAR_BIT 29
113	#define STS_DMA_BIT 28
114	#define STS_DI_BIT 27
115	#define STS_HI_BIT 26
116	#define STS_IRQMODE_BIT 24
117	#define STS_TRACE_BIT 23
118	#define STS_CFGERRVALID_BIT 20
119	#define STS_CFGERR_BIT 19
120	#define STS_INTTYPE_BIT 12
121	#define STS_INTSTS_BIT 8
122	#define STS_FDEPTH_BIT 2
123	#define STS_FNUM_BIT 0
124
125	#define STS_HOST (1<<STS_HOST_BIT)
126	#define STS_MST (1<<STS_MST_BIT)
127	#define STS_TAR (1<<STS_TAR_BIT)
128	#define STS_DMA (1<<STS_DMA_BIT)
129	#define STS_DI (1<<STS_DI_BIT)
130	#define STS_HI (1<<STS_HI_BIT)
131	#define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
132	#define STS_TRACE (1<<STS_TRACE_BIT)
133	#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
134	#define STS_CFGERR (1<<STS_CFGERR_BIT)
135	#define STS_INTTYPE (0x7f<<STS_INTTYPE_BIT)
136	#define STS_INTSTS (0xf<<STS_INTSTS_BIT)
137	#define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
138	#define STS_FNUM (0x3<<STS_FNUM_BIT)
139
140	#define STS_ITIMEOUT (1<<18)
141	#define STS_ISYSERR (1<<17)
142	#define STS_IDMA (1<<16)
143	#define STS_IDMAERR (1<<15)
144	#define STS_IMSTABRT (1<<14)
145	#define STS_ITGTABRT (1<<13)
146	#define STS_IPARERR (1<<12)
147
148	struct grpci2_bd_chan {
149	volatile unsigned int ctrl; /* 0x00 DMA Control */
150	volatile unsigned int nchan; /* 0x04 Next DMA Channel Address */
151	volatile unsigned int nbd; /* 0x08 Next Data Descriptor in channel */
152	volatile unsigned int res; /* 0x0C Reserved */
153	};
154
155	#define BD_CHAN_EN (1<<BD_CHAN_EN_BIT)
156	#define BD_CHAN_ID (0x3<<BD_CHAN_ID_BIT)
157	#define BD_CHAN_TYPE (0x3<<BD_CHAN_TYPE_BIT)
158	#define BD_CHAN_BDCNT (0xffff<<BD_CHAN_BDCNT_BIT)
159	#define BD_CHAN_EN_BIT 31
160	#define BD_CHAN_ID_BIT 22
161	#define BD_CHAN_TYPE_BIT 20
162	#define BD_CHAN_BDCNT_BIT 0
163
164	struct grpci2_bd_data {
165	volatile unsigned int ctrl; /* 0x00 DMA Data Control */
166	volatile unsigned int pci_adr; /* 0x04 PCI Start Address */
167	volatile unsigned int ahb_adr; /* 0x08 AHB Start address */
168	volatile unsigned int next; /* 0x0C Next Data Descriptor in channel */
169	};
170
171	#define BD_DATA_EN (0x1<<BD_DATA_EN_BIT)
172	#define BD_DATA_IE (0x1<<BD_DATA_IE_BIT)
173	#define BD_DATA_DR (0x1<<BD_DATA_DR_BIT)
174	#define BD_DATA_BE (0x1<<BD_DATA_BE_BIT)
175	#define BD_DATA_TYPE (0x3<<BD_DATA_TYPE_BIT)
176	#define BD_DATA_ER (0x1<<BD_DATA_ER_BIT)
177	#define BD_DATA_LEN (0xffff<<BD_DATA_LEN_BIT)
178	#define BD_DATA_EN_BIT 31
179	#define BD_DATA_IE_BIT 30
180	#define BD_DATA_DR_BIT 29
181	#define BD_DATA_BE_BIT 28
182	#define BD_DATA_TYPE_BIT 20
183	#define BD_DATA_ER_BIT 19
184	#define BD_DATA_LEN_BIT 0
185
186	/* GRPCI2 Capability */
187	struct grpci2_cap_first {
188	unsigned int ctrl;
189	unsigned int pci2ahb_map[6];
190	unsigned int ext2ahb_map;
191	unsigned int io_map;
192	unsigned int pcibar_size[6];
193	unsigned int ahb_pref;
194	};
195	#define CAP9_CTRL_OFS 0
196	#define CAP9_BAR_OFS 0x4
197	#define CAP9_IOMAP_OFS 0x20
198	#define CAP9_BARSIZE_OFS 0x24
199	#define CAP9_AHBPREF_OFS 0x3C
200
201	/* Used internally for accessing the PCI bridge's configuration space itself */
202	#define HOST_TGT PCI_DEV(0xff, 0, 0)
203
204	struct grpci2_priv *grpci2priv = NULL;
205
206	/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
207	* to a system interrupt number.
208	*/
209	unsigned char grpci2_pci_irq_table[4] =
210	{
211	/* INTA# */ GRPCI2_INTA_SYSIRQ,
212	/* INTB# */ GRPCI2_INTB_SYSIRQ,
213	/* INTC# */ GRPCI2_INTC_SYSIRQ,
214	/* INTD# */ GRPCI2_INTD_SYSIRQ
215	};
216
217	/* Start of workspace/dynamical area */
218	extern unsigned int _end;
219	#define DMA_START ((unsigned int) &_end)
220
221	/* Default BAR mapping, set BAR0 256MB 1:1 mapped base of CPU RAM */
222	struct grpci2_pcibar_cfg grpci2_default_bar_mapping[6] = {
223	/* BAR0 */ {DMA_START, DMA_START, 0x10000000},
224	/* BAR1 */ {0, 0, 0},
225	/* BAR2 */ {0, 0, 0},
226	/* BAR3 */ {0, 0, 0},
227	/* BAR4 */ {0, 0, 0},
228	/* BAR5 */ {0, 0, 0},
229	};
230
231	/* Driver private data struture */
232	struct grpci2_priv {
233	struct drvmgr_dev *dev;
234	struct grpci2_regs *regs;
235	unsigned char ver;
236	char irq;
237	char irq_mode; /* IRQ Mode from CAPSTS REG */
238	char bt_enabled;
239	unsigned int irq_mask;
240
241	struct grpci2_pcibar_cfg *barcfg;
242
243	unsigned int pci_area;
244	unsigned int pci_area_end;
245	unsigned int pci_io;
246	unsigned int pci_conf;
247	unsigned int pci_conf_end;
248
249	uint32_t devVend; /* Host PCI Device/Vendor ID */
250
251	struct drvmgr_map_entry maps_up[7];
252	struct drvmgr_map_entry maps_down[2];
253	struct pcibus_config config;
254	};
255
256	int grpci2_init1(struct drvmgr_dev *dev);
257	int grpci2_init3(struct drvmgr_dev *dev);
258	void grpci2_err_isr(void *arg);
259
260	/* GRPCI2 DRIVER */
261
262	struct drvmgr_drv_ops grpci2_ops =
263	{
264	.init = {grpci2_init1, NULL, grpci2_init3, NULL},
265	.remove = NULL,
266	.info = NULL
267	};
268
269	struct amba_dev_id grpci2_ids[] =
270	{
271	{VENDOR_GAISLER, GAISLER_GRPCI2},
272	{0, 0} /* Mark end of table */
273	};
274
275	struct amba_drv_info grpci2_info =
276	{
277	{
278	DRVMGR_OBJ_DRV, /* Driver */
279	NULL, /* Next driver */
280	NULL, /* Device list */
281	DRIVER_AMBAPP_GAISLER_GRPCI2_ID,/* Driver ID */
282	"GRPCI2_DRV", /* Driver Name */
283	DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
284	&grpci2_ops,
285	NULL, /* Funcs */
286	0, /* No devices yet */
287	sizeof(struct grpci2_priv), /* Make drvmgr alloc private */
288	},
289	&grpci2_ids[0]
290	};
291
292	void grpci2_register_drv(void)
293	{
294	DBG("Registering GRPCI2 driver\n");
295	drvmgr_drv_register(&grpci2_info.general);
296	}
297
298	static int grpci2_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val)
299	{
300	struct grpci2_priv *priv = grpci2priv;
301	volatile uint32_t *pci_conf;
302	unsigned int tmp, devfn;
303	IRQ_GLOBAL_PREPARE(oldLevel);
304	int retval, bus = PCI_DEV_BUS(dev);
305
306	if ((unsigned int)ofs & 0xffffff03) {
307	retval = PCISTS_EINVAL;
308	goto out2;
309	}
310
311	if (PCI_DEV_SLOT(dev) > 15) {
312	retval = PCISTS_MSTABRT;
313	goto out;
314	}
315
316	/* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
317	* we skip them.
318	*/
319	if (dev == HOST_TGT)
320	bus = devfn = 0;
321	else if (bus == 0)
322	devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
323	else
324	devfn = PCI_DEV_DEVFUNC(dev);
325
326	pci_conf = (volatile uint32_t *) (priv->pci_conf \| (devfn << 8) \| ofs);
327
328	IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
329
330	/* Select bus */
331	priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) \| (bus<<16);
332	/* clear old status */
333	priv->regs->sts_cap = (STS_CFGERR \| STS_CFGERRVALID);
334
335	tmp = *pci_conf;
336
337	/* Wait until GRPCI2 signals that CFG access is done, it should be
338	* done instantaneously unless a DMA operation is ongoing...
339	*/
340	while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
341	;
342
343	if (priv->regs->sts_cap & STS_CFGERR) {
344	retval = PCISTS_MSTABRT;
345	} else {
346	/* Bus always little endian (unaffected by byte-swapping) */
347	*val = CPU_swap_u32(tmp);
348	retval = PCISTS_OK;
349	}
350
351	IRQ_GLOBAL_ENABLE(oldLevel);
352
353	out:
354	if (retval != PCISTS_OK)
355	*val = 0xffffffff;
356
357	DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
358	PCI_DEV_EXPAND(dev), ofs, pci_conf, *val, retval);
359
360	out2:
361	return retval;
362	}
363
364	static int grpci2_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
365	{
366	uint32_t v;
367	int retval;
368
369	if (ofs & 1)
370	return PCISTS_EINVAL;
371
372	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
373	val = 0xffff & (v >> (8(ofs & 0x3)));
374
375	return retval;
376	}
377
378	static int grpci2_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
379	{
380	uint32_t v;
381	int retval;
382
383	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
384
385	val = 0xff & (v >> (8(ofs & 3)));
386
387	return retval;
388	}
389
390	static int grpci2_cfg_w32(pci_dev_t dev, int ofs, uint32_t val)
391	{
392	struct grpci2_priv *priv = grpci2priv;
393	volatile uint32_t *pci_conf;
394	uint32_t value, devfn;
395	int retval, bus = PCI_DEV_BUS(dev);
396	IRQ_GLOBAL_PREPARE(oldLevel);
397
398	if ((unsigned int)ofs & 0xffffff03)
399	return PCISTS_EINVAL;
400
401	if (PCI_DEV_SLOT(dev) > 15)
402	return PCISTS_MSTABRT;
403
404	value = CPU_swap_u32(val);
405
406	/* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
407	* we skip them.
408	*/
409	if (dev == HOST_TGT)
410	bus = devfn = 0;
411	else if (bus == 0)
412	devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
413	else
414	devfn = PCI_DEV_DEVFUNC(dev);
415
416	pci_conf = (volatile uint32_t *) (priv->pci_conf \| (devfn << 8) \| ofs);
417
418	IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
419
420	/* Select bus */
421	priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) \| (bus<<16);
422	/* clear old status */
423	priv->regs->sts_cap = (STS_CFGERR \| STS_CFGERRVALID);
424
425	*pci_conf = value;
426
427	/* Wait until GRPCI2 signals that CFG access is done, it should be
428	* done instantaneously unless a DMA operation is ongoing...
429	*/
430	while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
431	;
432
433	if (priv->regs->sts_cap & STS_CFGERR)
434	retval = PCISTS_MSTABRT;
435	else
436	retval = PCISTS_OK;
437
438	IRQ_GLOBAL_ENABLE(oldLevel);
439
440	DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
441	PCI_DEV_EXPAND(dev), ofs, pci_conf, value, retval);
442
443	return retval;
444	}
445
446	static int grpci2_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
447	{
448	uint32_t v;
449	int retval;
450
451	if (ofs & 1)
452	return PCISTS_EINVAL;
453
454	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
455	if (retval != PCISTS_OK)
456	return retval;
457
458	v = (v & ~(0xffff << (8(ofs&3)))) \| ((0xffff&val) << (8(ofs&3)));
459
460	return grpci2_cfg_w32(dev, ofs & ~0x3, v);
461	}
462
463	static int grpci2_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
464	{
465	uint32_t v;
466	int retval;
467
468	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
469	if (retval != PCISTS_OK)
470	return retval;
471
472	v = (v & ~(0xff << (8(ofs&3)))) \| ((0xff&val) << (8(ofs&3)));
473
474	return grpci2_cfg_w32(dev, ofs & ~0x3, v);
475	}
476
477	/* Return the assigned system IRQ number that corresponds to the PCI
478	* "Interrupt Pin" information from configuration space.
479	*
480	* The IRQ information is stored in the grpci2_pci_irq_table configurable
481	* by the user.
482	*
483	* Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
484	* 0xff if not assigned.
485	*/
486	static uint8_t grpci2_bus0_irq_map(pci_dev_t dev, int irq_pin)
487	{
488	uint8_t sysIrqNr = 0; /* not assigned */
489	int irq_group;
490
491	if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
492	/* Use default IRQ decoding on PCI BUS0 according slot numbering */
493	irq_group = PCI_DEV_SLOT(dev) & 0x3;
494	irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
495	/* Valid PCI "Interrupt Pin" number */
496	sysIrqNr = grpci2_pci_irq_table[irq_pin];
497	}
498	return sysIrqNr;
499	}
500
501	static int grpci2_translate(uint32_t *address, int type, int dir)
502	{
503	uint32_t adr, start, end;
504	struct grpci2_priv *priv = grpci2priv;
505	int i;
506
507	if (type == 1) {
508	/* I/O */
509	if (dir != 0) {
510	/* The PCI bus can not access the CPU bus from I/O
511	* because GRPCI2 core does not support I/O BARs
512	*/
513	return -1;
514	}
515
516	/* We have got a PCI IO BAR address that the CPU want to access.
517	* Check that it is within the PCI I/O window, I/O adresses
518	* are NOT mapped 1:1 with GRPCI2 driver... translation needed.
519	*/
520	adr = (uint32_t )address;
521	if (adr < 0x100 \|\| adr > 0x10000)
522	return -1;
523	*address = adr + priv->pci_io;
524	} else {
525	/* MEMIO and MEM.
526	* Memory space is mapped 1:1 so no translation is needed.
527	* Check that address is within accessible windows.
528	*/
529	adr = (uint32_t )address;
530	if (dir == 0) {
531	/* PCI BAR to AMBA-CPU address.. check that it is
532	* located within GRPCI2 PCI Memory Window
533	* adr = PCI address.
534	*/
535	if (adr < priv->pci_area \|\| adr >= priv->pci_area_end)
536	return -1;
537	} else {
538	/* We have a CPU address and want to get access to it
539	* from PCI space, typically when doing DMA into CPU
540	* RAM. The GRPCI2 core may have multiple target BARs
541	* that PCI masters can access, the BARs are user
542	* configurable in the following ways:
543	* BAR_SIZE, PCI_BAR Address and MAPPING (AMBA ADR)
544	*
545	* The below code tries to find a BAR for which the
546	* AMBA bar may have been mapped onto, and translate
547	* the AMBA-CPU address into a PCI address using the
548	* given mapping.
549	*
550	* adr = AMBA address.
551	*/
552	for(i=0; i<6; i++) {
553	start = priv->barcfg[i].ahbadr;
554	end = priv->barcfg[i].ahbadr +
555	priv->barcfg[i].barsize;
556	if (adr >= start && adr < end) {
557	/* BAR match: Translate address */
558	*address = (adr - start) +
559	priv->barcfg[i].pciadr;
560	return 0;
561	}
562	}
563	return -1;
564	}
565	}
566
567	return 0;
568	}
569
570	extern struct pci_memreg_ops pci_memreg_sparc_le_ops;
571	extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
572
573	/* GRPCI2 PCI access routines, default to Little-endian PCI Bus */
574	struct pci_access_drv grpci2_access_drv = {
575	.cfg =
576	{
577	grpci2_cfg_r8,
578	grpci2_cfg_r16,
579	grpci2_cfg_r32,
580	grpci2_cfg_w8,
581	grpci2_cfg_w16,
582	grpci2_cfg_w32,
583	},
584	.io =
585	{
586	_ld8,
587	_ld_le16,
588	_ld_le32,
589	_st8,
590	_st_le16,
591	_st_le32,
592	},
593	.memreg = &pci_memreg_sparc_le_ops,
594	.translate = grpci2_translate,
595	};
596
597	struct pci_io_ops grpci2_io_ops_be =
598	{
599	_ld8,
600	_ld_be16,
601	_ld_be32,
602	_st8,
603	_st_be16,
604	_st_be32,
605	};
606
607	/* PCI Error Interrupt handler, called when there may be a PCI Target/Master
608	* Abort.
609	*/
610	void grpci2_err_isr(void *arg)
611	{
612	struct grpci2_priv *priv = arg;
613	unsigned int sts = priv->regs->sts_cap;
614
615	if (sts & (STS_IMSTABRT \| STS_ITGTABRT \| STS_IPARERR \| STS_ISYSERR \| STS_ITIMEOUT)) {
616	/* A PCI error IRQ ... Error handler unimplemented
617	* add your code here...
618	*/
619	if (sts & STS_IMSTABRT) {
620	printk("GRPCI2: unhandled Master Abort IRQ\n");
621	}
622	if (sts & STS_ITGTABRT) {
623	printk("GRPCI2: unhandled Target Abort IRQ\n");
624	}
625	if (sts & STS_IPARERR) {
626	printk("GRPCI2: unhandled Parity Error IRQ\n");
627	}
628	if (sts & STS_ISYSERR) {
629	printk("GRPCI2: unhandled System Error IRQ\n");
630	}
631	if (sts & STS_ITIMEOUT) {
632	printk("GRPCI2: unhandled PCI target access timeout IRQ\n");
633	}
634	}
635	}
636
637	static int grpci2_hw_init(struct grpci2_priv *priv)
638	{
639	struct grpci2_regs *regs = priv->regs;
640	int i;
641	uint8_t capptr;
642	uint32_t data, io_map, ahbadr, pciadr, size;
643	pci_dev_t host = HOST_TGT;
644	struct grpci2_pcibar_cfg *barcfg = priv->barcfg;
645
646	/* Reset any earlier setup */
647	regs->ctrl = 0;
648	regs->sts_cap = ~0; /* Clear Status */
649	regs->dma_ctrl = 0;
650	regs->dma_bdbase = 0;
651
652	/* Translate I/O accesses 1:1, (will not work for PCI 2.3) */
653	regs->io_map = priv->pci_io & 0xffff0000;
654
655	/* set 1:1 mapping between AHB -> PCI memory space, for all Masters
656	* Each AHB master has it's own mapping registers. Max 16 AHB masters.
657	*/
658	for (i=0; i<16; i++)
659	regs->ahbmst_map[i] = priv->pci_area;
660
661	/* Get the GRPCI2 Host PCI ID */
662	grpci2_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
663
664	/* Get address to first (always defined) capability structure */
665	grpci2_cfg_r8(host, PCIR_CAP_PTR, &capptr);
666	if (capptr == 0)
667	return -1;
668
669	/* Limit the prefetch for GRPCI2 version 0. */
670	if (priv->ver == 0)
671	grpci2_cfg_w32(host, capptr+CAP9_AHBPREF_OFS, 0);
672
673	/* Enable/Disable Byte twisting */
674	grpci2_cfg_r32(host, capptr+CAP9_IOMAP_OFS, &io_map);
675	io_map = (io_map & ~0x1) \| (priv->bt_enabled ? 1 : 0);
676	grpci2_cfg_w32(host, capptr+CAP9_IOMAP_OFS, io_map);
677
678	/* Setup the Host's PCI Target BARs for others to access (DMA) */
679	for (i=0; i<6; i++) {
680	/* Make sure address is properly aligned */
681	size = ~(barcfg[i].barsize-1);
682	barcfg[i].pciadr &= size;
683	barcfg[i].ahbadr &= size;
684
685	pciadr = barcfg[i].pciadr;
686	ahbadr = barcfg[i].ahbadr;
687	size \|= PCIM_BAR_MEM_PREFETCH;
688
689	grpci2_cfg_w32(host, capptr+CAP9_BARSIZE_OFS+i*4, size);
690	grpci2_cfg_w32(host, capptr+CAP9_BAR_OFS+i*4, ahbadr);
691	grpci2_cfg_w32(host, PCIR_BAR(0)+i*4, pciadr);
692	}
693
694	/* set as bus master and enable pci memory responses */
695	grpci2_cfg_r32(host, PCIR_COMMAND, &data);
696	data \|= (PCIM_CMD_MEMEN \| PCIM_CMD_BUSMASTEREN);
697	grpci2_cfg_w32(host, PCIR_COMMAND, data);
698
699	/* Enable Error respone (CPU-TRAP) on illegal memory access */
700	regs->ctrl = CTRL_ER \| CTRL_PE;
701
702	/* Successful */
703	return 0;
704	}
705
706	/* Initializes the GRPCI2 core and driver, must be called before calling
707	* init_pci()
708	*
709	* Return values
710	* 0 Successful initalization
711	* -1 Error during initialization, for example "PCI core not found".
712	* -2 Error PCI controller not HOST (targets not supported)
713	* -3 Error due to GRPCI2 hardware initialization
714	*/
715	static int grpci2_init(struct grpci2_priv *priv)
716	{
717	struct ambapp_apb_info *apb;
718	struct ambapp_ahb_info *ahb;
719	int pin, i, j;
720	union drvmgr_key_value *value;
721	char keyname[6];
722	struct amba_dev_info *ainfo = priv->dev->businfo;
723	struct grpci2_pcibar_cfg *barcfg;
724	unsigned int size;
725
726	/* Find PCI core from Plug&Play information */
727	apb = ainfo->info.apb_slv;
728	ahb = ainfo->info.ahb_slv;
729
730	/* Found PCI core, init private structure */
731	priv->irq = apb->irq;
732	priv->ver = apb->ver;
733	priv->regs = (struct grpci2_regs *)apb->start;
734	priv->bt_enabled = DEFAULT_BT_ENABLED;
735	priv->irq_mode = (priv->regs->sts_cap & STS_IRQMODE) >> STS_IRQMODE_BIT;
736
737	/* Calculate the PCI windows
738	* AMBA->PCI Window: AHB SLAVE AREA0
739	* AMBA->PCI I/O cycles Window: AHB SLAVE AREA1 Lower half
740	* AMBA->PCI Configuration cycles Window: AHB SLAVE AREA1 Upper half
741	*/
742	priv->pci_area = ahb->start[0];
743	priv->pci_area_end = ahb->start[0] + ahb->mask[0];
744	priv->pci_io = ahb->start[1];
745	priv->pci_conf = ahb->start[1] + 0x10000;
746	priv->pci_conf_end = priv->pci_conf + 0x10000;
747
748	/* On systems where PCI I/O area and configuration area is apart of the
749	* "PCI Window" the PCI Window stops at the start of the PCI I/O area
750	*/
751	if ((priv->pci_io > priv->pci_area) &&
752	(priv->pci_io < (priv->pci_area_end-1))) {
753	priv->pci_area_end = priv->pci_io;
754	}
755
756	/* Init PCI interrupt assignment table to all use the interrupt routed
757	* through the GRPCI2 core.
758	*/
759	strcpy(keyname, "INTX#");
760	for (pin=1; pin<5; pin++) {
761	if (grpci2_pci_irq_table[pin-1] == 0xff) {
762	if (priv->irq_mode < 2) {
763	/* PCI Interrupts are shared */
764	grpci2_pci_irq_table[pin-1] = priv->irq;
765	} else {
766	/* Unique IRQ per PCI INT Pin */
767	grpci2_pci_irq_table[pin-1] = priv->irq + pin-1;
768	}
769
770	/* User may override Both hardcoded IRQ setup and Plug & Play IRQ */
771	keyname[3] = 'A' + (pin-1);
772	value = drvmgr_dev_key_get(priv->dev, keyname, DRVMGR_KT_INT);
773	if (value)
774	grpci2_pci_irq_table[pin-1] = value->i;
775	}
776
777	/* Remember which IRQs are enabled */
778	if (grpci2_pci_irq_table[pin-1] != 0)
779	priv->irq_mask \|= 1 << (pin-1);
780	}
781
782	/* User may override DEFAULT_BT_ENABLED to enable/disable byte twisting */
783	value = drvmgr_dev_key_get(priv->dev, "byteTwisting", DRVMGR_KT_INT);
784	if (value)
785	priv->bt_enabled = value->i;
786
787	/* Let user Configure the 6 target BARs */
788	value = drvmgr_dev_key_get(priv->dev, "tgtBarCfg", DRVMGR_KT_POINTER);
789	if (value)
790	priv->barcfg = value->ptr;
791	else
792	priv->barcfg = grpci2_default_bar_mapping;
793
794	/* This driver only support HOST systems, we check that it can act as a
795	* PCI Master and that it is in the Host slot. */
796	if ((priv->regs->sts_cap&STS_HOST) \|\| !(priv->regs->sts_cap&STS_MST))
797	return -2; /* Target not supported */
798
799	/* Init the PCI Core */
800	if (grpci2_hw_init(priv))
801	return -3;
802
803	/* Down streams translation table */
804	priv->maps_down[0].name = "AMBA -> PCI MEM Window";
805	priv->maps_down[0].size = priv->pci_area_end - priv->pci_area;
806	priv->maps_down[0].from_adr = (void *)priv->pci_area;
807	priv->maps_down[0].to_adr = (void *)priv->pci_area;
808	/* End table */
809	priv->maps_down[1].size = 0;
810
811	/* Up streams translation table */
812	/* Setup the Host's PCI Target BARs for others to access (DMA) */
813	barcfg = priv->barcfg;
814	for (i=0,j=0; i<6; i++) {
815	size = barcfg[i].barsize;
816	if (size == 0)
817	continue;
818
819	/* Make sure address is properly aligned */
820	priv->maps_up[j].name = "Target BAR[I] -> AMBA";
821	priv->maps_up[j].size = size;
822	priv->maps_up[j].from_adr = (void *)
823	(barcfg[i].pciadr & ~(size - 1));
824	priv->maps_up[j].to_adr = (void *)
825	(barcfg[i].ahbadr & ~(size - 1));
826	j++;
827	}
828
829	/* End table */
830	priv->maps_up[j].size = 0;
831
832	return 0;
833	}
834
835	/* Called when a core is found with the AMBA device and vendor ID
836	* given in grpci2_ids[]. IRQ, Console does not work here
837	*/
838	int grpci2_init1(struct drvmgr_dev *dev)
839	{
840	int status;
841	struct grpci2_priv *priv;
842	struct pci_auto_setup grpci2_auto_cfg;
843
844	DBG("GRPCI2[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
845
846	if (grpci2priv) {
847	DBG("Driver only supports one PCI core\n");
848	return DRVMGR_FAIL;
849	}
850
851	if ((strcmp(dev->parent->dev->drv->name, "AMBAPP_GRLIB_DRV") != 0) &&
852	(strcmp(dev->parent->dev->drv->name, "AMBAPP_LEON2_DRV") != 0)) {
853	/* We only support GRPCI2 driver on local bus */
854	return DRVMGR_FAIL;
855	}
856
857	priv = dev->priv;
858	if (!priv)
859	return DRVMGR_NOMEM;
860
861	priv->dev = dev;
862	grpci2priv = priv;
863
864	/* Initialize GRPCI2 Hardware */
865	status = grpci2_init(priv);
866	if (status) {
867	printf("Failed to initialize grpci2 driver %d\n", status);
868	return -1;
869	}
870
871	/* Register the PCI core at the PCI layers */
872
873	if (priv->bt_enabled == 0) {
874	/* Host is Big-Endian */
875	pci_endian = PCI_BIG_ENDIAN;
876
877	memcpy(&grpci2_access_drv.io, &grpci2_io_ops_be,
878	sizeof(grpci2_io_ops_be));
879	grpci2_access_drv.memreg = &pci_memreg_sparc_be_ops;
880	}
881
882	if (pci_access_drv_register(&grpci2_access_drv)) {
883	/* Access routines registration failed */
884	return DRVMGR_FAIL;
885	}
886
887	/* Prepare memory MAP */
888	grpci2_auto_cfg.options = 0;
889	grpci2_auto_cfg.mem_start = 0;
890	grpci2_auto_cfg.mem_size = 0;
891	grpci2_auto_cfg.memio_start = priv->pci_area;
892	grpci2_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area;
893	grpci2_auto_cfg.io_start = 0x100; /* avoid PCI address 0 */
894	grpci2_auto_cfg.io_size = 0x10000 - 0x100; /* lower 64kB I/O 16 */
895	grpci2_auto_cfg.irq_map = grpci2_bus0_irq_map;
896	grpci2_auto_cfg.irq_route = NULL; /* use standard routing */
897	pci_config_register(&grpci2_auto_cfg);
898
899	if (pci_config_init()) {
900	/* PCI configuration failed */
901	return DRVMGR_FAIL;
902	}
903
904	/* Initialize/Register Driver Manager PCI Bus */
905	priv->config.maps_down = &priv->maps_down[0];
906	priv->config.maps_up = &priv->maps_up[0];
907	return pcibus_register(dev, &priv->config);
908	}
909
910	int grpci2_init3(struct drvmgr_dev *dev)
911	{
912	struct grpci2_priv *priv = dev->priv;
913
914	/* Install and Enable PCI Error interrupt handler */
915	drvmgr_interrupt_register(dev, 0, "grpci2", grpci2_err_isr, priv);
916
917	/* Unmask Error IRQ and all PCI interrupts at PCI Core. For this to be
918	* safe every PCI board have to be resetted (no IRQ generation) before
919	* Global IRQs are enabled (Init is reached or similar)
920	*/
921	priv->regs->ctrl \|= (CTRL_EI \| priv->irq_mask);
922
923	return DRVMGR_OK;
924	}

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