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source: rtems/c/src/lib/libbsp/sparc/shared/pci/grpci2.c @ a545ce26

5

Last change on this file since a545ce26 was a545ce26, checked in by Javier Jalle <javier.jalle@…>, on 01/26/17 at 14:31:17
leon, grpci2: added TIMEOUT interrupt
Property mode set to `100644`
File size: 24.1 KB

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1	/* GRLIB GRPCI2 PCI HOST driver.
2	*
3	* COPYRIGHT (c) 2011
4	* Cobham Gaisler AB.
5	*
6	* The license and distribution terms for this file may be
7	* found in found in the file LICENSE in this distribution or at
8	* http://www.rtems.org/license/LICENSE.
9	*/
10
11	/* Configures the GRPCI2 core and initialize,
12	* - the PCI Library (pci.c)
13	* - the general part of the PCI Bus driver (pci_bus.c)
14	*
15	* System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
16	* default taken from Plug and Play, but may be overridden by the
17	* driver resources INTA#..INTD#. GRPCI2 handles differently depending
18	* on the design (4 different ways).
19	*
20	* GRPCI2 IRQ implementation notes
21	* -------------------------------
22	* Since the Driver Manager pci_bus layer implements IRQ by calling
23	* pci_interrupt_* which translates into BSP_shared_interrupt_*, and the
24	* root-bus also relies on BSP_shared_interrupt_*, it is safe for the GRPCI2
25	* driver to use the drvmgr_interrupt_* routines since they will be
26	* accessing the same routines in the end. Otherwise the GRPCI2 driver must
27	* have used the pci_interrupt_* routines.
28	*/
29
30	#include <stdlib.h>
31	#include <stdio.h>
32	#include <string.h>
33	#include <rtems/bspIo.h>
34	#include <libcpu/byteorder.h>
35	#include <libcpu/access.h>
36	#include <pci.h>
37	#include <pci/cfg.h>
38
39	#include <drvmgr/drvmgr.h>
40	#include <drvmgr/ambapp_bus.h>
41	#include <ambapp.h>
42	#include <drvmgr/pci_bus.h>
43	#include <bsp/grpci2.h>
44
45	#ifndef IRQ_GLOBAL_PREPARE
46	#define IRQ_GLOBAL_PREPARE(level) rtems_interrupt_level level
47	#endif
48
49	#ifndef IRQ_GLOBAL_DISABLE
50	#define IRQ_GLOBAL_DISABLE(level) rtems_interrupt_disable(level)
51	#endif
52
53	#ifndef IRQ_GLOBAL_ENABLE
54	#define IRQ_GLOBAL_ENABLE(level) rtems_interrupt_enable(level)
55	#endif
56
57	/* If defined to 1 - byte twisting is enabled by default */
58	#define DEFAULT_BT_ENABLED 0
59
60	/* Interrupt assignment. Set to other value than 0xff in order to
61	* override defaults and plug&play information
62	*/
63	#ifndef GRPCI2_INTA_SYSIRQ
64	#define GRPCI2_INTA_SYSIRQ 0xff
65	#endif
66	#ifndef GRPCI2_INTB_SYSIRQ
67	#define GRPCI2_INTB_SYSIRQ 0xff
68	#endif
69	#ifndef GRPCI2_INTC_SYSIRQ
70	#define GRPCI2_INTC_SYSIRQ 0xff
71	#endif
72	#ifndef GRPCI2_INTD_SYSIRQ
73	#define GRPCI2_INTD_SYSIRQ 0xff
74	#endif
75
76	/#define DEBUG 1/
77
78	#ifdef DEBUG
79	#define DBG(x...) printk(x)
80	#else
81	#define DBG(x...)
82	#endif
83
84	/*
85	* GRPCI2 APB Register MAP
86	*/
87	struct grpci2_regs {
88	volatile unsigned int ctrl; /* 0x00 */
89	volatile unsigned int sts_cap; /* 0x04 */
90	volatile unsigned int ppref; /* 0x08 */
91	volatile unsigned int io_map; /* 0x0C */
92	volatile unsigned int dma_ctrl; /* 0x10 */
93	volatile unsigned int dma_bdbase; /* 0x14 */
94	volatile unsigned int dma_chact; /* 0x18 */
95	int res1; /* 0x1C */
96	volatile unsigned int bars[6]; /* 0x20 */
97	int res2[2]; /* 0x38 */
98	volatile unsigned int ahbmst_map[16]; /* 0x40 */
99	};
100
101	#define CTRL_BUS_BIT 16
102
103	#define CTRL_SI (1<<27)
104	#define CTRL_PE (1<<26)
105	#define CTRL_EI (1<<25)
106	#define CTRL_ER (1<<24)
107	#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
108	#define CTRL_HOSTINT 0xf
109
110	#define STS_HOST_BIT 31
111	#define STS_MST_BIT 30
112	#define STS_TAR_BIT 29
113	#define STS_DMA_BIT 28
114	#define STS_DI_BIT 27
115	#define STS_HI_BIT 26
116	#define STS_IRQMODE_BIT 24
117	#define STS_TRACE_BIT 23
118	#define STS_CFGERRVALID_BIT 20
119	#define STS_CFGERR_BIT 19
120	#define STS_INTTYPE_BIT 12
121	#define STS_INTSTS_BIT 8
122	#define STS_FDEPTH_BIT 2
123	#define STS_FNUM_BIT 0
124
125	#define STS_HOST (1<<STS_HOST_BIT)
126	#define STS_MST (1<<STS_MST_BIT)
127	#define STS_TAR (1<<STS_TAR_BIT)
128	#define STS_DMA (1<<STS_DMA_BIT)
129	#define STS_DI (1<<STS_DI_BIT)
130	#define STS_HI (1<<STS_HI_BIT)
131	#define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
132	#define STS_TRACE (1<<STS_TRACE_BIT)
133	#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
134	#define STS_CFGERR (1<<STS_CFGERR_BIT)
135	#define STS_INTTYPE (0x7f<<STS_INTTYPE_BIT)
136	#define STS_INTSTS (0xf<<STS_INTSTS_BIT)
137	#define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
138	#define STS_FNUM (0x3<<STS_FNUM_BIT)
139
140	#define STS_ITIMEOUT (1<<18)
141	#define STS_ISYSERR (1<<17)
142	#define STS_IDMA (1<<16)
143	#define STS_IDMAERR (1<<15)
144	#define STS_IMSTABRT (1<<14)
145	#define STS_ITGTABRT (1<<13)
146	#define STS_IPARERR (1<<12)
147
148	struct grpci2_bd_chan {
149	volatile unsigned int ctrl; /* 0x00 DMA Control */
150	volatile unsigned int nchan; /* 0x04 Next DMA Channel Address */
151	volatile unsigned int nbd; /* 0x08 Next Data Descriptor in channel */
152	volatile unsigned int res; /* 0x0C Reserved */
153	};
154
155	#define BD_CHAN_EN 0x80000000
156	#define BD_CHAN_TYPE 0x00300000
157	#define BD_CHAN_BDCNT 0x0000ffff
158	#define BD_CHAN_EN_BIT 31
159	#define BD_CHAN_TYPE_BIT 20
160	#define BD_CHAN_BDCNT_BIT 0
161
162	struct grpci2_bd_data {
163	volatile unsigned int ctrl; /* 0x00 DMA Data Control */
164	volatile unsigned int pci_adr; /* 0x04 PCI Start Address */
165	volatile unsigned int ahb_adr; /* 0x08 AHB Start address */
166	volatile unsigned int next; /* 0x0C Next Data Descriptor in channel */
167	};
168
169	#define BD_DATA_EN 0x80000000
170	#define BD_DATA_IE 0x40000000
171	#define BD_DATA_DR 0x20000000
172	#define BD_DATA_TYPE 0x00300000
173	#define BD_DATA_ER 0x00080000
174	#define BD_DATA_LEN 0x0000ffff
175	#define BD_DATA_EN_BIT 31
176	#define BD_DATA_IE_BIT 30
177	#define BD_DATA_DR_BIT 29
178	#define BD_DATA_TYPE_BIT 20
179	#define BD_DATA_ER_BIT 19
180	#define BD_DATA_LEN_BIT 0
181
182	/* GRPCI2 Capability */
183	struct grpci2_cap_first {
184	unsigned int ctrl;
185	unsigned int pci2ahb_map[6];
186	unsigned int ext2ahb_map;
187	unsigned int io_map;
188	unsigned int pcibar_size[6];
189	unsigned int ahb_pref;
190	};
191	#define CAP9_CTRL_OFS 0
192	#define CAP9_BAR_OFS 0x4
193	#define CAP9_IOMAP_OFS 0x20
194	#define CAP9_BARSIZE_OFS 0x24
195	#define CAP9_AHBPREF_OFS 0x3C
196
197	/* Used internally for accessing the PCI bridge's configuration space itself */
198	#define HOST_TGT PCI_DEV(0xff, 0, 0)
199
200	struct grpci2_priv *grpci2priv = NULL;
201
202	/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
203	* to a system interrupt number.
204	*/
205	unsigned char grpci2_pci_irq_table[4] =
206	{
207	/* INTA# */ GRPCI2_INTA_SYSIRQ,
208	/* INTB# */ GRPCI2_INTB_SYSIRQ,
209	/* INTC# */ GRPCI2_INTC_SYSIRQ,
210	/* INTD# */ GRPCI2_INTD_SYSIRQ
211	};
212
213	/* Start of workspace/dynamical area */
214	extern unsigned int _end;
215	#define DMA_START ((unsigned int) &_end)
216
217	/* Default BAR mapping, set BAR0 256MB 1:1 mapped base of CPU RAM */
218	struct grpci2_pcibar_cfg grpci2_default_bar_mapping[6] = {
219	/* BAR0 */ {DMA_START, DMA_START, 0x10000000},
220	/* BAR1 */ {0, 0, 0},
221	/* BAR2 */ {0, 0, 0},
222	/* BAR3 */ {0, 0, 0},
223	/* BAR4 */ {0, 0, 0},
224	/* BAR5 */ {0, 0, 0},
225	};
226
227	/* Driver private data struture */
228	struct grpci2_priv {
229	struct drvmgr_dev *dev;
230	struct grpci2_regs *regs;
231	unsigned char ver;
232	char irq;
233	char irq_mode; /* IRQ Mode from CAPSTS REG */
234	char bt_enabled;
235	unsigned int irq_mask;
236
237	struct grpci2_pcibar_cfg *barcfg;
238
239	unsigned int pci_area;
240	unsigned int pci_area_end;
241	unsigned int pci_io;
242	unsigned int pci_conf;
243	unsigned int pci_conf_end;
244
245	uint32_t devVend; /* Host PCI Device/Vendor ID */
246
247	struct drvmgr_map_entry maps_up[7];
248	struct drvmgr_map_entry maps_down[2];
249	struct pcibus_config config;
250	};
251
252	int grpci2_init1(struct drvmgr_dev *dev);
253	int grpci2_init3(struct drvmgr_dev *dev);
254	void grpci2_err_isr(void *arg);
255
256	/* GRPCI2 DRIVER */
257
258	struct drvmgr_drv_ops grpci2_ops =
259	{
260	.init = {grpci2_init1, NULL, grpci2_init3, NULL},
261	.remove = NULL,
262	.info = NULL
263	};
264
265	struct amba_dev_id grpci2_ids[] =
266	{
267	{VENDOR_GAISLER, GAISLER_GRPCI2},
268	{0, 0} /* Mark end of table */
269	};
270
271	struct amba_drv_info grpci2_info =
272	{
273	{
274	DRVMGR_OBJ_DRV, /* Driver */
275	NULL, /* Next driver */
276	NULL, /* Device list */
277	DRIVER_AMBAPP_GAISLER_GRPCI2_ID,/* Driver ID */
278	"GRPCI2_DRV", /* Driver Name */
279	DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
280	&grpci2_ops,
281	NULL, /* Funcs */
282	0, /* No devices yet */
283	sizeof(struct grpci2_priv), /* Make drvmgr alloc private */
284	},
285	&grpci2_ids[0]
286	};
287
288	void grpci2_register_drv(void)
289	{
290	DBG("Registering GRPCI2 driver\n");
291	drvmgr_drv_register(&grpci2_info.general);
292	}
293
294	static int grpci2_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val)
295	{
296	struct grpci2_priv *priv = grpci2priv;
297	volatile uint32_t *pci_conf;
298	unsigned int tmp, devfn;
299	IRQ_GLOBAL_PREPARE(oldLevel);
300	int retval, bus = PCI_DEV_BUS(dev);
301
302	if ((unsigned int)ofs & 0xffffff03) {
303	retval = PCISTS_EINVAL;
304	goto out2;
305	}
306
307	if (PCI_DEV_SLOT(dev) > 15) {
308	retval = PCISTS_MSTABRT;
309	goto out;
310	}
311
312	/* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
313	* we skip them.
314	*/
315	if (dev == HOST_TGT)
316	bus = devfn = 0;
317	else if (bus == 0)
318	devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
319	else
320	devfn = PCI_DEV_DEVFUNC(dev);
321
322	pci_conf = (volatile uint32_t *) (priv->pci_conf \| (devfn << 8) \| ofs);
323
324	IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
325
326	/* Select bus */
327	priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) \| (bus<<16);
328	/* clear old status */
329	priv->regs->sts_cap = (STS_CFGERR \| STS_CFGERRVALID);
330
331	tmp = *pci_conf;
332
333	/* Wait until GRPCI2 signals that CFG access is done, it should be
334	* done instantaneously unless a DMA operation is ongoing...
335	*/
336	while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
337	;
338
339	if (priv->regs->sts_cap & STS_CFGERR) {
340	retval = PCISTS_MSTABRT;
341	} else {
342	/* Bus always little endian (unaffected by byte-swapping) */
343	*val = CPU_swap_u32(tmp);
344	retval = PCISTS_OK;
345	}
346
347	IRQ_GLOBAL_ENABLE(oldLevel);
348
349	out:
350	if (retval != PCISTS_OK)
351	*val = 0xffffffff;
352
353	DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
354	PCI_DEV_EXPAND(dev), ofs, pci_conf, *val, retval);
355
356	out2:
357	return retval;
358	}
359
360	static int grpci2_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
361	{
362	uint32_t v;
363	int retval;
364
365	if (ofs & 1)
366	return PCISTS_EINVAL;
367
368	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
369	val = 0xffff & (v >> (8(ofs & 0x3)));
370
371	return retval;
372	}
373
374	static int grpci2_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
375	{
376	uint32_t v;
377	int retval;
378
379	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
380
381	val = 0xff & (v >> (8(ofs & 3)));
382
383	return retval;
384	}
385
386	static int grpci2_cfg_w32(pci_dev_t dev, int ofs, uint32_t val)
387	{
388	struct grpci2_priv *priv = grpci2priv;
389	volatile uint32_t *pci_conf;
390	uint32_t value, devfn;
391	int retval, bus = PCI_DEV_BUS(dev);
392	IRQ_GLOBAL_PREPARE(oldLevel);
393
394	if ((unsigned int)ofs & 0xffffff03)
395	return PCISTS_EINVAL;
396
397	if (PCI_DEV_SLOT(dev) > 15)
398	return PCISTS_MSTABRT;
399
400	value = CPU_swap_u32(val);
401
402	/* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
403	* we skip them.
404	*/
405	if (dev == HOST_TGT)
406	bus = devfn = 0;
407	else if (bus == 0)
408	devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
409	else
410	devfn = PCI_DEV_DEVFUNC(dev);
411
412	pci_conf = (volatile uint32_t *) (priv->pci_conf \| (devfn << 8) \| ofs);
413
414	IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
415
416	/* Select bus */
417	priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) \| (bus<<16);
418	/* clear old status */
419	priv->regs->sts_cap = (STS_CFGERR \| STS_CFGERRVALID);
420
421	*pci_conf = value;
422
423	/* Wait until GRPCI2 signals that CFG access is done, it should be
424	* done instantaneously unless a DMA operation is ongoing...
425	*/
426	while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
427	;
428
429	if (priv->regs->sts_cap & STS_CFGERR)
430	retval = PCISTS_MSTABRT;
431	else
432	retval = PCISTS_OK;
433
434	IRQ_GLOBAL_ENABLE(oldLevel);
435
436	DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
437	PCI_DEV_EXPAND(dev), ofs, pci_conf, value, retval);
438
439	return retval;
440	}
441
442	static int grpci2_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
443	{
444	uint32_t v;
445	int retval;
446
447	if (ofs & 1)
448	return PCISTS_EINVAL;
449
450	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
451	if (retval != PCISTS_OK)
452	return retval;
453
454	v = (v & ~(0xffff << (8(ofs&3)))) \| ((0xffff&val) << (8(ofs&3)));
455
456	return grpci2_cfg_w32(dev, ofs & ~0x3, v);
457	}
458
459	static int grpci2_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
460	{
461	uint32_t v;
462	int retval;
463
464	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
465	if (retval != PCISTS_OK)
466	return retval;
467
468	v = (v & ~(0xff << (8(ofs&3)))) \| ((0xff&val) << (8(ofs&3)));
469
470	return grpci2_cfg_w32(dev, ofs & ~0x3, v);
471	}
472
473	/* Return the assigned system IRQ number that corresponds to the PCI
474	* "Interrupt Pin" information from configuration space.
475	*
476	* The IRQ information is stored in the grpci2_pci_irq_table configurable
477	* by the user.
478	*
479	* Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
480	* 0xff if not assigned.
481	*/
482	static uint8_t grpci2_bus0_irq_map(pci_dev_t dev, int irq_pin)
483	{
484	uint8_t sysIrqNr = 0; /* not assigned */
485	int irq_group;
486
487	if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
488	/* Use default IRQ decoding on PCI BUS0 according slot numbering */
489	irq_group = PCI_DEV_SLOT(dev) & 0x3;
490	irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
491	/* Valid PCI "Interrupt Pin" number */
492	sysIrqNr = grpci2_pci_irq_table[irq_pin];
493	}
494	return sysIrqNr;
495	}
496
497	static int grpci2_translate(uint32_t *address, int type, int dir)
498	{
499	uint32_t adr, start, end;
500	struct grpci2_priv *priv = grpci2priv;
501	int i;
502
503	if (type == 1) {
504	/* I/O */
505	if (dir != 0) {
506	/* The PCI bus can not access the CPU bus from I/O
507	* because GRPCI2 core does not support I/O BARs
508	*/
509	return -1;
510	}
511
512	/* We have got a PCI IO BAR address that the CPU want to access.
513	* Check that it is within the PCI I/O window, I/O adresses
514	* are NOT mapped 1:1 with GRPCI2 driver... translation needed.
515	*/
516	adr = (uint32_t )address;
517	if (adr < 0x100 \|\| adr > 0x10000)
518	return -1;
519	*address = adr + priv->pci_io;
520	} else {
521	/* MEMIO and MEM.
522	* Memory space is mapped 1:1 so no translation is needed.
523	* Check that address is within accessible windows.
524	*/
525	adr = (uint32_t )address;
526	if (dir == 0) {
527	/* PCI BAR to AMBA-CPU address.. check that it is
528	* located within GRPCI2 PCI Memory Window
529	* adr = PCI address.
530	*/
531	if (adr < priv->pci_area \|\| adr >= priv->pci_area_end)
532	return -1;
533	} else {
534	/* We have a CPU address and want to get access to it
535	* from PCI space, typically when doing DMA into CPU
536	* RAM. The GRPCI2 core may have multiple target BARs
537	* that PCI masters can access, the BARs are user
538	* configurable in the following ways:
539	* BAR_SIZE, PCI_BAR Address and MAPPING (AMBA ADR)
540	*
541	* The below code tries to find a BAR for which the
542	* AMBA bar may have been mapped onto, and translate
543	* the AMBA-CPU address into a PCI address using the
544	* given mapping.
545	*
546	* adr = AMBA address.
547	*/
548	for(i=0; i<6; i++) {
549	start = priv->barcfg[i].ahbadr;
550	end = priv->barcfg[i].ahbadr +
551	priv->barcfg[i].barsize;
552	if (adr >= start && adr < end) {
553	/* BAR match: Translate address */
554	*address = (adr - start) +
555	priv->barcfg[i].pciadr;
556	return 0;
557	}
558	}
559	return -1;
560	}
561	}
562
563	return 0;
564	}
565
566	extern struct pci_memreg_ops pci_memreg_sparc_le_ops;
567	extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
568
569	/* GRPCI2 PCI access routines, default to Little-endian PCI Bus */
570	struct pci_access_drv grpci2_access_drv = {
571	.cfg =
572	{
573	grpci2_cfg_r8,
574	grpci2_cfg_r16,
575	grpci2_cfg_r32,
576	grpci2_cfg_w8,
577	grpci2_cfg_w16,
578	grpci2_cfg_w32,
579	},
580	.io =
581	{
582	_ld8,
583	_ld_le16,
584	_ld_le32,
585	_st8,
586	_st_le16,
587	_st_le32,
588	},
589	.memreg = &pci_memreg_sparc_le_ops,
590	.translate = grpci2_translate,
591	};
592
593	struct pci_io_ops grpci2_io_ops_be =
594	{
595	_ld8,
596	_ld_be16,
597	_ld_be32,
598	_st8,
599	_st_be16,
600	_st_be32,
601	};
602
603	/* PCI Error Interrupt handler, called when there may be a PCI Target/Master
604	* Abort.
605	*/
606	void grpci2_err_isr(void *arg)
607	{
608	struct grpci2_priv *priv = arg;
609	unsigned int sts = priv->regs->sts_cap;
610
611	if (sts & (STS_IMSTABRT \| STS_ITGTABRT \| STS_IPARERR \| STS_ISYSERR \| STS_ITIMEOUT)) {
612	/* A PCI error IRQ ... Error handler unimplemented
613	* add your code here...
614	*/
615	if (sts & STS_IMSTABRT) {
616	printk("GRPCI2: unhandled Master Abort IRQ\n");
617	}
618	if (sts & STS_ITGTABRT) {
619	printk("GRPCI2: unhandled Target Abort IRQ\n");
620	}
621	if (sts & STS_IPARERR) {
622	printk("GRPCI2: unhandled Parity Error IRQ\n");
623	}
624	if (sts & STS_ISYSERR) {
625	printk("GRPCI2: unhandled System Error IRQ\n");
626	}
627	if (sts & STS_ITIMEOUT) {
628	printk("GRPCI2: unhandled PCI target access timeout IRQ\n");
629	}
630	}
631	}
632
633	static int grpci2_hw_init(struct grpci2_priv *priv)
634	{
635	struct grpci2_regs *regs = priv->regs;
636	int i;
637	uint8_t capptr;
638	uint32_t data, io_map, ahbadr, pciadr, size;
639	pci_dev_t host = HOST_TGT;
640	struct grpci2_pcibar_cfg *barcfg = priv->barcfg;
641
642	/* Reset any earlier setup */
643	regs->ctrl = 0;
644	regs->sts_cap = ~0; /* Clear Status */
645	regs->dma_ctrl = 0;
646	regs->dma_bdbase = 0;
647
648	/* Translate I/O accesses 1:1, (will not work for PCI 2.3) */
649	regs->io_map = priv->pci_io & 0xffff0000;
650
651	/* set 1:1 mapping between AHB -> PCI memory space, for all Masters
652	* Each AHB master has it's own mapping registers. Max 16 AHB masters.
653	*/
654	for (i=0; i<16; i++)
655	regs->ahbmst_map[i] = priv->pci_area;
656
657	/* Get the GRPCI2 Host PCI ID */
658	grpci2_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
659
660	/* Get address to first (always defined) capability structure */
661	grpci2_cfg_r8(host, PCIR_CAP_PTR, &capptr);
662	if (capptr == 0)
663	return -1;
664
665	/* Limit the prefetch for GRPCI2 version 0. */
666	if (priv->ver == 0)
667	grpci2_cfg_w32(host, capptr+CAP9_AHBPREF_OFS, 0);
668
669	/* Enable/Disable Byte twisting */
670	grpci2_cfg_r32(host, capptr+CAP9_IOMAP_OFS, &io_map);
671	io_map = (io_map & ~0x1) \| (priv->bt_enabled ? 1 : 0);
672	grpci2_cfg_w32(host, capptr+CAP9_IOMAP_OFS, io_map);
673
674	/* Setup the Host's PCI Target BARs for others to access (DMA) */
675	for (i=0; i<6; i++) {
676	/* Make sure address is properly aligned */
677	size = ~(barcfg[i].barsize-1);
678	barcfg[i].pciadr &= size;
679	barcfg[i].ahbadr &= size;
680
681	pciadr = barcfg[i].pciadr;
682	ahbadr = barcfg[i].ahbadr;
683	size \|= PCIM_BAR_MEM_PREFETCH;
684
685	grpci2_cfg_w32(host, capptr+CAP9_BARSIZE_OFS+i*4, size);
686	grpci2_cfg_w32(host, capptr+CAP9_BAR_OFS+i*4, ahbadr);
687	grpci2_cfg_w32(host, PCIR_BAR(0)+i*4, pciadr);
688	}
689
690	/* set as bus master and enable pci memory responses */
691	grpci2_cfg_r32(host, PCIR_COMMAND, &data);
692	data \|= (PCIM_CMD_MEMEN \| PCIM_CMD_BUSMASTEREN);
693	grpci2_cfg_w32(host, PCIR_COMMAND, data);
694
695	/* Enable Error respone (CPU-TRAP) on illegal memory access */
696	regs->ctrl = CTRL_ER \| CTRL_PE;
697
698	/* Successful */
699	return 0;
700	}
701
702	/* Initializes the GRPCI2 core and driver, must be called before calling
703	* init_pci()
704	*
705	* Return values
706	* 0 Successful initalization
707	* -1 Error during initialization, for example "PCI core not found".
708	* -2 Error PCI controller not HOST (targets not supported)
709	* -3 Error due to GRPCI2 hardware initialization
710	*/
711	static int grpci2_init(struct grpci2_priv *priv)
712	{
713	struct ambapp_apb_info *apb;
714	struct ambapp_ahb_info *ahb;
715	int pin, i, j;
716	union drvmgr_key_value *value;
717	char keyname[6];
718	struct amba_dev_info *ainfo = priv->dev->businfo;
719	struct grpci2_pcibar_cfg *barcfg;
720	unsigned int size;
721
722	/* Find PCI core from Plug&Play information */
723	apb = ainfo->info.apb_slv;
724	ahb = ainfo->info.ahb_slv;
725
726	/* Found PCI core, init private structure */
727	priv->irq = apb->irq;
728	priv->ver = apb->ver;
729	priv->regs = (struct grpci2_regs *)apb->start;
730	priv->bt_enabled = DEFAULT_BT_ENABLED;
731	priv->irq_mode = (priv->regs->sts_cap & STS_IRQMODE) >> STS_IRQMODE_BIT;
732
733	/* Calculate the PCI windows
734	* AMBA->PCI Window: AHB SLAVE AREA0
735	* AMBA->PCI I/O cycles Window: AHB SLAVE AREA1 Lower half
736	* AMBA->PCI Configuration cycles Window: AHB SLAVE AREA1 Upper half
737	*/
738	priv->pci_area = ahb->start[0];
739	priv->pci_area_end = ahb->start[0] + ahb->mask[0];
740	priv->pci_io = ahb->start[1];
741	priv->pci_conf = ahb->start[1] + 0x10000;
742	priv->pci_conf_end = priv->pci_conf + 0x10000;
743
744	/* On systems where PCI I/O area and configuration area is apart of the
745	* "PCI Window" the PCI Window stops at the start of the PCI I/O area
746	*/
747	if ((priv->pci_io > priv->pci_area) &&
748	(priv->pci_io < (priv->pci_area_end-1))) {
749	priv->pci_area_end = priv->pci_io;
750	}
751
752	/* Init PCI interrupt assignment table to all use the interrupt routed
753	* through the GRPCI2 core.
754	*/
755	strcpy(keyname, "INTX#");
756	for (pin=1; pin<5; pin++) {
757	if (grpci2_pci_irq_table[pin-1] == 0xff) {
758	if (priv->irq_mode < 2) {
759	/* PCI Interrupts are shared */
760	grpci2_pci_irq_table[pin-1] = priv->irq;
761	} else {
762	/* Unique IRQ per PCI INT Pin */
763	grpci2_pci_irq_table[pin-1] = priv->irq + pin-1;
764	}
765
766	/* User may override Both hardcoded IRQ setup and Plug & Play IRQ */
767	keyname[3] = 'A' + (pin-1);
768	value = drvmgr_dev_key_get(priv->dev, keyname, DRVMGR_KT_INT);
769	if (value)
770	grpci2_pci_irq_table[pin-1] = value->i;
771	}
772
773	/* Remember which IRQs are enabled */
774	if (grpci2_pci_irq_table[pin-1] != 0)
775	priv->irq_mask \|= 1 << (pin-1);
776	}
777
778	/* User may override DEFAULT_BT_ENABLED to enable/disable byte twisting */
779	value = drvmgr_dev_key_get(priv->dev, "byteTwisting", DRVMGR_KT_INT);
780	if (value)
781	priv->bt_enabled = value->i;
782
783	/* Let user Configure the 6 target BARs */
784	value = drvmgr_dev_key_get(priv->dev, "tgtBarCfg", DRVMGR_KT_POINTER);
785	if (value)
786	priv->barcfg = value->ptr;
787	else
788	priv->barcfg = grpci2_default_bar_mapping;
789
790	/* This driver only support HOST systems, we check that it can act as a
791	* PCI Master and that it is in the Host slot. */
792	if ((priv->regs->sts_cap&STS_HOST) \|\| !(priv->regs->sts_cap&STS_MST))
793	return -2; /* Target not supported */
794
795	/* Init the PCI Core */
796	if (grpci2_hw_init(priv))
797	return -3;
798
799	/* Down streams translation table */
800	priv->maps_down[0].name = "AMBA -> PCI MEM Window";
801	priv->maps_down[0].size = priv->pci_area_end - priv->pci_area;
802	priv->maps_down[0].from_adr = (void *)priv->pci_area;
803	priv->maps_down[0].to_adr = (void *)priv->pci_area;
804	/* End table */
805	priv->maps_down[1].size = 0;
806
807	/* Up streams translation table */
808	/* Setup the Host's PCI Target BARs for others to access (DMA) */
809	barcfg = priv->barcfg;
810	for (i=0,j=0; i<6; i++) {
811	size = barcfg[i].barsize;
812	if (size == 0)
813	continue;
814
815	/* Make sure address is properly aligned */
816	priv->maps_up[j].name = "Target BAR[I] -> AMBA";
817	priv->maps_up[j].size = size;
818	priv->maps_up[j].from_adr = (void *)
819	(barcfg[i].pciadr & ~(size - 1));
820	priv->maps_up[j].to_adr = (void *)
821	(barcfg[i].ahbadr & ~(size - 1));
822	j++;
823	}
824
825	/* End table */
826	priv->maps_up[j].size = 0;
827
828	return 0;
829	}
830
831	/* Called when a core is found with the AMBA device and vendor ID
832	* given in grpci2_ids[]. IRQ, Console does not work here
833	*/
834	int grpci2_init1(struct drvmgr_dev *dev)
835	{
836	int status;
837	struct grpci2_priv *priv;
838	struct pci_auto_setup grpci2_auto_cfg;
839
840	DBG("GRPCI2[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
841
842	if (grpci2priv) {
843	DBG("Driver only supports one PCI core\n");
844	return DRVMGR_FAIL;
845	}
846
847	if ((strcmp(dev->parent->dev->drv->name, "AMBAPP_GRLIB_DRV") != 0) &&
848	(strcmp(dev->parent->dev->drv->name, "AMBAPP_LEON2_DRV") != 0)) {
849	/* We only support GRPCI2 driver on local bus */
850	return DRVMGR_FAIL;
851	}
852
853	priv = dev->priv;
854	if (!priv)
855	return DRVMGR_NOMEM;
856
857	priv->dev = dev;
858	grpci2priv = priv;
859
860	/* Initialize GRPCI2 Hardware */
861	status = grpci2_init(priv);
862	if (status) {
863	printf("Failed to initialize grpci2 driver %d\n", status);
864	return -1;
865	}
866
867	/* Register the PCI core at the PCI layers */
868
869	if (priv->bt_enabled == 0) {
870	/* Host is Big-Endian */
871	pci_endian = PCI_BIG_ENDIAN;
872
873	memcpy(&grpci2_access_drv.io, &grpci2_io_ops_be,
874	sizeof(grpci2_io_ops_be));
875	grpci2_access_drv.memreg = &pci_memreg_sparc_be_ops;
876	}
877
878	if (pci_access_drv_register(&grpci2_access_drv)) {
879	/* Access routines registration failed */
880	return DRVMGR_FAIL;
881	}
882
883	/* Prepare memory MAP */
884	grpci2_auto_cfg.options = 0;
885	grpci2_auto_cfg.mem_start = 0;
886	grpci2_auto_cfg.mem_size = 0;
887	grpci2_auto_cfg.memio_start = priv->pci_area;
888	grpci2_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area;
889	grpci2_auto_cfg.io_start = 0x100; /* avoid PCI address 0 */
890	grpci2_auto_cfg.io_size = 0x10000 - 0x100; /* lower 64kB I/O 16 */
891	grpci2_auto_cfg.irq_map = grpci2_bus0_irq_map;
892	grpci2_auto_cfg.irq_route = NULL; /* use standard routing */
893	pci_config_register(&grpci2_auto_cfg);
894
895	if (pci_config_init()) {
896	/* PCI configuration failed */
897	return DRVMGR_FAIL;
898	}
899
900	/* Initialize/Register Driver Manager PCI Bus */
901	priv->config.maps_down = &priv->maps_down[0];
902	priv->config.maps_up = &priv->maps_up[0];
903	return pcibus_register(dev, &priv->config);
904	}
905
906	int grpci2_init3(struct drvmgr_dev *dev)
907	{
908	struct grpci2_priv *priv = dev->priv;
909
910	/* Install and Enable PCI Error interrupt handler */
911	drvmgr_interrupt_register(dev, 0, "grpci2", grpci2_err_isr, priv);
912
913	/* Unmask Error IRQ and all PCI interrupts at PCI Core. For this to be
914	* safe every PCI board have to be resetted (no IRQ generation) before
915	* Global IRQs are enabled (Init is reached or similar)
916	*/
917	priv->regs->ctrl \|= (CTRL_EI \| priv->irq_mask);
918
919	return DRVMGR_OK;
920	}

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