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source: rtems/c/src/lib/libbsp/sparc/shared/pci/grpci2.c @ 6657a3d

4.115

Last change on this file since 6657a3d was 6657a3d, checked in by Daniel Hellstrom <daniel@…>, on 02/10/15 at 15:33:16
LEON: GRPCI2 driver warning fixes
Property mode set to `100644`
File size: 24.1 KB

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1	/* GRLIB GRPCI2 PCI HOST driver.
2	*
3	* COPYRIGHT (c) 2011
4	* Cobham Gaisler AB.
5	*
6	* The license and distribution terms for this file may be
7	* found in found in the file LICENSE in this distribution or at
8	* http://www.rtems.com/license/LICENSE.
9	*/
10
11	/* Configures the GRPCI2 core and initialize,
12	* - the PCI Library (pci.c)
13	* - the general part of the PCI Bus driver (pci_bus.c)
14	*
15	* System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
16	* default taken from Plug and Play, but may be overridden by the
17	* driver resources INTA#..INTD#. GRPCI2 handles differently depending
18	* on the design (4 different ways).
19	*
20	* GRPCI2 IRQ implementation notes
21	* -------------------------------
22	* Since the Driver Manager pci_bus layer implements IRQ by calling
23	* pci_interrupt_* which translates into BSP_shared_interrupt_*, and the
24	* root-bus also relies on BSP_shared_interrupt_*, it is safe for the GRPCI2
25	* driver to use the drvmgr_interrupt_* routines since they will be
26	* accessing the same routines in the end. Otherwise the GRPCI2 driver must
27	* have used the pci_interrupt_* routines.
28	*/
29
30	#include <stdlib.h>
31	#include <stdio.h>
32	#include <string.h>
33	#include <rtems/bspIo.h>
34	#include <libcpu/byteorder.h>
35	#include <libcpu/access.h>
36	#include <pci.h>
37	#include <pci/cfg.h>
38
39	#include <drvmgr/drvmgr.h>
40	#include <drvmgr/ambapp_bus.h>
41	#include <ambapp.h>
42	#include <drvmgr/pci_bus.h>
43	#include <grpci2.h>
44
45	#ifndef IRQ_GLOBAL_PREPARE
46	#define IRQ_GLOBAL_PREPARE(level) rtems_interrupt_level level
47	#endif
48
49	#ifndef IRQ_GLOBAL_DISABLE
50	#define IRQ_GLOBAL_DISABLE(level) rtems_interrupt_disable(level)
51	#endif
52
53	#ifndef IRQ_GLOBAL_ENABLE
54	#define IRQ_GLOBAL_ENABLE(level) rtems_interrupt_enable(level)
55	#endif
56
57	/* If defined to 1 - byte twisting is enabled by default */
58	#define DEFAULT_BT_ENABLED 0
59
60	/* Interrupt assignment. Set to other value than 0xff in order to
61	* override defaults and plug&play information
62	*/
63	#ifndef GRPCI2_INTA_SYSIRQ
64	#define GRPCI2_INTA_SYSIRQ 0xff
65	#endif
66	#ifndef GRPCI2_INTB_SYSIRQ
67	#define GRPCI2_INTB_SYSIRQ 0xff
68	#endif
69	#ifndef GRPCI2_INTC_SYSIRQ
70	#define GRPCI2_INTC_SYSIRQ 0xff
71	#endif
72	#ifndef GRPCI2_INTD_SYSIRQ
73	#define GRPCI2_INTD_SYSIRQ 0xff
74	#endif
75
76	/#define DEBUG 1/
77
78	#ifdef DEBUG
79	#define DBG(x...) printk(x)
80	#else
81	#define DBG(x...)
82	#endif
83
84	#define PCI_INVALID_VENDORDEVICEID 0xffffffff
85	#define PCI_MULTI_FUNCTION 0x80
86
87	/*
88	* GRPCI2 APB Register MAP
89	*/
90	struct grpci2_regs {
91	volatile unsigned int ctrl; /* 0x00 */
92	volatile unsigned int sts_cap; /* 0x04 */
93	volatile unsigned int ppref; /* 0x08 */
94	volatile unsigned int io_map; /* 0x0C */
95	volatile unsigned int dma_ctrl; /* 0x10 */
96	volatile unsigned int dma_bdbase; /* 0x14 */
97	volatile unsigned int dma_chact; /* 0x18 */
98	int res1; /* 0x1C */
99	volatile unsigned int bars[6]; /* 0x20 */
100	int res2[2]; /* 0x38 */
101	volatile unsigned int ahbmst_map[16]; /* 0x40 */
102	};
103
104	#define CTRL_BUS_BIT 16
105
106	#define CTRL_SI (1<<27)
107	#define CTRL_PE (1<<26)
108	#define CTRL_EI (1<<25)
109	#define CTRL_ER (1<<24)
110	#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
111	#define CTRL_HOSTINT 0xf
112
113	#define STS_HOST_BIT 31
114	#define STS_MST_BIT 30
115	#define STS_TAR_BIT 29
116	#define STS_DMA_BIT 28
117	#define STS_DI_BIT 27
118	#define STS_HI_BIT 26
119	#define STS_IRQMODE_BIT 24
120	#define STS_TRACE_BIT 23
121	#define STS_CFGERRVALID_BIT 20
122	#define STS_CFGERR_BIT 19
123	#define STS_INTTYPE_BIT 12
124	#define STS_INTSTS_BIT 8
125	#define STS_FDEPTH_BIT 2
126	#define STS_FNUM_BIT 0
127
128	#define STS_HOST (1<<STS_HOST_BIT)
129	#define STS_MST (1<<STS_MST_BIT)
130	#define STS_TAR (1<<STS_TAR_BIT)
131	#define STS_DMA (1<<STS_DMA_BIT)
132	#define STS_DI (1<<STS_DI_BIT)
133	#define STS_HI (1<<STS_HI_BIT)
134	#define STS_IRQMODE (0x3<<STS_IRQMODE_BIT)
135	#define STS_TRACE (1<<STS_TRACE_BIT)
136	#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
137	#define STS_CFGERR (1<<STS_CFGERR_BIT)
138	#define STS_INTTYPE (0x3f<<STS_INTTYPE_BIT)
139	#define STS_INTSTS (0xf<<STS_INTSTS_BIT)
140	#define STS_FDEPTH (0x7<<STS_FDEPTH_BIT)
141	#define STS_FNUM (0x3<<STS_FNUM_BIT)
142
143	#define STS_ISYSERR (1<<17)
144	#define STS_IDMA (1<<16)
145	#define STS_IDMAERR (1<<15)
146	#define STS_IMSTABRT (1<<14)
147	#define STS_ITGTABRT (1<<13)
148	#define STS_IPARERR (1<<12)
149
150	struct grpci2_bd_chan {
151	volatile unsigned int ctrl; /* 0x00 DMA Control */
152	volatile unsigned int nchan; /* 0x04 Next DMA Channel Address */
153	volatile unsigned int nbd; /* 0x08 Next Data Descriptor in channel */
154	volatile unsigned int res; /* 0x0C Reserved */
155	};
156
157	#define BD_CHAN_EN 0x80000000
158	#define BD_CHAN_TYPE 0x00300000
159	#define BD_CHAN_BDCNT 0x0000ffff
160	#define BD_CHAN_EN_BIT 31
161	#define BD_CHAN_TYPE_BIT 20
162	#define BD_CHAN_BDCNT_BIT 0
163
164	struct grpci2_bd_data {
165	volatile unsigned int ctrl; /* 0x00 DMA Data Control */
166	volatile unsigned int pci_adr; /* 0x04 PCI Start Address */
167	volatile unsigned int ahb_adr; /* 0x08 AHB Start address */
168	volatile unsigned int next; /* 0x0C Next Data Descriptor in channel */
169	};
170
171	#define BD_DATA_EN 0x80000000
172	#define BD_DATA_IE 0x40000000
173	#define BD_DATA_DR 0x20000000
174	#define BD_DATA_TYPE 0x00300000
175	#define BD_DATA_ER 0x00080000
176	#define BD_DATA_LEN 0x0000ffff
177	#define BD_DATA_EN_BIT 31
178	#define BD_DATA_IE_BIT 30
179	#define BD_DATA_DR_BIT 29
180	#define BD_DATA_TYPE_BIT 20
181	#define BD_DATA_ER_BIT 19
182	#define BD_DATA_LEN_BIT 0
183
184	/* GRPCI2 Capability */
185	struct grpci2_cap_first {
186	unsigned int ctrl;
187	unsigned int pci2ahb_map[6];
188	unsigned int ext2ahb_map;
189	unsigned int io_map;
190	unsigned int pcibar_size[6];
191	unsigned int ahb_pref;
192	};
193	#define CAP9_CTRL_OFS 0
194	#define CAP9_BAR_OFS 0x4
195	#define CAP9_IOMAP_OFS 0x20
196	#define CAP9_BARSIZE_OFS 0x24
197	#define CAP9_AHBPREF_OFS 0x3C
198
199	/* Used internally for accessing the PCI bridge's configuration space itself */
200	#define HOST_TGT PCI_DEV(0xff, 0, 0)
201
202	struct grpci2_priv *grpci2priv = NULL;
203
204	/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
205	* to a system interrupt number.
206	*/
207	unsigned char grpci2_pci_irq_table[4] =
208	{
209	/* INTA# */ GRPCI2_INTA_SYSIRQ,
210	/* INTB# */ GRPCI2_INTB_SYSIRQ,
211	/* INTC# */ GRPCI2_INTC_SYSIRQ,
212	/* INTD# */ GRPCI2_INTD_SYSIRQ
213	};
214
215	/* Start of workspace/dynamical area */
216	extern unsigned int _end;
217	#define DMA_START ((unsigned int) &_end)
218
219	/* Default BAR mapping, set BAR0 256MB 1:1 mapped base of CPU RAM */
220	struct grpci2_pcibar_cfg grpci2_default_bar_mapping[6] = {
221	/* BAR0 */ {DMA_START, DMA_START, 0x10000000},
222	/* BAR1 */ {0, 0, 0},
223	/* BAR2 */ {0, 0, 0},
224	/* BAR3 */ {0, 0, 0},
225	/* BAR4 */ {0, 0, 0},
226	/* BAR5 */ {0, 0, 0},
227	};
228
229	/* Driver private data struture */
230	struct grpci2_priv {
231	struct drvmgr_dev *dev;
232	struct grpci2_regs *regs;
233	unsigned char ver;
234	char irq;
235	char irq_mode; /* IRQ Mode from CAPSTS REG */
236	char bt_enabled;
237	unsigned int irq_mask;
238
239	struct grpci2_pcibar_cfg *barcfg;
240
241	unsigned int pci_area;
242	unsigned int pci_area_end;
243	unsigned int pci_io;
244	unsigned int pci_conf;
245	unsigned int pci_conf_end;
246
247	uint32_t devVend; /* Host PCI Device/Vendor ID */
248
249	struct drvmgr_map_entry maps_up[7];
250	struct drvmgr_map_entry maps_down[2];
251	struct pcibus_config config;
252	};
253
254	int grpci2_init1(struct drvmgr_dev *dev);
255	int grpci2_init3(struct drvmgr_dev *dev);
256	void grpci2_err_isr(void *arg);
257
258	/* GRPCI2 DRIVER */
259
260	struct drvmgr_drv_ops grpci2_ops =
261	{
262	.init = {grpci2_init1, NULL, grpci2_init3, NULL},
263	.remove = NULL,
264	.info = NULL
265	};
266
267	struct amba_dev_id grpci2_ids[] =
268	{
269	{VENDOR_GAISLER, GAISLER_GRPCI2},
270	{0, 0} /* Mark end of table */
271	};
272
273	struct amba_drv_info grpci2_info =
274	{
275	{
276	DRVMGR_OBJ_DRV, /* Driver */
277	NULL, /* Next driver */
278	NULL, /* Device list */
279	DRIVER_AMBAPP_GAISLER_GRPCI2_ID,/* Driver ID */
280	"GRPCI2_DRV", /* Driver Name */
281	DRVMGR_BUS_TYPE_AMBAPP, /* Bus Type */
282	&grpci2_ops,
283	NULL, /* Funcs */
284	0, /* No devices yet */
285	sizeof(struct grpci2_priv), /* Make drvmgr alloc private */
286	},
287	&grpci2_ids[0]
288	};
289
290	void grpci2_register_drv(void)
291	{
292	DBG("Registering GRPCI2 driver\n");
293	drvmgr_drv_register(&grpci2_info.general);
294	}
295
296	static int grpci2_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val)
297	{
298	struct grpci2_priv *priv = grpci2priv;
299	volatile uint32_t *pci_conf;
300	unsigned int tmp, devfn;
301	IRQ_GLOBAL_PREPARE(oldLevel);
302	int retval, bus = PCI_DEV_BUS(dev);
303
304	if ((unsigned int)ofs & 0xffffff03) {
305	retval = PCISTS_EINVAL;
306	goto out2;
307	}
308
309	if (PCI_DEV_SLOT(dev) > 15) {
310	retval = PCISTS_MSTABRT;
311	goto out;
312	}
313
314	/* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
315	* we skip them.
316	*/
317	if (dev == HOST_TGT)
318	bus = devfn = 0;
319	else if (bus == 0)
320	devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
321	else
322	devfn = PCI_DEV_DEVFUNC(dev);
323
324	pci_conf = (volatile uint32_t *) (priv->pci_conf \| (devfn << 8) \| ofs);
325
326	IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
327
328	/* Select bus */
329	priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) \| (bus<<16);
330	/* clear old status */
331	priv->regs->sts_cap = (STS_CFGERR \| STS_CFGERRVALID);
332
333	tmp = *pci_conf;
334
335	/* Wait until GRPCI2 signals that CFG access is done, it should be
336	* done instantaneously unless a DMA operation is ongoing...
337	*/
338	while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
339	;
340
341	if (priv->regs->sts_cap & STS_CFGERR) {
342	retval = PCISTS_MSTABRT;
343	} else {
344	/* Bus always little endian (unaffected by byte-swapping) */
345	*val = CPU_swap_u32(tmp);
346	retval = PCISTS_OK;
347	}
348
349	IRQ_GLOBAL_ENABLE(oldLevel);
350
351	out:
352	if (retval != PCISTS_OK)
353	*val = 0xffffffff;
354
355	DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
356	PCI_DEV_EXPAND(dev), ofs, pci_conf, *val, retval);
357
358	out2:
359	return retval;
360	}
361
362	static int grpci2_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
363	{
364	uint32_t v;
365	int retval;
366
367	if (ofs & 1)
368	return PCISTS_EINVAL;
369
370	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
371	val = 0xffff & (v >> (8(ofs & 0x3)));
372
373	return retval;
374	}
375
376	static int grpci2_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
377	{
378	uint32_t v;
379	int retval;
380
381	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
382
383	val = 0xff & (v >> (8(ofs & 3)));
384
385	return retval;
386	}
387
388	static int grpci2_cfg_w32(pci_dev_t dev, int ofs, uint32_t val)
389	{
390	struct grpci2_priv *priv = grpci2priv;
391	volatile uint32_t *pci_conf;
392	uint32_t value, devfn;
393	int retval, bus = PCI_DEV_BUS(dev);
394	IRQ_GLOBAL_PREPARE(oldLevel);
395
396	if ((unsigned int)ofs & 0xffffff03)
397	return PCISTS_EINVAL;
398
399	if (PCI_DEV_SLOT(dev) > 15)
400	return PCISTS_MSTABRT;
401
402	value = CPU_swap_u32(val);
403
404	/* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
405	* we skip them.
406	*/
407	if (dev == HOST_TGT)
408	bus = devfn = 0;
409	else if (bus == 0)
410	devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
411	else
412	devfn = PCI_DEV_DEVFUNC(dev);
413
414	pci_conf = (volatile uint32_t *) (priv->pci_conf \| (devfn << 8) \| ofs);
415
416	IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
417
418	/* Select bus */
419	priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) \| (bus<<16);
420	/* clear old status */
421	priv->regs->sts_cap = (STS_CFGERR \| STS_CFGERRVALID);
422
423	*pci_conf = value;
424
425	/* Wait until GRPCI2 signals that CFG access is done, it should be
426	* done instantaneously unless a DMA operation is ongoing...
427	*/
428	while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
429	;
430
431	if (priv->regs->sts_cap & STS_CFGERR)
432	retval = PCISTS_MSTABRT;
433	else
434	retval = PCISTS_OK;
435
436	IRQ_GLOBAL_ENABLE(oldLevel);
437
438	DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x (%d)\n",
439	PCI_DEV_EXPAND(dev), ofs, pci_conf, value, retval);
440
441	return retval;
442	}
443
444	static int grpci2_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
445	{
446	uint32_t v;
447	int retval;
448
449	if (ofs & 1)
450	return PCISTS_EINVAL;
451
452	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
453	if (retval != PCISTS_OK)
454	return retval;
455
456	v = (v & ~(0xffff << (8(ofs&3)))) \| ((0xffff&val) << (8(ofs&3)));
457
458	return grpci2_cfg_w32(dev, ofs & ~0x3, v);
459	}
460
461	static int grpci2_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
462	{
463	uint32_t v;
464	int retval;
465
466	retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
467	if (retval != PCISTS_OK)
468	return retval;
469
470	v = (v & ~(0xff << (8(ofs&3)))) \| ((0xff&val) << (8(ofs&3)));
471
472	return grpci2_cfg_w32(dev, ofs & ~0x3, v);
473	}
474
475	/* Return the assigned system IRQ number that corresponds to the PCI
476	* "Interrupt Pin" information from configuration space.
477	*
478	* The IRQ information is stored in the grpci2_pci_irq_table configurable
479	* by the user.
480	*
481	* Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
482	* 0xff if not assigned.
483	*/
484	static uint8_t grpci2_bus0_irq_map(pci_dev_t dev, int irq_pin)
485	{
486	uint8_t sysIrqNr = 0; /* not assigned */
487	int irq_group;
488
489	if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
490	/* Use default IRQ decoding on PCI BUS0 according slot numbering */
491	irq_group = PCI_DEV_SLOT(dev) & 0x3;
492	irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
493	/* Valid PCI "Interrupt Pin" number */
494	sysIrqNr = grpci2_pci_irq_table[irq_pin];
495	}
496	return sysIrqNr;
497	}
498
499	static int grpci2_translate(uint32_t *address, int type, int dir)
500	{
501	uint32_t adr, start, end;
502	struct grpci2_priv *priv = grpci2priv;
503	int i;
504
505	if (type == 1) {
506	/* I/O */
507	if (dir != 0) {
508	/* The PCI bus can not access the CPU bus from I/O
509	* because GRPCI2 core does not support I/O BARs
510	*/
511	return -1;
512	}
513
514	/* We have got a PCI IO BAR address that the CPU want to access.
515	* Check that it is within the PCI I/O window, I/O adresses
516	* are NOT mapped 1:1 with GRPCI2 driver... translation needed.
517	*/
518	adr = (uint32_t )address;
519	if (adr < 0x100 \|\| adr > 0x10000)
520	return -1;
521	*address = adr + priv->pci_io;
522	} else {
523	/* MEMIO and MEM.
524	* Memory space is mapped 1:1 so no translation is needed.
525	* Check that address is within accessible windows.
526	*/
527	adr = (uint32_t )address;
528	if (dir == 0) {
529	/* PCI BAR to AMBA-CPU address.. check that it is
530	* located within GRPCI2 PCI Memory Window
531	* adr = PCI address.
532	*/
533	if (adr < priv->pci_area \|\| adr >= priv->pci_area_end)
534	return -1;
535	} else {
536	/* We have a CPU address and want to get access to it
537	* from PCI space, typically when doing DMA into CPU
538	* RAM. The GRPCI2 core may have multiple target BARs
539	* that PCI masters can access, the BARs are user
540	* configurable in the following ways:
541	* BAR_SIZE, PCI_BAR Address and MAPPING (AMBA ADR)
542	*
543	* The below code tries to find a BAR for which the
544	* AMBA bar may have been mapped onto, and translate
545	* the AMBA-CPU address into a PCI address using the
546	* given mapping.
547	*
548	* adr = AMBA address.
549	*/
550	for(i=0; i<6; i++) {
551	start = priv->barcfg[i].ahbadr;
552	end = priv->barcfg[i].ahbadr +
553	priv->barcfg[i].barsize;
554	if (adr >= start && adr < end) {
555	/* BAR match: Translate address */
556	*address = (adr - start) +
557	priv->barcfg[i].pciadr;
558	return 0;
559	}
560	}
561	return -1;
562	}
563	}
564
565	return 0;
566	}
567
568	extern struct pci_memreg_ops pci_memreg_sparc_le_ops;
569	extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
570
571	/* GRPCI2 PCI access routines, default to Little-endian PCI Bus */
572	struct pci_access_drv grpci2_access_drv = {
573	.cfg =
574	{
575	grpci2_cfg_r8,
576	grpci2_cfg_r16,
577	grpci2_cfg_r32,
578	grpci2_cfg_w8,
579	grpci2_cfg_w16,
580	grpci2_cfg_w32,
581	},
582	.io =
583	{
584	_ld8,
585	_ld_le16,
586	_ld_le32,
587	_st8,
588	_st_le16,
589	_st_le32,
590	},
591	.memreg = &pci_memreg_sparc_le_ops,
592	.translate = grpci2_translate,
593	};
594
595	struct pci_io_ops grpci2_io_ops_be =
596	{
597	_ld8,
598	_ld_be16,
599	_ld_be32,
600	_st8,
601	_st_be16,
602	_st_be32,
603	};
604
605	/* PCI Error Interrupt handler, called when there may be a PCI Target/Master
606	* Abort.
607	*/
608	void grpci2_err_isr(void *arg)
609	{
610	struct grpci2_priv *priv = arg;
611	unsigned int sts = priv->regs->sts_cap;
612
613	if (sts & (STS_IMSTABRT \| STS_ITGTABRT \| STS_IPARERR \| STS_ISYSERR)) {
614	/* A PCI error IRQ ... Error handler unimplemented
615	* add your code here...
616	*/
617	if (sts & STS_IMSTABRT) {
618	printk("GRPCI2: unhandled Master Abort IRQ\n");
619	}
620	if (sts & STS_ITGTABRT) {
621	printk("GRPCI2: unhandled Target Abort IRQ\n");
622	}
623	if (sts & STS_IPARERR) {
624	printk("GRPCI2: unhandled Parity Error IRQ\n");
625	}
626	if (sts & STS_ISYSERR) {
627	printk("GRPCI2: unhandled System Error IRQ\n");
628	}
629	}
630	}
631
632	static int grpci2_hw_init(struct grpci2_priv *priv)
633	{
634	struct grpci2_regs *regs = priv->regs;
635	int i;
636	uint8_t capptr;
637	uint32_t data, io_map, ahbadr, pciadr, size;
638	pci_dev_t host = HOST_TGT;
639	struct grpci2_pcibar_cfg *barcfg = priv->barcfg;
640
641	/* Reset any earlier setup */
642	regs->ctrl = 0;
643	regs->sts_cap = ~0; /* Clear Status */
644	regs->dma_ctrl = 0;
645	regs->dma_bdbase = 0;
646
647	/* Translate I/O accesses 1:1, (will not work for PCI 2.3) */
648	regs->io_map = priv->pci_io & 0xffff0000;
649
650	/* set 1:1 mapping between AHB -> PCI memory space, for all Masters
651	* Each AHB master has it's own mapping registers. Max 16 AHB masters.
652	*/
653	for (i=0; i<16; i++)
654	regs->ahbmst_map[i] = priv->pci_area;
655
656	/* Get the GRPCI2 Host PCI ID */
657	grpci2_cfg_r32(host, PCI_VENDOR_ID, &priv->devVend);
658
659	/* Get address to first (always defined) capability structure */
660	grpci2_cfg_r8(host, PCI_CAP_PTR, &capptr);
661	if (capptr == 0)
662	return -1;
663
664	/* Limit the prefetch for GRPCI2 version 0. */
665	if (priv->ver == 0)
666	grpci2_cfg_w32(host, capptr+CAP9_AHBPREF_OFS, 0);
667
668	/* Enable/Disable Byte twisting */
669	grpci2_cfg_r32(host, capptr+CAP9_IOMAP_OFS, &io_map);
670	io_map = (io_map & ~0x1) \| (priv->bt_enabled ? 1 : 0);
671	grpci2_cfg_w32(host, capptr+CAP9_IOMAP_OFS, io_map);
672
673	/* Setup the Host's PCI Target BARs for others to access (DMA) */
674	for (i=0; i<6; i++) {
675	/* Make sure address is properly aligned */
676	size = ~(barcfg[i].barsize-1);
677	barcfg[i].pciadr &= size;
678	barcfg[i].ahbadr &= size;
679
680	pciadr = barcfg[i].pciadr;
681	ahbadr = barcfg[i].ahbadr;
682	size \|= PCI_BASE_ADDRESS_MEM_PREFETCH;
683
684	grpci2_cfg_w32(host, capptr+CAP9_BARSIZE_OFS+i*4, size);
685	grpci2_cfg_w32(host, capptr+CAP9_BAR_OFS+i*4, ahbadr);
686	grpci2_cfg_w32(host, PCI_BASE_ADDRESS_0+i*4, pciadr);
687	}
688
689	/* set as bus master and enable pci memory responses */
690	grpci2_cfg_r32(host, PCI_COMMAND, &data);
691	data \|= (PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
692	grpci2_cfg_w32(host, PCI_COMMAND, data);
693
694	/* Enable Error respone (CPU-TRAP) on illegal memory access */
695	regs->ctrl = CTRL_ER \| CTRL_PE;
696
697	/* Successful */
698	return 0;
699	}
700
701	/* Initializes the GRPCI2 core and driver, must be called before calling
702	* init_pci()
703	*
704	* Return values
705	* 0 Successful initalization
706	* -1 Error during initialization, for example "PCI core not found".
707	* -2 Error PCI controller not HOST (targets not supported)
708	* -3 Error due to GRPCI2 hardware initialization
709	*/
710	static int grpci2_init(struct grpci2_priv *priv)
711	{
712	struct ambapp_apb_info *apb;
713	struct ambapp_ahb_info *ahb;
714	int pin, i, j;
715	union drvmgr_key_value *value;
716	char keyname[6];
717	struct amba_dev_info *ainfo = priv->dev->businfo;
718	struct grpci2_pcibar_cfg *barcfg;
719	unsigned int size;
720
721	/* Find PCI core from Plug&Play information */
722	apb = ainfo->info.apb_slv;
723	ahb = ainfo->info.ahb_slv;
724
725	/* Found PCI core, init private structure */
726	priv->irq = apb->irq;
727	priv->ver = apb->ver;
728	priv->regs = (struct grpci2_regs *)apb->start;
729	priv->bt_enabled = DEFAULT_BT_ENABLED;
730	priv->irq_mode = (priv->regs->sts_cap & STS_IRQMODE) >> STS_IRQMODE_BIT;
731
732	/* Calculate the PCI windows
733	* AMBA->PCI Window: AHB SLAVE AREA0
734	* AMBA->PCI I/O cycles Window: AHB SLAVE AREA1 Lower half
735	* AMBA->PCI Configuration cycles Window: AHB SLAVE AREA1 Upper half
736	*/
737	priv->pci_area = ahb->start[0];
738	priv->pci_area_end = ahb->start[0] + ahb->mask[0];
739	priv->pci_io = ahb->start[1];
740	priv->pci_conf = ahb->start[1] + 0x10000;
741	priv->pci_conf_end = priv->pci_conf + 0x10000;
742
743	/* On systems where PCI I/O area and configuration area is apart of the
744	* "PCI Window" the PCI Window stops at the start of the PCI I/O area
745	*/
746	if ((priv->pci_io > priv->pci_area) &&
747	(priv->pci_io < (priv->pci_area_end-1))) {
748	priv->pci_area_end = priv->pci_io;
749	}
750
751	/* Init PCI interrupt assignment table to all use the interrupt routed
752	* through the GRPCI2 core.
753	*/
754	strcpy(keyname, "INTX#");
755	for (pin=1; pin<5; pin++) {
756	if (grpci2_pci_irq_table[pin-1] == 0xff) {
757	if (priv->irq_mode < 2) {
758	/* PCI Interrupts are shared */
759	grpci2_pci_irq_table[pin-1] = priv->irq;
760	} else {
761	/* Unique IRQ per PCI INT Pin */
762	grpci2_pci_irq_table[pin-1] = priv->irq + pin-1;
763	}
764
765	/* User may override Both hardcoded IRQ setup and Plug & Play IRQ */
766	keyname[3] = 'A' + (pin-1);
767	value = drvmgr_dev_key_get(priv->dev, keyname, KEY_TYPE_INT);
768	if (value)
769	grpci2_pci_irq_table[pin-1] = value->i;
770	}
771
772	/* Remember which IRQs are enabled */
773	if (grpci2_pci_irq_table[pin-1] != 0)
774	priv->irq_mask \|= 1 << (pin-1);
775	}
776
777	/* User may override DEFAULT_BT_ENABLED to enable/disable byte twisting */
778	value = drvmgr_dev_key_get(priv->dev, "byteTwisting", KEY_TYPE_INT);
779	if (value)
780	priv->bt_enabled = value->i;
781
782	/* Let user Configure the 6 target BARs */
783	value = drvmgr_dev_key_get(priv->dev, "tgtBarCfg", KEY_TYPE_POINTER);
784	if (value)
785	priv->barcfg = value->ptr;
786	else
787	priv->barcfg = grpci2_default_bar_mapping;
788
789	/* This driver only support HOST systems, we check that it can act as a
790	* PCI Master and that it is in the Host slot. */
791	if ((priv->regs->sts_cap&STS_HOST) \|\| !(priv->regs->sts_cap&STS_MST))
792	return -2; /* Target not supported */
793
794	/* Init the PCI Core */
795	if (grpci2_hw_init(priv))
796	return -3;
797
798	/* Down streams translation table */
799	priv->maps_down[0].name = "AMBA -> PCI MEM Window";
800	priv->maps_down[0].size = priv->pci_area_end - priv->pci_area;
801	priv->maps_down[0].from_adr = (void *)priv->pci_area;
802	priv->maps_down[0].to_adr = (void *)priv->pci_area;
803	/* End table */
804	priv->maps_down[1].size = 0;
805
806	/* Up streams translation table */
807	/* Setup the Host's PCI Target BARs for others to access (DMA) */
808	barcfg = priv->barcfg;
809	for (i=0,j=0; i<6; i++) {
810	size = barcfg[i].barsize;
811	if (size == 0)
812	continue;
813
814	/* Make sure address is properly aligned */
815	priv->maps_up[j].name = "Target BAR[I] -> AMBA";
816	priv->maps_up[j].size = size;
817	priv->maps_up[j].from_adr = (void *)
818	(barcfg[i].pciadr & ~(size - 1));
819	priv->maps_up[j].to_adr = (void *)
820	(barcfg[i].ahbadr & ~(size - 1));
821	j++;
822	}
823
824	/* End table */
825	priv->maps_up[j].size = 0;
826
827	return 0;
828	}
829
830	/* Called when a core is found with the AMBA device and vendor ID
831	* given in grpci2_ids[]. IRQ, Console does not work here
832	*/
833	int grpci2_init1(struct drvmgr_dev *dev)
834	{
835	int status;
836	struct grpci2_priv *priv;
837	struct pci_auto_setup grpci2_auto_cfg;
838
839	DBG("GRPCI2[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
840
841	if (grpci2priv) {
842	DBG("Driver only supports one PCI core\n");
843	return DRVMGR_FAIL;
844	}
845
846	if ((strcmp(dev->parent->dev->drv->name, "AMBAPP_GRLIB_DRV") != 0) &&
847	(strcmp(dev->parent->dev->drv->name, "AMBAPP_LEON2_DRV") != 0)) {
848	/* We only support GRPCI2 driver on local bus */
849	return DRVMGR_FAIL;
850	}
851
852	priv = dev->priv;
853	if (!priv)
854	return DRVMGR_NOMEM;
855
856	priv->dev = dev;
857	grpci2priv = priv;
858
859	/* Initialize GRPCI2 Hardware */
860	status = grpci2_init(priv);
861	if (status) {
862	printf("Failed to initialize grpci2 driver %d\n", status);
863	return -1;
864	}
865
866	/* Register the PCI core at the PCI layers */
867
868	if (priv->bt_enabled == 0) {
869	/* Host is Big-Endian */
870	pci_endian = PCI_BIG_ENDIAN;
871
872	memcpy(&grpci2_access_drv.io, &grpci2_io_ops_be,
873	sizeof(grpci2_io_ops_be));
874	grpci2_access_drv.memreg = &pci_memreg_sparc_be_ops;
875	}
876
877	if (pci_access_drv_register(&grpci2_access_drv)) {
878	/* Access routines registration failed */
879	return DRVMGR_FAIL;
880	}
881
882	/* Prepare memory MAP */
883	grpci2_auto_cfg.options = 0;
884	grpci2_auto_cfg.mem_start = 0;
885	grpci2_auto_cfg.mem_size = 0;
886	grpci2_auto_cfg.memio_start = priv->pci_area;
887	grpci2_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area;
888	grpci2_auto_cfg.io_start = 0x100; /* avoid PCI address 0 */
889	grpci2_auto_cfg.io_size = 0x10000 - 0x100; /* lower 64kB I/O 16 */
890	grpci2_auto_cfg.irq_map = grpci2_bus0_irq_map;
891	grpci2_auto_cfg.irq_route = NULL; /* use standard routing */
892	pci_config_register(&grpci2_auto_cfg);
893
894	if (pci_config_init()) {
895	/* PCI configuration failed */
896	return DRVMGR_FAIL;
897	}
898
899	/* Initialize/Register Driver Manager PCI Bus */
900	priv->config.maps_down = &priv->maps_down[0];
901	priv->config.maps_up = &priv->maps_up[0];
902	return pcibus_register(dev, &priv->config);
903	}
904
905	int grpci2_init3(struct drvmgr_dev *dev)
906	{
907	struct grpci2_priv *priv = dev->priv;
908
909	/* Install and Enable PCI Error interrupt handler */
910	drvmgr_interrupt_register(dev, 0, "grpci2", grpci2_err_isr, priv);
911
912	/* Unmask Error IRQ and all PCI interrupts at PCI Core. For this to be
913	* safe every PCI board have to be resetted (no IRQ generation) before
914	* Global IRQs are enabled (Init is reached or similar)
915	*/
916	priv->regs->ctrl \|= (CTRL_EI \| priv->irq_mask);
917
918	return DRVMGR_OK;
919	}

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