source: rtems/c/src/lib/libbsp/sparc/shared/pci/grpci2.c @ 4d3e70f4

4.115
Last change on this file since 4d3e70f4 was 4d3e70f4, checked in by Daniel Hellstrom <daniel@…>, on 04/13/15 at 09:26:52

DRVMGR: KEY_TYPE now a enum drvmgr_kt

  • Property mode set to 100644
File size: 24.0 KB
Line 
1/*  GRLIB GRPCI2 PCI HOST driver.
2 *
3 *  COPYRIGHT (c) 2011
4 *  Cobham Gaisler AB.
5 *
6 *  The license and distribution terms for this file may be
7 *  found in found in the file LICENSE in this distribution or at
8 *  http://www.rtems.org/license/LICENSE.
9 */
10
11/* Configures the GRPCI2 core and initialize,
12 *  - the PCI Library (pci.c)
13 *  - the general part of the PCI Bus driver (pci_bus.c)
14 * 
15 * System interrupt assigned to PCI interrupt (INTA#..INTD#) is by
16 * default taken from Plug and Play, but may be overridden by the
17 * driver resources INTA#..INTD#. GRPCI2 handles differently depending
18 * on the design (4 different ways).
19 *
20 * GRPCI2 IRQ implementation notes
21 * -------------------------------
22 * Since the Driver Manager pci_bus layer implements IRQ by calling
23 * pci_interrupt_* which translates into BSP_shared_interrupt_*, and the
24 * root-bus also relies on BSP_shared_interrupt_*, it is safe for the GRPCI2
25 * driver to use the drvmgr_interrupt_* routines since they will be
26 * accessing the same routines in the end. Otherwise the GRPCI2 driver must
27 * have used the pci_interrupt_* routines.
28 */
29
30#include <stdlib.h>
31#include <stdio.h>
32#include <string.h>
33#include <rtems/bspIo.h>
34#include <libcpu/byteorder.h>
35#include <libcpu/access.h>
36#include <pci.h>
37#include <pci/cfg.h>
38
39#include <drvmgr/drvmgr.h>
40#include <drvmgr/ambapp_bus.h>
41#include <ambapp.h>
42#include <drvmgr/pci_bus.h>
43#include <bsp/grpci2.h>
44
45#ifndef IRQ_GLOBAL_PREPARE
46 #define IRQ_GLOBAL_PREPARE(level) rtems_interrupt_level level
47#endif
48
49#ifndef IRQ_GLOBAL_DISABLE
50 #define IRQ_GLOBAL_DISABLE(level) rtems_interrupt_disable(level)
51#endif
52
53#ifndef IRQ_GLOBAL_ENABLE
54 #define IRQ_GLOBAL_ENABLE(level) rtems_interrupt_enable(level)
55#endif
56
57/* If defined to 1 - byte twisting is enabled by default */
58#define DEFAULT_BT_ENABLED 0
59
60/* Interrupt assignment. Set to other value than 0xff in order to
61 * override defaults and plug&play information
62 */
63#ifndef GRPCI2_INTA_SYSIRQ
64 #define GRPCI2_INTA_SYSIRQ 0xff
65#endif
66#ifndef GRPCI2_INTB_SYSIRQ
67 #define GRPCI2_INTB_SYSIRQ 0xff
68#endif
69#ifndef GRPCI2_INTC_SYSIRQ
70 #define GRPCI2_INTC_SYSIRQ 0xff
71#endif
72#ifndef GRPCI2_INTD_SYSIRQ
73 #define GRPCI2_INTD_SYSIRQ 0xff
74#endif
75
76/*#define DEBUG 1*/
77
78#ifdef DEBUG
79#define DBG(x...) printk(x)
80#else
81#define DBG(x...)
82#endif
83
84/*
85 * GRPCI2 APB Register MAP
86 */
87struct grpci2_regs {
88        volatile unsigned int ctrl;             /* 0x00 */
89        volatile unsigned int sts_cap;          /* 0x04 */
90        volatile unsigned int ppref;            /* 0x08 */
91        volatile unsigned int io_map;           /* 0x0C */
92        volatile unsigned int dma_ctrl;         /* 0x10 */
93        volatile unsigned int dma_bdbase;       /* 0x14 */
94        volatile unsigned int dma_chact;        /* 0x18 */
95        int res1;                               /* 0x1C */
96        volatile unsigned int bars[6];          /* 0x20 */
97        int res2[2];                            /* 0x38 */
98        volatile unsigned int ahbmst_map[16];   /* 0x40 */
99};
100
101#define CTRL_BUS_BIT 16
102
103#define CTRL_SI (1<<27)
104#define CTRL_PE (1<<26)
105#define CTRL_EI (1<<25)
106#define CTRL_ER (1<<24)
107#define CTRL_BUS (0xff<<CTRL_BUS_BIT)
108#define CTRL_HOSTINT 0xf
109
110#define STS_HOST_BIT    31
111#define STS_MST_BIT     30
112#define STS_TAR_BIT     29
113#define STS_DMA_BIT     28
114#define STS_DI_BIT      27
115#define STS_HI_BIT      26
116#define STS_IRQMODE_BIT 24
117#define STS_TRACE_BIT   23
118#define STS_CFGERRVALID_BIT 20
119#define STS_CFGERR_BIT  19
120#define STS_INTTYPE_BIT 12
121#define STS_INTSTS_BIT  8
122#define STS_FDEPTH_BIT  2
123#define STS_FNUM_BIT    0
124
125#define STS_HOST        (1<<STS_HOST_BIT)
126#define STS_MST         (1<<STS_MST_BIT)
127#define STS_TAR         (1<<STS_TAR_BIT)
128#define STS_DMA         (1<<STS_DMA_BIT)
129#define STS_DI          (1<<STS_DI_BIT)
130#define STS_HI          (1<<STS_HI_BIT)
131#define STS_IRQMODE     (0x3<<STS_IRQMODE_BIT)
132#define STS_TRACE       (1<<STS_TRACE_BIT)
133#define STS_CFGERRVALID (1<<STS_CFGERRVALID_BIT)
134#define STS_CFGERR      (1<<STS_CFGERR_BIT)
135#define STS_INTTYPE     (0x3f<<STS_INTTYPE_BIT)
136#define STS_INTSTS      (0xf<<STS_INTSTS_BIT)
137#define STS_FDEPTH      (0x7<<STS_FDEPTH_BIT)
138#define STS_FNUM        (0x3<<STS_FNUM_BIT)
139
140#define STS_ISYSERR     (1<<17)
141#define STS_IDMA        (1<<16)
142#define STS_IDMAERR     (1<<15)
143#define STS_IMSTABRT    (1<<14)
144#define STS_ITGTABRT    (1<<13)
145#define STS_IPARERR     (1<<12)
146
147struct grpci2_bd_chan {
148        volatile unsigned int ctrl;     /* 0x00 DMA Control */
149        volatile unsigned int nchan;    /* 0x04 Next DMA Channel Address */
150        volatile unsigned int nbd;      /* 0x08 Next Data Descriptor in channel */
151        volatile unsigned int res;      /* 0x0C Reserved */
152};
153
154#define BD_CHAN_EN              0x80000000
155#define BD_CHAN_TYPE            0x00300000
156#define BD_CHAN_BDCNT           0x0000ffff
157#define BD_CHAN_EN_BIT          31
158#define BD_CHAN_TYPE_BIT        20
159#define BD_CHAN_BDCNT_BIT       0
160
161struct grpci2_bd_data {
162        volatile unsigned int ctrl;     /* 0x00 DMA Data Control */
163        volatile unsigned int pci_adr;  /* 0x04 PCI Start Address */
164        volatile unsigned int ahb_adr;  /* 0x08 AHB Start address */
165        volatile unsigned int next;     /* 0x0C Next Data Descriptor in channel */
166};
167
168#define BD_DATA_EN              0x80000000
169#define BD_DATA_IE              0x40000000
170#define BD_DATA_DR              0x20000000
171#define BD_DATA_TYPE            0x00300000
172#define BD_DATA_ER              0x00080000
173#define BD_DATA_LEN             0x0000ffff
174#define BD_DATA_EN_BIT          31
175#define BD_DATA_IE_BIT          30
176#define BD_DATA_DR_BIT          29
177#define BD_DATA_TYPE_BIT        20
178#define BD_DATA_ER_BIT          19
179#define BD_DATA_LEN_BIT         0
180
181/* GRPCI2 Capability */
182struct grpci2_cap_first {
183        unsigned int ctrl;
184        unsigned int pci2ahb_map[6];
185        unsigned int ext2ahb_map;
186        unsigned int io_map;
187        unsigned int pcibar_size[6];
188        unsigned int ahb_pref;
189};
190#define CAP9_CTRL_OFS 0
191#define CAP9_BAR_OFS 0x4
192#define CAP9_IOMAP_OFS 0x20
193#define CAP9_BARSIZE_OFS 0x24
194#define CAP9_AHBPREF_OFS 0x3C
195
196/* Used internally for accessing the PCI bridge's configuration space itself */
197#define HOST_TGT PCI_DEV(0xff, 0, 0)
198
199struct grpci2_priv *grpci2priv = NULL;
200
201/* PCI Interrupt assignment. Connects an PCI interrupt pin (INTA#..INTD#)
202 * to a system interrupt number.
203 */
204unsigned char grpci2_pci_irq_table[4] =
205{
206        /* INTA# */     GRPCI2_INTA_SYSIRQ,
207        /* INTB# */     GRPCI2_INTB_SYSIRQ,
208        /* INTC# */     GRPCI2_INTC_SYSIRQ,
209        /* INTD# */     GRPCI2_INTD_SYSIRQ
210};
211
212/* Start of workspace/dynamical area */
213extern unsigned int _end;
214#define DMA_START ((unsigned int) &_end)
215
216/* Default BAR mapping, set BAR0 256MB 1:1 mapped base of CPU RAM */
217struct grpci2_pcibar_cfg grpci2_default_bar_mapping[6] = {
218        /* BAR0 */ {DMA_START, DMA_START, 0x10000000},
219        /* BAR1 */ {0, 0, 0},
220        /* BAR2 */ {0, 0, 0},
221        /* BAR3 */ {0, 0, 0},
222        /* BAR4 */ {0, 0, 0},
223        /* BAR5 */ {0, 0, 0},
224};
225
226/* Driver private data struture */
227struct grpci2_priv {
228        struct drvmgr_dev       *dev;
229        struct grpci2_regs              *regs;
230        unsigned char                   ver;
231        char                            irq;
232        char                            irq_mode; /* IRQ Mode from CAPSTS REG */
233        char                            bt_enabled;
234        unsigned int                    irq_mask;
235
236        struct grpci2_pcibar_cfg        *barcfg;
237
238        unsigned int                    pci_area;
239        unsigned int                    pci_area_end;
240        unsigned int                    pci_io;   
241        unsigned int                    pci_conf;
242        unsigned int                    pci_conf_end;
243
244        uint32_t                        devVend; /* Host PCI Device/Vendor ID */
245
246        struct drvmgr_map_entry         maps_up[7];
247        struct drvmgr_map_entry         maps_down[2];
248        struct pcibus_config            config;
249};
250
251int grpci2_init1(struct drvmgr_dev *dev);
252int grpci2_init3(struct drvmgr_dev *dev);
253void grpci2_err_isr(void *arg);
254
255/* GRPCI2 DRIVER */
256
257struct drvmgr_drv_ops grpci2_ops =
258{
259        .init = {grpci2_init1, NULL, grpci2_init3, NULL},
260        .remove = NULL,
261        .info = NULL
262};
263
264struct amba_dev_id grpci2_ids[] =
265{
266        {VENDOR_GAISLER, GAISLER_GRPCI2},
267        {0, 0}          /* Mark end of table */
268};
269
270struct amba_drv_info grpci2_info =
271{
272        {
273                DRVMGR_OBJ_DRV,                 /* Driver */
274                NULL,                           /* Next driver */
275                NULL,                           /* Device list */
276                DRIVER_AMBAPP_GAISLER_GRPCI2_ID,/* Driver ID */
277                "GRPCI2_DRV",                   /* Driver Name */
278                DRVMGR_BUS_TYPE_AMBAPP,         /* Bus Type */
279                &grpci2_ops,
280                NULL,                           /* Funcs */
281                0,                              /* No devices yet */
282                sizeof(struct grpci2_priv),     /* Make drvmgr alloc private */
283        },
284        &grpci2_ids[0]
285};
286
287void grpci2_register_drv(void)
288{
289        DBG("Registering GRPCI2 driver\n");
290        drvmgr_drv_register(&grpci2_info.general);
291}
292
293static int grpci2_cfg_r32(pci_dev_t dev, int ofs, uint32_t *val)
294{
295        struct grpci2_priv *priv = grpci2priv;
296        volatile uint32_t *pci_conf;
297        unsigned int tmp, devfn;
298        IRQ_GLOBAL_PREPARE(oldLevel);
299        int retval, bus = PCI_DEV_BUS(dev);
300
301        if ((unsigned int)ofs & 0xffffff03) {
302                retval = PCISTS_EINVAL;
303                goto out2;
304        }
305
306        if (PCI_DEV_SLOT(dev) > 15) {
307                retval = PCISTS_MSTABRT;
308                goto out;
309        }
310
311        /* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
312         * we skip them.
313         */
314        if (dev == HOST_TGT)
315                bus = devfn = 0;
316        else if (bus == 0)
317                devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
318        else
319                devfn = PCI_DEV_DEVFUNC(dev);
320
321        pci_conf = (volatile uint32_t *) (priv->pci_conf | (devfn << 8) | ofs);
322
323        IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
324
325        /* Select bus */
326        priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) | (bus<<16);
327        /* clear old status */
328        priv->regs->sts_cap = (STS_CFGERR | STS_CFGERRVALID);
329
330        tmp = *pci_conf;
331
332        /* Wait until GRPCI2 signals that CFG access is done, it should be
333         * done instantaneously unless a DMA operation is ongoing...
334         */
335        while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
336                ;
337
338        if (priv->regs->sts_cap & STS_CFGERR) {
339                retval = PCISTS_MSTABRT;
340        } else {
341                /* Bus always little endian (unaffected by byte-swapping) */
342                *val = CPU_swap_u32(tmp);
343                retval = PCISTS_OK;
344        }
345
346        IRQ_GLOBAL_ENABLE(oldLevel);
347
348out:
349        if (retval != PCISTS_OK)
350                *val = 0xffffffff;
351
352        DBG("pci_read: [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x  (%d)\n",
353                PCI_DEV_EXPAND(dev), ofs, pci_conf, *val, retval);
354
355out2:
356        return retval;
357}
358
359static int grpci2_cfg_r16(pci_dev_t dev, int ofs, uint16_t *val)
360{
361        uint32_t v;
362        int retval;
363
364        if (ofs & 1)
365                return PCISTS_EINVAL;
366
367        retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
368        *val = 0xffff & (v >> (8*(ofs & 0x3)));
369
370        return retval;
371}
372
373static int grpci2_cfg_r8(pci_dev_t dev, int ofs, uint8_t *val)
374{
375        uint32_t v;
376        int retval;
377
378        retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
379
380        *val = 0xff & (v >> (8*(ofs & 3)));
381
382        return retval;
383}
384
385static int grpci2_cfg_w32(pci_dev_t dev, int ofs, uint32_t val)
386{
387        struct grpci2_priv *priv = grpci2priv;
388        volatile uint32_t *pci_conf;
389        uint32_t value, devfn;
390        int retval, bus = PCI_DEV_BUS(dev);
391        IRQ_GLOBAL_PREPARE(oldLevel);
392
393        if ((unsigned int)ofs & 0xffffff03)
394                return PCISTS_EINVAL;
395
396        if (PCI_DEV_SLOT(dev) > 15)
397                return PCISTS_MSTABRT;
398
399        value = CPU_swap_u32(val);
400
401        /* GRPCI2 can access "non-standard" devices on bus0 (on AD11.AD16),
402         * we skip them.
403         */
404        if (dev == HOST_TGT)
405                bus = devfn = 0;
406        else if (bus == 0)
407                devfn = PCI_DEV_DEVFUNC(dev) + PCI_DEV(0, 6, 0);
408        else
409                devfn = PCI_DEV_DEVFUNC(dev);
410
411        pci_conf = (volatile uint32_t *) (priv->pci_conf | (devfn << 8) | ofs);
412
413        IRQ_GLOBAL_DISABLE(oldLevel); /* protect regs */
414
415        /* Select bus */
416        priv->regs->ctrl = (priv->regs->ctrl & ~(0xff<<16)) | (bus<<16);
417        /* clear old status */
418        priv->regs->sts_cap = (STS_CFGERR | STS_CFGERRVALID);
419
420        *pci_conf = value;
421
422        /* Wait until GRPCI2 signals that CFG access is done, it should be
423         * done instantaneously unless a DMA operation is ongoing...
424         */
425        while ((priv->regs->sts_cap & STS_CFGERRVALID) == 0)
426                ;
427
428        if (priv->regs->sts_cap & STS_CFGERR)
429                retval = PCISTS_MSTABRT;
430        else
431                retval = PCISTS_OK;
432
433        IRQ_GLOBAL_ENABLE(oldLevel);
434
435        DBG("pci_write - [%x:%x:%x] reg: 0x%x => addr: 0x%x, val: 0x%x  (%d)\n",
436                PCI_DEV_EXPAND(dev), ofs, pci_conf, value, retval);
437
438        return retval;
439}
440
441static int grpci2_cfg_w16(pci_dev_t dev, int ofs, uint16_t val)
442{
443        uint32_t v;
444        int retval;
445
446        if (ofs & 1)
447                return PCISTS_EINVAL;
448
449        retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
450        if (retval != PCISTS_OK)
451                return retval;
452
453        v = (v & ~(0xffff << (8*(ofs&3)))) | ((0xffff&val) << (8*(ofs&3)));
454
455        return grpci2_cfg_w32(dev, ofs & ~0x3, v);
456}
457
458static int grpci2_cfg_w8(pci_dev_t dev, int ofs, uint8_t val)
459{
460        uint32_t v;
461        int retval;
462
463        retval = grpci2_cfg_r32(dev, ofs & ~0x3, &v);
464        if (retval != PCISTS_OK)
465                return retval;
466
467        v = (v & ~(0xff << (8*(ofs&3)))) | ((0xff&val) << (8*(ofs&3)));
468
469        return grpci2_cfg_w32(dev, ofs & ~0x3, v);
470}
471
472/* Return the assigned system IRQ number that corresponds to the PCI
473 * "Interrupt Pin" information from configuration space.
474 *
475 * The IRQ information is stored in the grpci2_pci_irq_table configurable
476 * by the user.
477 *
478 * Returns the "system IRQ" for the PCI INTA#..INTD# pin in irq_pin. Returns
479 * 0xff if not assigned.
480 */
481static uint8_t grpci2_bus0_irq_map(pci_dev_t dev, int irq_pin)
482{
483        uint8_t sysIrqNr = 0; /* not assigned */
484        int irq_group;
485
486        if ( (irq_pin >= 1) && (irq_pin <= 4) ) {
487                /* Use default IRQ decoding on PCI BUS0 according slot numbering */
488                irq_group = PCI_DEV_SLOT(dev) & 0x3;
489                irq_pin = ((irq_pin - 1) + irq_group) & 0x3;
490                /* Valid PCI "Interrupt Pin" number */
491                sysIrqNr = grpci2_pci_irq_table[irq_pin];
492        }
493        return sysIrqNr;
494}
495
496static int grpci2_translate(uint32_t *address, int type, int dir)
497{
498        uint32_t adr, start, end;
499        struct grpci2_priv *priv = grpci2priv;
500        int i;
501
502        if (type == 1) {
503                /* I/O */
504                if (dir != 0) {
505                        /* The PCI bus can not access the CPU bus from I/O
506                         * because GRPCI2 core does not support I/O BARs
507                         */
508                        return -1;
509                }
510
511                /* We have got a PCI IO BAR address that the CPU want to access.
512                 * Check that it is within the PCI I/O window, I/O adresses
513                 * are NOT mapped 1:1 with GRPCI2 driver... translation needed.
514                 */
515                adr = *(uint32_t *)address;
516                if (adr < 0x100 || adr > 0x10000)
517                        return -1;
518                *address = adr + priv->pci_io;
519        } else {
520                /* MEMIO and MEM.
521                 * Memory space is mapped 1:1 so no translation is needed.
522                 * Check that address is within accessible windows.
523                 */
524                adr = *(uint32_t *)address;
525                if (dir == 0) {
526                        /* PCI BAR to AMBA-CPU address.. check that it is
527                         * located within GRPCI2 PCI Memory Window
528                         * adr = PCI address.
529                         */
530                        if (adr < priv->pci_area || adr >= priv->pci_area_end)
531                                return -1;
532                } else {
533                        /* We have a CPU address and want to get access to it
534                         * from PCI space, typically when doing DMA into CPU
535                         * RAM. The GRPCI2 core may have multiple target BARs
536                         * that PCI masters can access, the BARs are user
537                         * configurable in the following ways:
538                         *  BAR_SIZE, PCI_BAR Address and MAPPING (AMBA ADR)
539                         *
540                         * The below code tries to find a BAR for which the
541                         * AMBA bar may have been mapped onto, and translate
542                         * the AMBA-CPU address into a PCI address using the
543                         * given mapping.
544                         *
545                         * adr = AMBA address.
546                         */
547                        for(i=0; i<6; i++) {
548                                start = priv->barcfg[i].ahbadr;
549                                end = priv->barcfg[i].ahbadr +
550                                        priv->barcfg[i].barsize;
551                                if (adr >= start && adr < end) {
552                                        /* BAR match: Translate address */
553                                        *address = (adr - start) +
554                                                priv->barcfg[i].pciadr;
555                                        return 0;
556                                }
557                        }
558                        return -1;
559                }
560        }
561
562        return 0;
563}
564
565extern struct pci_memreg_ops pci_memreg_sparc_le_ops;
566extern struct pci_memreg_ops pci_memreg_sparc_be_ops;
567
568/* GRPCI2 PCI access routines, default to Little-endian PCI Bus */
569struct pci_access_drv grpci2_access_drv = {
570        .cfg =
571        {
572                grpci2_cfg_r8,
573                grpci2_cfg_r16,
574                grpci2_cfg_r32,
575                grpci2_cfg_w8,
576                grpci2_cfg_w16,
577                grpci2_cfg_w32,
578        },
579        .io =
580        {
581                _ld8,
582                _ld_le16,
583                _ld_le32,
584                _st8,
585                _st_le16,
586                _st_le32,
587        },
588        .memreg = &pci_memreg_sparc_le_ops,
589        .translate = grpci2_translate,
590};
591
592struct pci_io_ops grpci2_io_ops_be =
593{
594        _ld8,
595        _ld_be16,
596        _ld_be32,
597        _st8,
598        _st_be16,
599        _st_be32,
600};
601
602/* PCI Error Interrupt handler, called when there may be a PCI Target/Master
603 * Abort.
604 */
605void grpci2_err_isr(void *arg)
606{
607        struct grpci2_priv *priv = arg;
608        unsigned int sts = priv->regs->sts_cap;
609
610        if (sts & (STS_IMSTABRT | STS_ITGTABRT | STS_IPARERR | STS_ISYSERR)) {
611                /* A PCI error IRQ ... Error handler unimplemented
612                 * add your code here...
613                 */
614                if (sts & STS_IMSTABRT) {
615                        printk("GRPCI2: unhandled Master Abort IRQ\n");
616                }
617                if (sts & STS_ITGTABRT) {
618                        printk("GRPCI2: unhandled Target Abort IRQ\n");
619                }
620                if (sts & STS_IPARERR) {
621                        printk("GRPCI2: unhandled Parity Error IRQ\n");
622                }
623                if (sts & STS_ISYSERR) {
624                        printk("GRPCI2: unhandled System Error IRQ\n");
625                }
626        }
627}
628
629static int grpci2_hw_init(struct grpci2_priv *priv)
630{
631        struct grpci2_regs *regs = priv->regs;
632        int i;
633        uint8_t capptr;
634        uint32_t data, io_map, ahbadr, pciadr, size;
635        pci_dev_t host = HOST_TGT;
636        struct grpci2_pcibar_cfg *barcfg = priv->barcfg;
637
638        /* Reset any earlier setup */
639        regs->ctrl = 0;
640        regs->sts_cap = ~0; /* Clear Status */
641        regs->dma_ctrl = 0;
642        regs->dma_bdbase = 0;
643
644        /* Translate I/O accesses 1:1, (will not work for PCI 2.3) */
645        regs->io_map = priv->pci_io & 0xffff0000;
646
647        /* set 1:1 mapping between AHB -> PCI memory space, for all Masters
648         * Each AHB master has it's own mapping registers. Max 16 AHB masters.
649         */
650        for (i=0; i<16; i++)
651                regs->ahbmst_map[i] = priv->pci_area;
652
653        /* Get the GRPCI2 Host PCI ID */
654        grpci2_cfg_r32(host, PCIR_VENDOR, &priv->devVend);
655
656        /* Get address to first (always defined) capability structure */
657        grpci2_cfg_r8(host, PCIR_CAP_PTR, &capptr);
658        if (capptr == 0)
659                return -1;
660
661        /* Limit the prefetch for GRPCI2 version 0. */
662        if (priv->ver == 0)
663                grpci2_cfg_w32(host, capptr+CAP9_AHBPREF_OFS, 0);
664
665        /* Enable/Disable Byte twisting */
666        grpci2_cfg_r32(host, capptr+CAP9_IOMAP_OFS, &io_map);
667        io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
668        grpci2_cfg_w32(host, capptr+CAP9_IOMAP_OFS, io_map);
669
670        /* Setup the Host's PCI Target BARs for others to access (DMA) */
671        for (i=0; i<6; i++) {
672                /* Make sure address is properly aligned */
673                size = ~(barcfg[i].barsize-1);
674                barcfg[i].pciadr &= size;
675                barcfg[i].ahbadr &= size;
676
677                pciadr = barcfg[i].pciadr;
678                ahbadr = barcfg[i].ahbadr;
679                size |= PCIM_BAR_MEM_PREFETCH;
680
681                grpci2_cfg_w32(host, capptr+CAP9_BARSIZE_OFS+i*4, size);
682                grpci2_cfg_w32(host, capptr+CAP9_BAR_OFS+i*4, ahbadr);
683                grpci2_cfg_w32(host, PCIR_BAR(0)+i*4, pciadr);
684        }
685
686        /* set as bus master and enable pci memory responses */ 
687        grpci2_cfg_r32(host, PCIR_COMMAND, &data);
688        data |= (PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
689        grpci2_cfg_w32(host, PCIR_COMMAND, data);
690
691        /* Enable Error respone (CPU-TRAP) on illegal memory access */
692        regs->ctrl = CTRL_ER | CTRL_PE;
693
694        /* Successful */
695        return 0;
696}
697
698/* Initializes the GRPCI2 core and driver, must be called before calling
699 * init_pci()
700 *
701 * Return values
702 *  0             Successful initalization
703 *  -1            Error during initialization, for example "PCI core not found".
704 *  -2            Error PCI controller not HOST (targets not supported)
705 *  -3            Error due to GRPCI2 hardware initialization
706 */
707static int grpci2_init(struct grpci2_priv *priv)
708{
709        struct ambapp_apb_info *apb;
710        struct ambapp_ahb_info *ahb;
711        int pin, i, j;
712        union drvmgr_key_value *value;
713        char keyname[6];
714        struct amba_dev_info *ainfo = priv->dev->businfo;
715        struct grpci2_pcibar_cfg *barcfg;
716        unsigned int size;
717
718        /* Find PCI core from Plug&Play information */
719        apb = ainfo->info.apb_slv;
720        ahb = ainfo->info.ahb_slv;
721
722        /* Found PCI core, init private structure */
723        priv->irq = apb->irq;
724        priv->ver = apb->ver;
725        priv->regs = (struct grpci2_regs *)apb->start;
726        priv->bt_enabled = DEFAULT_BT_ENABLED;
727        priv->irq_mode = (priv->regs->sts_cap & STS_IRQMODE) >> STS_IRQMODE_BIT;
728
729        /* Calculate the PCI windows
730         *  AMBA->PCI Window:                       AHB SLAVE AREA0
731         *  AMBA->PCI I/O cycles Window:            AHB SLAVE AREA1 Lower half
732         *  AMBA->PCI Configuration cycles Window:  AHB SLAVE AREA1 Upper half
733         */
734        priv->pci_area     = ahb->start[0];
735        priv->pci_area_end = ahb->start[0] + ahb->mask[0];
736        priv->pci_io       = ahb->start[1];
737        priv->pci_conf     = ahb->start[1] + 0x10000;
738        priv->pci_conf_end = priv->pci_conf + 0x10000;
739
740        /* On systems where PCI I/O area and configuration area is apart of the
741         * "PCI Window" the PCI Window stops at the start of the PCI I/O area
742         */
743        if ((priv->pci_io > priv->pci_area) &&
744            (priv->pci_io < (priv->pci_area_end-1))) {
745                priv->pci_area_end = priv->pci_io;
746        }
747
748        /* Init PCI interrupt assignment table to all use the interrupt routed
749         * through the GRPCI2 core.
750         */
751        strcpy(keyname, "INTX#");
752        for (pin=1; pin<5; pin++) {
753                if (grpci2_pci_irq_table[pin-1] == 0xff) {
754                        if (priv->irq_mode < 2) {
755                                /* PCI Interrupts are shared */
756                                grpci2_pci_irq_table[pin-1] = priv->irq;
757                        } else {
758                                /* Unique IRQ per PCI INT Pin */
759                                grpci2_pci_irq_table[pin-1] = priv->irq + pin-1;
760                        }
761
762                        /* User may override Both hardcoded IRQ setup and Plug & Play IRQ */
763                        keyname[3] = 'A' + (pin-1);
764                        value = drvmgr_dev_key_get(priv->dev, keyname, DRVMGR_KT_INT);
765                        if (value)
766                                grpci2_pci_irq_table[pin-1] = value->i;
767                }
768
769                /* Remember which IRQs are enabled */
770                if (grpci2_pci_irq_table[pin-1] != 0)
771                        priv->irq_mask |= 1 << (pin-1);
772        }
773
774        /* User may override DEFAULT_BT_ENABLED to enable/disable byte twisting */
775        value = drvmgr_dev_key_get(priv->dev, "byteTwisting", DRVMGR_KT_INT);
776        if (value)
777                priv->bt_enabled = value->i;
778
779        /* Let user Configure the 6 target BARs */
780        value = drvmgr_dev_key_get(priv->dev, "tgtBarCfg", DRVMGR_KT_POINTER);
781        if (value)
782                priv->barcfg = value->ptr;
783        else
784                priv->barcfg = grpci2_default_bar_mapping;
785
786        /* This driver only support HOST systems, we check that it can act as a
787         * PCI Master and that it is in the Host slot. */
788        if ((priv->regs->sts_cap&STS_HOST) || !(priv->regs->sts_cap&STS_MST))
789                return -2; /* Target not supported */
790
791        /* Init the PCI Core */
792        if (grpci2_hw_init(priv))
793                return -3;
794
795        /* Down streams translation table */
796        priv->maps_down[0].name = "AMBA -> PCI MEM Window";
797        priv->maps_down[0].size = priv->pci_area_end - priv->pci_area;
798        priv->maps_down[0].from_adr = (void *)priv->pci_area;
799        priv->maps_down[0].to_adr = (void *)priv->pci_area;
800        /* End table */
801        priv->maps_down[1].size = 0;
802
803        /* Up streams translation table */
804        /* Setup the Host's PCI Target BARs for others to access (DMA) */
805        barcfg = priv->barcfg;
806        for (i=0,j=0; i<6; i++) {
807                size = barcfg[i].barsize;
808                if (size == 0)
809                        continue;
810
811                /* Make sure address is properly aligned */
812                priv->maps_up[j].name = "Target BAR[I] -> AMBA";
813                priv->maps_up[j].size = size;
814                priv->maps_up[j].from_adr = (void *)
815                                        (barcfg[i].pciadr & ~(size - 1));
816                priv->maps_up[j].to_adr = (void *)
817                                        (barcfg[i].ahbadr & ~(size - 1));
818                j++;
819        }
820
821        /* End table */
822        priv->maps_up[j].size = 0;
823
824        return 0;
825}
826
827/* Called when a core is found with the AMBA device and vendor ID
828 * given in grpci2_ids[]. IRQ, Console does not work here
829 */
830int grpci2_init1(struct drvmgr_dev *dev)
831{
832        int status;
833        struct grpci2_priv *priv;
834        struct pci_auto_setup grpci2_auto_cfg;
835
836        DBG("GRPCI2[%d] on bus %s\n", dev->minor_drv, dev->parent->dev->name);
837
838        if (grpci2priv) {
839                DBG("Driver only supports one PCI core\n");
840                return DRVMGR_FAIL;
841        }
842
843        if ((strcmp(dev->parent->dev->drv->name, "AMBAPP_GRLIB_DRV") != 0) &&
844            (strcmp(dev->parent->dev->drv->name, "AMBAPP_LEON2_DRV") != 0)) {
845                /* We only support GRPCI2 driver on local bus */
846                return DRVMGR_FAIL;
847        }
848
849        priv = dev->priv;
850        if (!priv)
851                return DRVMGR_NOMEM;
852
853        priv->dev = dev;
854        grpci2priv = priv;
855
856        /* Initialize GRPCI2 Hardware */
857        status = grpci2_init(priv);
858        if (status) {
859                printf("Failed to initialize grpci2 driver %d\n", status);
860                return -1;
861        }
862
863        /* Register the PCI core at the PCI layers */
864
865        if (priv->bt_enabled == 0) {
866                /* Host is Big-Endian */
867                pci_endian = PCI_BIG_ENDIAN;
868
869                memcpy(&grpci2_access_drv.io, &grpci2_io_ops_be,
870                                                sizeof(grpci2_io_ops_be));
871                grpci2_access_drv.memreg = &pci_memreg_sparc_be_ops;
872        }
873
874        if (pci_access_drv_register(&grpci2_access_drv)) {
875                /* Access routines registration failed */
876                return DRVMGR_FAIL;
877        }
878
879        /* Prepare memory MAP */
880        grpci2_auto_cfg.options = 0;
881        grpci2_auto_cfg.mem_start = 0;
882        grpci2_auto_cfg.mem_size = 0;
883        grpci2_auto_cfg.memio_start = priv->pci_area;
884        grpci2_auto_cfg.memio_size = priv->pci_area_end - priv->pci_area;
885        grpci2_auto_cfg.io_start = 0x100; /* avoid PCI address 0 */
886        grpci2_auto_cfg.io_size = 0x10000 - 0x100; /* lower 64kB I/O 16 */
887        grpci2_auto_cfg.irq_map = grpci2_bus0_irq_map;
888        grpci2_auto_cfg.irq_route = NULL; /* use standard routing */
889        pci_config_register(&grpci2_auto_cfg);
890
891        if (pci_config_init()) {
892                /* PCI configuration failed */
893                return DRVMGR_FAIL;
894        }
895
896        /* Initialize/Register Driver Manager PCI Bus */
897        priv->config.maps_down = &priv->maps_down[0];
898        priv->config.maps_up = &priv->maps_up[0];
899        return pcibus_register(dev, &priv->config);
900}
901
902int grpci2_init3(struct drvmgr_dev *dev)
903{
904        struct grpci2_priv *priv = dev->priv;
905
906        /* Install and Enable PCI Error interrupt handler */
907        drvmgr_interrupt_register(dev, 0, "grpci2", grpci2_err_isr, priv);
908
909        /* Unmask Error IRQ and all PCI interrupts at PCI Core. For this to be
910         * safe every PCI board have to be resetted (no IRQ generation) before
911         * Global IRQs are enabled (Init is reached or similar)
912         */
913        priv->regs->ctrl |= (CTRL_EI | priv->irq_mask);
914
915        return DRVMGR_OK;
916}
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