1 | /* GR-RASTA-IO PCI Target driver. |
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2 | * |
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3 | * COPYRIGHT (c) 2008. |
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4 | * Cobham Gaisler AB. |
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5 | * |
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6 | * Configures the GR-RASTA-IO interface PCI board. |
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7 | * This driver provides a AMBA PnP bus by using the general part |
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8 | * of the AMBA PnP bus driver (ambapp_bus.c). |
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9 | * |
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10 | * Driver resources for the AMBA PnP bus provided can be set using |
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11 | * gr_rasta_io_set_resources(). |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.com/license/LICENSE. |
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16 | */ |
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17 | |
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18 | #include <stdio.h> |
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19 | #include <stdlib.h> |
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20 | #include <string.h> |
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21 | #include <sys/types.h> |
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22 | #include <sys/stat.h> |
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23 | |
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24 | #include <bsp.h> |
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25 | #include <rtems/bspIo.h> |
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26 | #include <pci.h> |
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27 | |
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28 | #include <ambapp.h> |
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29 | #include <grlib.h> |
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30 | #include <drvmgr/drvmgr.h> |
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31 | #include <drvmgr/ambapp_bus.h> |
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32 | #include <drvmgr/pci_bus.h> |
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33 | #include <genirq.h> |
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34 | |
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35 | #include <gr_rasta_io.h> |
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36 | |
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37 | /* Determines which PCI address the AHB masters will access, it should be |
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38 | * set so that the masters can access the CPU RAM. Default is base of CPU RAM, |
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39 | * CPU RAM is mapped 1:1 to PCI space. |
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40 | */ |
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41 | extern unsigned int _RAM_START; |
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42 | #define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000) |
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43 | |
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44 | /* Offset from 0x80000000 (dual bus version) */ |
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45 | #define AHB1_BASE_ADDR 0x80000000 |
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46 | #define AHB1_IOAREA_BASE_ADDR 0x80100000 |
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47 | |
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48 | /* #define DEBUG 1 */ |
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49 | |
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50 | #ifdef DEBUG |
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51 | #define DBG(x...) printk(x) |
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52 | #else |
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53 | #define DBG(x...) |
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54 | #endif |
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55 | |
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56 | /* PCI ID */ |
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57 | #define PCIID_VENDOR_GAISLER 0x1AC8 |
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58 | |
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59 | int gr_rasta_io_init1(struct drvmgr_dev *dev); |
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60 | int gr_rasta_io_init2(struct drvmgr_dev *dev); |
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61 | |
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62 | struct grpci_regs { |
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63 | volatile unsigned int cfg_stat; |
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64 | volatile unsigned int bar0; |
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65 | volatile unsigned int page0; |
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66 | volatile unsigned int bar1; |
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67 | volatile unsigned int page1; |
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68 | volatile unsigned int iomap; |
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69 | volatile unsigned int stat_cmd; |
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70 | }; |
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71 | |
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72 | struct gr_rasta_io_ver { |
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73 | const unsigned int amba_freq_hz; /* The frequency */ |
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74 | const unsigned int amba_ioarea; /* The address where the PnP IOAREA starts at */ |
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75 | }; |
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76 | |
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77 | /* Private data structure for driver */ |
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78 | struct gr_rasta_io_priv { |
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79 | /* Driver management */ |
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80 | struct drvmgr_dev *dev; |
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81 | char prefix[16]; |
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82 | |
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83 | /* PCI */ |
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84 | pci_dev_t pcidev; |
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85 | struct pci_dev_info *devinfo; |
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86 | uint32_t ahbmst2pci_map; |
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87 | |
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88 | /* IRQ */ |
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89 | genirq_t genirq; |
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90 | |
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91 | /* GR-RASTA-IO */ |
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92 | struct gr_rasta_io_ver *version; |
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93 | struct irqmp_regs *irq; |
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94 | struct grpci_regs *grpci; |
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95 | struct drvmgr_map_entry bus_maps_down[3]; |
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96 | struct drvmgr_map_entry bus_maps_up[2]; |
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97 | |
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98 | /* AMBA Plug&Play information on GR-RASTA-IO */ |
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99 | struct ambapp_bus abus; |
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100 | struct ambapp_mmap amba_maps[4]; |
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101 | struct ambapp_config config; |
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102 | }; |
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103 | |
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104 | struct gr_rasta_io_ver gr_rasta_io_ver0 = { |
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105 | .amba_freq_hz = 30000000, |
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106 | .amba_ioarea = 0x80100000, |
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107 | }; |
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108 | |
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109 | struct gr_rasta_io_ver gr_rasta_io_ver1 = { |
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110 | .amba_freq_hz = 50000000, |
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111 | .amba_ioarea = 0x80100000, |
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112 | }; |
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113 | |
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114 | int ambapp_rasta_io_int_register( |
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115 | struct drvmgr_dev *dev, |
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116 | int irq, |
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117 | const char *info, |
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118 | drvmgr_isr handler, |
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119 | void *arg); |
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120 | int ambapp_rasta_io_int_unregister( |
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121 | struct drvmgr_dev *dev, |
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122 | int irq, |
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123 | drvmgr_isr handler, |
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124 | void *arg); |
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125 | int ambapp_rasta_io_int_unmask( |
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126 | struct drvmgr_dev *dev, |
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127 | int irq); |
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128 | int ambapp_rasta_io_int_mask( |
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129 | struct drvmgr_dev *dev, |
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130 | int irq); |
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131 | int ambapp_rasta_io_int_clear( |
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132 | struct drvmgr_dev *dev, |
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133 | int irq); |
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134 | int ambapp_rasta_io_get_params( |
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135 | struct drvmgr_dev *dev, |
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136 | struct drvmgr_bus_params *params); |
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137 | |
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138 | struct ambapp_ops ambapp_rasta_io_ops = { |
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139 | .int_register = ambapp_rasta_io_int_register, |
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140 | .int_unregister = ambapp_rasta_io_int_unregister, |
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141 | .int_unmask = ambapp_rasta_io_int_unmask, |
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142 | .int_mask = ambapp_rasta_io_int_mask, |
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143 | .int_clear = ambapp_rasta_io_int_clear, |
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144 | .get_params = ambapp_rasta_io_get_params |
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145 | }; |
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146 | |
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147 | struct drvmgr_drv_ops gr_rasta_io_ops = |
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148 | { |
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149 | .init = {gr_rasta_io_init1, gr_rasta_io_init2, NULL, NULL}, |
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150 | .remove = NULL, |
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151 | .info = NULL |
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152 | }; |
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153 | |
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154 | struct pci_dev_id_match gr_rasta_io_ids[] = |
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155 | { |
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156 | PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_IO), |
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157 | PCIID_DEVVEND(PCIID_VENDOR_GAISLER_OLD, PCIID_DEVICE_GR_RASTA_IO_OLD), |
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158 | PCIID_END_TABLE /* Mark end of table */ |
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159 | }; |
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160 | |
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161 | struct pci_drv_info gr_rasta_io_info = |
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162 | { |
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163 | { |
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164 | DRVMGR_OBJ_DRV, /* Driver */ |
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165 | NULL, /* Next driver */ |
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166 | NULL, /* Device list */ |
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167 | DRIVER_PCI_GAISLER_RASTAIO_ID, /* Driver ID */ |
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168 | "GR-RASTA-IO_DRV", /* Driver Name */ |
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169 | DRVMGR_BUS_TYPE_PCI, /* Bus Type */ |
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170 | &gr_rasta_io_ops, |
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171 | NULL, /* Funcs */ |
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172 | 0, /* No devices yet */ |
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173 | 0, |
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174 | }, |
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175 | &gr_rasta_io_ids[0] |
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176 | }; |
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177 | |
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178 | /* Driver resources configuration for the AMBA bus on the GR-RASTA-IO board. |
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179 | * It is declared weak so that the user may override it from the project file, |
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180 | * if the default settings are not enough. |
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181 | * |
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182 | * The configuration consists of an array of configuration pointers, each |
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183 | * pointer determine the configuration of one GR-RASTA-IO board. Pointer |
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184 | * zero is for board0, pointer 1 for board1 and so on. |
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185 | * |
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186 | * The array must end with a NULL pointer. |
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187 | */ |
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188 | struct drvmgr_bus_res *gr_rasta_io_resources[] __attribute__((weak)) = |
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189 | { |
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190 | NULL |
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191 | }; |
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192 | int gr_rasta_io_resources_cnt = 0; |
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193 | |
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194 | void gr_rasta_io_register_drv(void) |
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195 | { |
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196 | DBG("Registering GR-RASTA-IO PCI driver\n"); |
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197 | drvmgr_drv_register(&gr_rasta_io_info.general); |
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198 | } |
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199 | |
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200 | void gr_rasta_io_isr (void *arg) |
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201 | { |
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202 | struct gr_rasta_io_priv *priv = arg; |
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203 | unsigned int status, tmp; |
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204 | int irq; |
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205 | tmp = status = priv->irq->ipend; |
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206 | |
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207 | /* DBG("GR-RASTA-IO: IRQ 0x%x\n",status); */ |
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208 | |
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209 | for(irq=0; irq<16; irq++) { |
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210 | if ( status & (1<<irq) ) { |
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211 | genirq_doirq(priv->genirq, irq); |
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212 | priv->irq->iclear = (1<<irq); |
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213 | status &= ~(1<<irq); |
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214 | if ( status == 0 ) |
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215 | break; |
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216 | } |
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217 | } |
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218 | |
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219 | /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */ |
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220 | if ( tmp ) |
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221 | drvmgr_interrupt_clear(priv->dev, 0); |
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222 | |
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223 | DBG("RASTA-IO-IRQ: 0x%x\n", tmp); |
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224 | } |
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225 | |
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226 | int gr_rasta_io_hw_init(struct gr_rasta_io_priv *priv) |
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227 | { |
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228 | unsigned int *page0 = NULL; |
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229 | struct ambapp_dev *tmp; |
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230 | int status; |
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231 | struct ambapp_ahb_info *ahb; |
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232 | struct pci_dev_info *devinfo = priv->devinfo; |
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233 | uint32_t bar0, bar0_size; |
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234 | |
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235 | /* Select version of GR-RASTA-IO board */ |
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236 | switch (devinfo->rev) { |
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237 | case 0: |
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238 | priv->version = &gr_rasta_io_ver0; |
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239 | break; |
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240 | case 1: |
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241 | priv->version = &gr_rasta_io_ver1; |
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242 | break; |
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243 | default: |
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244 | return -2; |
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245 | } |
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246 | |
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247 | bar0 = devinfo->resources[0].address; |
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248 | bar0_size = devinfo->resources[0].size; |
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249 | page0 = (unsigned int *)(bar0 + bar0_size/2); |
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250 | |
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251 | /* Point PAGE0 to start of Plug and Play information */ |
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252 | *page0 = priv->version->amba_ioarea & 0xf0000000; |
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253 | |
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254 | #if 0 |
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255 | { |
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256 | uint32_t data; |
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257 | /* set parity error response */ |
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258 | pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data); |
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259 | pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY)); |
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260 | } |
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261 | #endif |
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262 | |
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263 | /* Setup cache line size. Default cache line size will result in |
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264 | * poor performance (256 word fetches), 0xff will set it according |
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265 | * to the max size of the PCI FIFO. |
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266 | */ |
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267 | pci_cfg_w8(priv->pcidev, PCI_CACHE_LINE_SIZE, 0xff); |
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268 | |
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269 | /* Scan AMBA Plug&Play */ |
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270 | |
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271 | /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */ |
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272 | priv->amba_maps[0].size = bar0_size/2; |
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273 | priv->amba_maps[0].local_adr = bar0; |
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274 | priv->amba_maps[0].remote_adr = 0x80000000; |
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275 | |
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276 | /* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */ |
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277 | priv->amba_maps[1].size = devinfo->resources[1].size; |
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278 | priv->amba_maps[1].local_adr = devinfo->resources[1].address; |
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279 | priv->amba_maps[1].remote_adr = 0x40000000; |
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280 | |
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281 | /* Addresses not matching with map be untouched */ |
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282 | priv->amba_maps[2].size = 0xfffffff0; |
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283 | priv->amba_maps[2].local_adr = 0; |
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284 | priv->amba_maps[2].remote_adr = 0; |
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285 | |
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286 | /* Mark end of table */ |
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287 | priv->amba_maps[3].size=0; |
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288 | priv->amba_maps[3].local_adr = 0; |
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289 | priv->amba_maps[3].remote_adr = 0; |
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290 | |
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291 | /* Start AMBA PnP scan at first AHB bus */ |
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292 | ambapp_scan(&priv->abus, |
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293 | bar0 + (priv->version->amba_ioarea & ~0xf0000000), |
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294 | NULL, &priv->amba_maps[0]); |
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295 | |
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296 | /* Initialize Frequency of AMBA bus */ |
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297 | ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz); |
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298 | |
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299 | /* Point PAGE0 to start of APB area */ |
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300 | *page0 = 0x80000000; |
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301 | |
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302 | /* Find GRPCI controller */ |
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303 | tmp = (void *)ambapp_for_each(&priv->abus, |
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304 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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305 | VENDOR_GAISLER, GAISLER_PCIFBRG, |
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306 | ambapp_find_by_idx, NULL); |
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307 | if ( !tmp ) { |
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308 | return -3; |
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309 | } |
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310 | priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start; |
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311 | |
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312 | /* Set GRPCI mmap so that AMBA masters can access CPU-RAM over |
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313 | * the PCI window. |
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314 | */ |
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315 | priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) | |
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316 | (priv->ahbmst2pci_map & 0xf0000000); |
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317 | priv->grpci->page1 = 0x40000000; |
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318 | |
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319 | /* Find IRQ controller, Clear all current IRQs */ |
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320 | tmp = (void *)ambapp_for_each(&priv->abus, |
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321 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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322 | VENDOR_GAISLER, GAISLER_IRQMP, |
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323 | ambapp_find_by_idx, NULL); |
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324 | if ( !tmp ) { |
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325 | return -4; |
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326 | } |
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327 | priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start; |
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328 | /* Set up GR-RASTA-IO irq controller */ |
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329 | priv->irq->mask[0] = 0; |
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330 | priv->irq->iclear = 0xffff; |
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331 | priv->irq->ilevel = 0; |
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332 | |
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333 | /* DOWN streams translation table */ |
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334 | priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA"; |
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335 | priv->bus_maps_down[0].size = priv->amba_maps[0].size; |
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336 | priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr; |
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337 | priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr; |
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338 | |
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339 | priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA"; |
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340 | priv->bus_maps_down[1].size = priv->amba_maps[1].size; |
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341 | priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr; |
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342 | priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr; |
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343 | |
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344 | /* Mark end of translation table */ |
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345 | priv->bus_maps_down[2].size = 0; |
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346 | |
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347 | /* Find GRPCI controller AHB Slave interface */ |
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348 | tmp = (void *)ambapp_for_each(&priv->abus, |
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349 | (OPTIONS_ALL|OPTIONS_AHB_SLVS), |
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350 | VENDOR_GAISLER, GAISLER_PCIFBRG, |
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351 | ambapp_find_by_idx, NULL); |
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352 | if ( !tmp ) { |
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353 | return -5; |
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354 | } |
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355 | ahb = (struct ambapp_ahb_info *)tmp->devinfo; |
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356 | |
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357 | /* UP streams translation table */ |
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358 | priv->bus_maps_up[0].name = "AMBA GRPCI Window"; |
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359 | priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-IO board */ |
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360 | priv->bus_maps_up[0].from_adr = (void *)ahb->start[0]; |
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361 | priv->bus_maps_up[0].to_adr = (void *) |
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362 | (priv->ahbmst2pci_map & 0xf0000000); |
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363 | |
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364 | /* Mark end of translation table */ |
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365 | priv->bus_maps_up[1].size = 0; |
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366 | |
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367 | /* Successfully registered the RASTA board */ |
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368 | return 0; |
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369 | } |
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370 | |
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371 | int gr_rasta_io_hw_init2(struct gr_rasta_io_priv *priv) |
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372 | { |
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373 | /* Enable DMA by enabling PCI target as master */ |
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374 | pci_master_enable(priv->pcidev); |
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375 | |
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376 | return DRVMGR_OK; |
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377 | } |
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378 | |
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379 | /* Called when a PCI target is found with the PCI device and vendor ID |
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380 | * given in gr_rasta_io_ids[]. |
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381 | */ |
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382 | int gr_rasta_io_init1(struct drvmgr_dev *dev) |
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383 | { |
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384 | struct gr_rasta_io_priv *priv; |
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385 | struct pci_dev_info *devinfo; |
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386 | int status; |
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387 | uint32_t bar0, bar1, bar0_size, bar1_size; |
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388 | union drvmgr_key_value *value; |
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389 | |
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390 | priv = malloc(sizeof(struct gr_rasta_io_priv)); |
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391 | if ( !priv ) |
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392 | return DRVMGR_NOMEM; |
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393 | |
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394 | memset(priv, 0, sizeof(*priv)); |
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395 | dev->priv = priv; |
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396 | priv->dev = dev; |
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397 | |
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398 | /* Determine number of configurations */ |
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399 | if ( gr_rasta_io_resources_cnt == 0 ) { |
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400 | while ( gr_rasta_io_resources[gr_rasta_io_resources_cnt] ) |
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401 | gr_rasta_io_resources_cnt++; |
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402 | } |
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403 | |
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404 | /* Generate Device prefix */ |
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405 | |
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406 | strcpy(priv->prefix, "/dev/rastaio0"); |
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407 | priv->prefix[12] += dev->minor_drv; |
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408 | mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO); |
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409 | priv->prefix[13] = '/'; |
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410 | priv->prefix[14] = '\0'; |
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411 | |
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412 | priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo; |
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413 | priv->pcidev = devinfo->pcidev; |
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414 | bar0 = devinfo->resources[0].address; |
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415 | bar0_size = devinfo->resources[0].size; |
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416 | bar1 = devinfo->resources[1].address; |
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417 | bar1_size = devinfo->resources[1].size; |
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418 | printf("\n\n--- GR-RASTA-IO[%d] ---\n", dev->minor_drv); |
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419 | printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n", |
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420 | PCI_DEV_EXPAND(priv->pcidev)); |
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421 | printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n", |
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422 | devinfo->id.vendor, devinfo->id.device); |
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423 | printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1); |
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424 | printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1); |
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425 | printf(" IRQ: %d\n\n\n", devinfo->irq); |
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426 | |
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427 | /* all neccessary space assigned to GR-RASTA-IO target? */ |
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428 | if ((bar0_size == 0) || (bar1_size == 0)) |
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429 | return DRVMGR_ENORES; |
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430 | |
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431 | /* Let user override which PCI address the AHB masters of the |
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432 | * GR-RASTA-IO board access when doing DMA to CPU RAM. The AHB masters |
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433 | * access the PCI Window of the AMBA bus, the MSB 4-bits of that address |
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434 | * is translated according this config option before the address |
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435 | * goes out on the PCI bus. |
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436 | * Only the 4 MSB bits have an effect; |
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437 | */ |
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438 | value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT); |
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439 | if (value) |
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440 | priv->ahbmst2pci_map = value->i; |
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441 | else |
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442 | priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */ |
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443 | |
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444 | priv->genirq = genirq_init(16); |
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445 | if ( priv->genirq == NULL ) { |
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446 | free(priv); |
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447 | dev->priv = NULL; |
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448 | return DRVMGR_FAIL; |
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449 | } |
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450 | |
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451 | status = gr_rasta_io_hw_init(priv); |
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452 | if ( status != 0 ) { |
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453 | genirq_destroy(priv->genirq); |
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454 | free(priv); |
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455 | dev->priv = NULL; |
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456 | printf(" Failed to initialize GR-RASTA-IO HW: %d\n", status); |
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457 | return DRVMGR_FAIL; |
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458 | } |
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459 | |
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460 | /* Init amba bus */ |
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461 | priv->config.abus = &priv->abus; |
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462 | priv->config.ops = &ambapp_rasta_io_ops; |
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463 | priv->config.maps_up = &priv->bus_maps_up[0]; |
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464 | priv->config.maps_down = &priv->bus_maps_down[0]; |
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465 | if ( priv->dev->minor_drv < gr_rasta_io_resources_cnt ) { |
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466 | priv->config.resources = gr_rasta_io_resources[priv->dev->minor_drv]; |
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467 | } else { |
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468 | priv->config.resources = NULL; |
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469 | } |
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470 | |
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471 | /* Create and register AMBA PnP bus. */ |
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472 | return ambapp_bus_register(dev, &priv->config); |
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473 | } |
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474 | |
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475 | int gr_rasta_io_init2(struct drvmgr_dev *dev) |
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476 | { |
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477 | struct gr_rasta_io_priv *priv = dev->priv; |
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478 | |
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479 | /* Clear any old interrupt requests */ |
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480 | drvmgr_interrupt_clear(dev, 0); |
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481 | |
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482 | /* Enable System IRQ so that GR-RASTA-IO PCI target interrupt goes |
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483 | * through. |
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484 | * |
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485 | * It is important to enable it in stage init2. If interrupts were |
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486 | * enabled in init1 this might hang the system when more than one |
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487 | * PCI board is connected, this is because PCI interrupts might |
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488 | * be shared and PCI board 2 have not initialized and |
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489 | * might therefore drive interrupt already when entering init1(). |
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490 | */ |
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491 | drvmgr_interrupt_register( |
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492 | dev, |
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493 | 0, |
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494 | "gr_rasta_io", |
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495 | gr_rasta_io_isr, |
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496 | (void *)priv); |
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497 | |
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498 | return gr_rasta_io_hw_init2(priv); |
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499 | } |
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500 | |
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501 | int ambapp_rasta_io_int_register( |
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502 | struct drvmgr_dev *dev, |
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503 | int irq, |
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504 | const char *info, |
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505 | drvmgr_isr handler, |
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506 | void *arg) |
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507 | { |
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508 | struct gr_rasta_io_priv *priv = dev->parent->dev->priv; |
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509 | rtems_interrupt_level level; |
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510 | int status; |
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511 | |
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512 | rtems_interrupt_disable(level); |
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513 | |
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514 | status = genirq_register(priv->genirq, irq, handler, arg); |
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515 | if ( status == 0 ) { |
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516 | /* Clear IRQ for first registered handler */ |
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517 | priv->irq->iclear = (1<<irq); |
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518 | } else if ( status == 1 ) |
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519 | status = 0; |
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520 | |
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521 | if (status != 0) { |
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522 | rtems_interrupt_enable(level); |
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523 | return DRVMGR_FAIL; |
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524 | } |
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525 | |
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526 | status = genirq_enable(priv->genirq, irq, handler, arg); |
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527 | if ( status == 0 ) { |
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528 | /* Enable IRQ for first enabled handler only */ |
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529 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
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530 | } else if ( status == 1 ) |
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531 | status = 0; |
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532 | |
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533 | rtems_interrupt_enable(level); |
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534 | |
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535 | return status; |
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536 | } |
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537 | |
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538 | int ambapp_rasta_io_int_unregister( |
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539 | struct drvmgr_dev *dev, |
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540 | int irq, |
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541 | drvmgr_isr isr, |
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542 | void *arg) |
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543 | { |
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544 | struct gr_rasta_io_priv *priv = dev->parent->dev->priv; |
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545 | rtems_interrupt_level level; |
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546 | int status; |
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547 | |
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548 | rtems_interrupt_disable(level); |
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549 | |
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550 | status = genirq_disable(priv->genirq, irq, isr, arg); |
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551 | if ( status == 0 ) { |
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552 | /* Disable IRQ only when no enabled handler exists */ |
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553 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
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554 | } |
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555 | |
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556 | status = genirq_unregister(priv->genirq, irq, isr, arg); |
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557 | if ( status != 0 ) |
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558 | status = DRVMGR_FAIL; |
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559 | |
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560 | rtems_interrupt_enable(level); |
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561 | |
---|
562 | return status; |
---|
563 | } |
---|
564 | |
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565 | int ambapp_rasta_io_int_unmask( |
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566 | struct drvmgr_dev *dev, |
---|
567 | int irq) |
---|
568 | { |
---|
569 | struct gr_rasta_io_priv *priv = dev->parent->dev->priv; |
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570 | rtems_interrupt_level level; |
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571 | |
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572 | DBG("RASTA-IO IRQ %d: unmask\n", irq); |
---|
573 | |
---|
574 | if ( genirq_check(priv->genirq, irq) ) |
---|
575 | return DRVMGR_EINVAL; |
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576 | |
---|
577 | rtems_interrupt_disable(level); |
---|
578 | |
---|
579 | /* Enable IRQ for first enabled handler only */ |
---|
580 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
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581 | |
---|
582 | rtems_interrupt_enable(level); |
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583 | |
---|
584 | return DRVMGR_OK; |
---|
585 | } |
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586 | |
---|
587 | int ambapp_rasta_io_int_mask( |
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588 | struct drvmgr_dev *dev, |
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589 | int irq) |
---|
590 | { |
---|
591 | struct gr_rasta_io_priv *priv = dev->parent->dev->priv; |
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592 | rtems_interrupt_level level; |
---|
593 | |
---|
594 | DBG("RASTA-IO IRQ %d: mask\n", irq); |
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595 | |
---|
596 | if ( genirq_check(priv->genirq, irq) ) |
---|
597 | return DRVMGR_EINVAL; |
---|
598 | |
---|
599 | rtems_interrupt_disable(level); |
---|
600 | |
---|
601 | /* Disable/mask IRQ */ |
---|
602 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
---|
603 | |
---|
604 | rtems_interrupt_enable(level); |
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605 | |
---|
606 | return DRVMGR_OK; |
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607 | } |
---|
608 | |
---|
609 | int ambapp_rasta_io_int_clear( |
---|
610 | struct drvmgr_dev *dev, |
---|
611 | int irq) |
---|
612 | { |
---|
613 | struct gr_rasta_io_priv *priv = dev->parent->dev->priv; |
---|
614 | |
---|
615 | if ( genirq_check(priv->genirq, irq) ) |
---|
616 | return DRVMGR_EINVAL; |
---|
617 | |
---|
618 | priv->irq->iclear = (1<<irq); |
---|
619 | |
---|
620 | return DRVMGR_OK; |
---|
621 | } |
---|
622 | |
---|
623 | int ambapp_rasta_io_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params) |
---|
624 | { |
---|
625 | struct gr_rasta_io_priv *priv = dev->parent->dev->priv; |
---|
626 | |
---|
627 | /* Device name prefix pointer, skip /dev */ |
---|
628 | params->dev_prefix = &priv->prefix[5]; |
---|
629 | |
---|
630 | return 0; |
---|
631 | } |
---|
632 | |
---|
633 | void gr_rasta_io_print_dev(struct drvmgr_dev *dev, int options) |
---|
634 | { |
---|
635 | struct gr_rasta_io_priv *priv = dev->priv; |
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636 | struct pci_dev_info *devinfo = priv->devinfo; |
---|
637 | uint32_t bar0, bar1, bar0_size, bar1_size; |
---|
638 | |
---|
639 | /* Print */ |
---|
640 | printf("--- GR-RASTA-IO [bus 0x%x, dev 0x%x, fun 0x%x] ---\n", |
---|
641 | PCI_DEV_EXPAND(priv->pcidev)); |
---|
642 | |
---|
643 | bar0 = devinfo->resources[0].address; |
---|
644 | bar0_size = devinfo->resources[0].size; |
---|
645 | bar1 = devinfo->resources[1].address; |
---|
646 | bar1_size = devinfo->resources[1].size; |
---|
647 | |
---|
648 | printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1); |
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649 | printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1); |
---|
650 | printf(" IRQ REGS: 0x%x\n", (unsigned int)priv->irq); |
---|
651 | printf(" IRQ: %d\n", devinfo->irq); |
---|
652 | printf(" PCI REVISION: %d\n", devinfo->rev); |
---|
653 | printf(" FREQ: %d Hz\n", priv->version->amba_freq_hz); |
---|
654 | printf(" IMASK: 0x%08x\n", priv->irq->mask[0]); |
---|
655 | printf(" IPEND: 0x%08x\n", priv->irq->ipend); |
---|
656 | |
---|
657 | /* Print amba config */ |
---|
658 | if ( options & RASTA_IO_OPTIONS_AMBA ) { |
---|
659 | ambapp_print(&priv->abus, 10); |
---|
660 | } |
---|
661 | |
---|
662 | #if 0 |
---|
663 | /* Print IRQ handlers and their arguments */ |
---|
664 | if ( options & RASTA_IO_OPTIONS_IRQ ) { |
---|
665 | int i; |
---|
666 | for(i=0; i<16; i++) { |
---|
667 | printf(" IRQ[%02d]: 0x%x, arg: 0x%x\n", |
---|
668 | i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg); |
---|
669 | } |
---|
670 | } |
---|
671 | #endif |
---|
672 | } |
---|
673 | |
---|
674 | void gr_rasta_io_print(int options) |
---|
675 | { |
---|
676 | struct pci_drv_info *drv = &gr_rasta_io_info; |
---|
677 | struct drvmgr_dev *dev; |
---|
678 | |
---|
679 | dev = drv->general.dev; |
---|
680 | while(dev) { |
---|
681 | gr_rasta_io_print_dev(dev, options); |
---|
682 | dev = dev->next_in_drv; |
---|
683 | } |
---|
684 | } |
---|