source: rtems/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c @ 3c236cc

4.115
Last change on this file since 3c236cc was 819de55b, checked in by Daniel Hellstrom <daniel@…>, on 03/18/13 at 07:29:39

PCI-RASTA: set GRPCI1 target cache-line-size to avoid poor performance

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File size: 17.8 KB
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1/*  GR-RASTA-IO PCI Target driver.
2 *
3 *  COPYRIGHT (c) 2008.
4 *  Cobham Gaisler AB.
5 *
6 *  Configures the GR-RASTA-IO interface PCI board.
7 *  This driver provides a AMBA PnP bus by using the general part
8 *  of the AMBA PnP bus driver (ambapp_bus.c).
9 *
10 *  Driver resources for the AMBA PnP bus provided can be set using
11 *  gr_rasta_io_set_resources().
12 *
13 *  The license and distribution terms for this file may be
14 *  found in found in the file LICENSE in this distribution or at
15 *  http://www.rtems.com/license/LICENSE.
16 */
17
18#include <stdio.h>
19#include <stdlib.h>
20#include <string.h>
21#include <sys/types.h>
22#include <sys/stat.h>
23
24#include <bsp.h>
25#include <rtems/bspIo.h>
26#include <pci.h>
27
28#include <ambapp.h>
29#include <grlib.h>
30#include <drvmgr/drvmgr.h>
31#include <drvmgr/ambapp_bus.h>
32#include <drvmgr/pci_bus.h>
33#include <genirq.h>
34
35#include <gr_rasta_io.h>
36
37/* Determines which PCI address the AHB masters will access, it should be
38 * set so that the masters can access the CPU RAM. Default is base of CPU RAM,
39 * CPU RAM is mapped 1:1 to PCI space.
40 */
41extern unsigned int _RAM_START;
42#define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000)
43
44/* Offset from 0x80000000 (dual bus version) */
45#define AHB1_BASE_ADDR 0x80000000
46#define AHB1_IOAREA_BASE_ADDR 0x80100000
47
48/* #define DEBUG 1 */
49
50#ifdef DEBUG
51#define DBG(x...) printk(x)
52#else
53#define DBG(x...)
54#endif
55
56/* PCI ID */
57#define PCIID_VENDOR_GAISLER            0x1AC8
58
59int gr_rasta_io_init1(struct drvmgr_dev *dev);
60int gr_rasta_io_init2(struct drvmgr_dev *dev);
61
62struct grpci_regs {
63        volatile unsigned int cfg_stat;
64        volatile unsigned int bar0;
65        volatile unsigned int page0;
66        volatile unsigned int bar1;
67        volatile unsigned int page1;
68        volatile unsigned int iomap;
69        volatile unsigned int stat_cmd;
70};
71
72struct gr_rasta_io_ver {
73        const unsigned int      amba_freq_hz;   /* The frequency */
74        const unsigned int      amba_ioarea;    /* The address where the PnP IOAREA starts at */
75};
76
77/* Private data structure for driver */
78struct gr_rasta_io_priv {
79        /* Driver management */
80        struct drvmgr_dev       *dev;
81        char                            prefix[16];
82
83        /* PCI */
84        pci_dev_t                       pcidev;
85        struct pci_dev_info             *devinfo;
86        uint32_t                        ahbmst2pci_map;
87
88        /* IRQ */
89        genirq_t                        genirq;
90
91        /* GR-RASTA-IO */
92        struct gr_rasta_io_ver          *version;
93        struct irqmp_regs               *irq;
94        struct grpci_regs               *grpci;
95        struct drvmgr_map_entry         bus_maps_down[3];
96        struct drvmgr_map_entry         bus_maps_up[2];
97
98        /* AMBA Plug&Play information on GR-RASTA-IO */
99        struct ambapp_bus               abus;
100        struct ambapp_mmap              amba_maps[4];
101        struct ambapp_config            config;
102};
103
104struct gr_rasta_io_ver gr_rasta_io_ver0 = {
105        .amba_freq_hz           = 30000000,
106        .amba_ioarea            = 0x80100000,
107};
108
109struct gr_rasta_io_ver gr_rasta_io_ver1 = {
110        .amba_freq_hz           = 50000000,
111        .amba_ioarea            = 0x80100000,
112};
113
114int ambapp_rasta_io_int_register(
115        struct drvmgr_dev *dev,
116        int irq,
117        const char *info,
118        drvmgr_isr handler,
119        void *arg);
120int ambapp_rasta_io_int_unregister(
121        struct drvmgr_dev *dev,
122        int irq,
123        drvmgr_isr handler,
124        void *arg);
125int ambapp_rasta_io_int_unmask(
126        struct drvmgr_dev *dev,
127        int irq);
128int ambapp_rasta_io_int_mask(
129        struct drvmgr_dev *dev,
130        int irq);
131int ambapp_rasta_io_int_clear(
132        struct drvmgr_dev *dev,
133        int irq);
134int ambapp_rasta_io_get_params(
135        struct drvmgr_dev *dev,
136        struct drvmgr_bus_params *params);
137
138struct ambapp_ops ambapp_rasta_io_ops = {
139        .int_register = ambapp_rasta_io_int_register,
140        .int_unregister = ambapp_rasta_io_int_unregister,
141        .int_unmask = ambapp_rasta_io_int_unmask,
142        .int_mask = ambapp_rasta_io_int_mask,
143        .int_clear = ambapp_rasta_io_int_clear,
144        .get_params = ambapp_rasta_io_get_params
145};
146
147struct drvmgr_drv_ops gr_rasta_io_ops =
148{
149        .init = {gr_rasta_io_init1, gr_rasta_io_init2, NULL, NULL},
150        .remove = NULL,
151        .info = NULL
152};
153
154struct pci_dev_id_match gr_rasta_io_ids[] =
155{
156        PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_IO),
157        PCIID_DEVVEND(PCIID_VENDOR_GAISLER_OLD, PCIID_DEVICE_GR_RASTA_IO_OLD),
158        PCIID_END_TABLE /* Mark end of table */
159};
160
161struct pci_drv_info gr_rasta_io_info =
162{
163        {
164                DRVMGR_OBJ_DRV,                 /* Driver */
165                NULL,                           /* Next driver */
166                NULL,                           /* Device list */
167                DRIVER_PCI_GAISLER_RASTAIO_ID,  /* Driver ID */
168                "GR-RASTA-IO_DRV",              /* Driver Name */
169                DRVMGR_BUS_TYPE_PCI,            /* Bus Type */
170                &gr_rasta_io_ops,
171                NULL,                           /* Funcs */
172                0,                              /* No devices yet */
173                0,
174        },
175        &gr_rasta_io_ids[0]
176};
177
178/* Driver resources configuration for the AMBA bus on the GR-RASTA-IO board.
179 * It is declared weak so that the user may override it from the project file,
180 * if the default settings are not enough.
181 *
182 * The configuration consists of an array of configuration pointers, each
183 * pointer determine the configuration of one GR-RASTA-IO board. Pointer
184 * zero is for board0, pointer 1 for board1 and so on.
185 *
186 * The array must end with a NULL pointer.
187 */
188struct drvmgr_bus_res *gr_rasta_io_resources[] __attribute__((weak)) =
189{
190        NULL
191};
192int gr_rasta_io_resources_cnt = 0;
193
194void gr_rasta_io_register_drv(void)
195{
196        DBG("Registering GR-RASTA-IO PCI driver\n");
197        drvmgr_drv_register(&gr_rasta_io_info.general);
198}
199
200void gr_rasta_io_isr (void *arg)
201{
202        struct gr_rasta_io_priv *priv = arg;
203        unsigned int status, tmp;
204        int irq;
205        tmp = status = priv->irq->ipend;
206
207        /* DBG("GR-RASTA-IO: IRQ 0x%x\n",status); */
208
209        for(irq=0; irq<16; irq++) {
210                if ( status & (1<<irq) ) {
211                        genirq_doirq(priv->genirq, irq);
212                        priv->irq->iclear = (1<<irq);
213                        status &= ~(1<<irq);
214                        if ( status == 0 )
215                                break;
216                }
217        }
218
219        /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */
220        if ( tmp )
221                drvmgr_interrupt_clear(priv->dev, 0);
222
223        DBG("RASTA-IO-IRQ: 0x%x\n", tmp);
224}
225
226int gr_rasta_io_hw_init(struct gr_rasta_io_priv *priv)
227{
228        unsigned int *page0 = NULL;
229        struct ambapp_dev *tmp;
230        int status;
231        struct ambapp_ahb_info *ahb;
232        struct pci_dev_info *devinfo = priv->devinfo;
233        uint32_t bar0, bar0_size;
234
235        /* Select version of GR-RASTA-IO board */
236        switch (devinfo->rev) {
237                case 0:
238                        priv->version = &gr_rasta_io_ver0;
239                        break;
240                case 1:
241                        priv->version = &gr_rasta_io_ver1;
242                        break;
243                default:
244                        return -2;
245        }
246
247        bar0 = devinfo->resources[0].address;
248        bar0_size = devinfo->resources[0].size;
249        page0 = (unsigned int *)(bar0 + bar0_size/2);
250
251        /* Point PAGE0 to start of Plug and Play information */
252        *page0 = priv->version->amba_ioarea & 0xf0000000;
253
254#if 0
255        {
256                uint32_t data;
257                /* set parity error response */
258                pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data);
259                pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
260        }
261#endif
262
263        /* Setup cache line size. Default cache line size will result in
264         * poor performance (256 word fetches), 0xff will set it according
265         * to the max size of the PCI FIFO.
266         */
267        pci_cfg_w8(priv->pcidev, PCI_CACHE_LINE_SIZE, 0xff);
268
269        /* Scan AMBA Plug&Play */
270
271        /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */
272        priv->amba_maps[0].size = bar0_size/2;
273        priv->amba_maps[0].local_adr = bar0;
274        priv->amba_maps[0].remote_adr = 0x80000000;
275
276        /* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */
277        priv->amba_maps[1].size = devinfo->resources[1].size;
278        priv->amba_maps[1].local_adr = devinfo->resources[1].address;
279        priv->amba_maps[1].remote_adr = 0x40000000;
280
281        /* Addresses not matching with map be untouched */
282        priv->amba_maps[2].size = 0xfffffff0;
283        priv->amba_maps[2].local_adr = 0;
284        priv->amba_maps[2].remote_adr = 0;
285
286        /* Mark end of table */
287        priv->amba_maps[3].size=0;
288        priv->amba_maps[3].local_adr = 0;
289        priv->amba_maps[3].remote_adr = 0;
290
291        /* Start AMBA PnP scan at first AHB bus */
292        ambapp_scan(&priv->abus,
293                        bar0 + (priv->version->amba_ioarea & ~0xf0000000),
294                        NULL, &priv->amba_maps[0]);
295
296        /* Initialize Frequency of AMBA bus */
297        ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz);
298
299        /* Point PAGE0 to start of APB area */
300        *page0 = 0x80000000;   
301
302        /* Find GRPCI controller */
303        tmp = (void *)ambapp_for_each(&priv->abus,
304                                        (OPTIONS_ALL|OPTIONS_APB_SLVS),
305                                        VENDOR_GAISLER, GAISLER_PCIFBRG,
306                                        ambapp_find_by_idx, NULL);
307        if ( !tmp ) {
308                return -3;
309        }
310        priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start;
311
312        /* Set GRPCI mmap so that AMBA masters can access CPU-RAM over
313         * the PCI window.
314         */
315        priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) |
316                                (priv->ahbmst2pci_map & 0xf0000000);
317        priv->grpci->page1 = 0x40000000;
318
319        /* Find IRQ controller, Clear all current IRQs */
320        tmp = (void *)ambapp_for_each(&priv->abus,
321                                        (OPTIONS_ALL|OPTIONS_APB_SLVS),
322                                        VENDOR_GAISLER, GAISLER_IRQMP,
323                                        ambapp_find_by_idx, NULL);
324        if ( !tmp ) {
325                return -4;
326        }
327        priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
328        /* Set up GR-RASTA-IO irq controller */
329        priv->irq->mask[0] = 0;
330        priv->irq->iclear = 0xffff;
331        priv->irq->ilevel = 0;
332
333        /* DOWN streams translation table */
334        priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
335        priv->bus_maps_down[0].size = priv->amba_maps[0].size;
336        priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
337        priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
338
339        priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA";
340        priv->bus_maps_down[1].size = priv->amba_maps[1].size;
341        priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr;
342        priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr;
343
344        /* Mark end of translation table */
345        priv->bus_maps_down[2].size = 0;
346
347        /* Find GRPCI controller AHB Slave interface */
348        tmp = (void *)ambapp_for_each(&priv->abus,
349                                        (OPTIONS_ALL|OPTIONS_AHB_SLVS),
350                                        VENDOR_GAISLER, GAISLER_PCIFBRG,
351                                        ambapp_find_by_idx, NULL);
352        if ( !tmp ) {
353                return -5;
354        }
355        ahb = (struct ambapp_ahb_info *)tmp->devinfo;
356
357        /* UP streams translation table */
358        priv->bus_maps_up[0].name = "AMBA GRPCI Window";
359        priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-IO board */
360        priv->bus_maps_up[0].from_adr = (void *)ahb->start[0];
361        priv->bus_maps_up[0].to_adr = (void *)
362                                        (priv->ahbmst2pci_map & 0xf0000000);
363
364        /* Mark end of translation table */
365        priv->bus_maps_up[1].size = 0;
366
367        /* Successfully registered the RASTA board */
368        return 0;
369}
370
371int gr_rasta_io_hw_init2(struct gr_rasta_io_priv *priv)
372{
373        /* Enable DMA by enabling PCI target as master */
374        pci_master_enable(priv->pcidev);
375
376        return DRVMGR_OK;
377}
378
379/* Called when a PCI target is found with the PCI device and vendor ID
380 * given in gr_rasta_io_ids[].
381 */
382int gr_rasta_io_init1(struct drvmgr_dev *dev)
383{
384        struct gr_rasta_io_priv *priv;
385        struct pci_dev_info *devinfo;
386        int status;
387        uint32_t bar0, bar1, bar0_size, bar1_size;
388        union drvmgr_key_value *value;
389
390        priv = malloc(sizeof(struct gr_rasta_io_priv));
391        if ( !priv )
392                return DRVMGR_NOMEM;
393
394        memset(priv, 0, sizeof(*priv));
395        dev->priv = priv;
396        priv->dev = dev;
397
398        /* Determine number of configurations */
399        if ( gr_rasta_io_resources_cnt == 0 ) {
400                while ( gr_rasta_io_resources[gr_rasta_io_resources_cnt] )
401                        gr_rasta_io_resources_cnt++;
402        }
403
404        /* Generate Device prefix */
405
406        strcpy(priv->prefix, "/dev/rastaio0");
407        priv->prefix[12] += dev->minor_drv;
408        mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
409        priv->prefix[13] = '/';
410        priv->prefix[14] = '\0';
411
412        priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
413        priv->pcidev = devinfo->pcidev;
414        bar0 = devinfo->resources[0].address;
415        bar0_size = devinfo->resources[0].size;
416        bar1 = devinfo->resources[1].address;
417        bar1_size = devinfo->resources[1].size;
418        printf("\n\n--- GR-RASTA-IO[%d] ---\n", dev->minor_drv);
419        printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
420                PCI_DEV_EXPAND(priv->pcidev));
421        printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n",
422                devinfo->id.vendor, devinfo->id.device);
423        printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
424        printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
425        printf(" IRQ: %d\n\n\n", devinfo->irq);
426
427        /* all neccessary space assigned to GR-RASTA-IO target? */
428        if ((bar0_size == 0) || (bar1_size == 0))
429                return DRVMGR_ENORES;
430
431        /* Let user override which PCI address the AHB masters of the
432         * GR-RASTA-IO board access when doing DMA to CPU RAM. The AHB masters
433         * access the PCI Window of the AMBA bus, the MSB 4-bits of that address
434         * is translated according this config option before the address
435         * goes out on the PCI bus.
436         * Only the 4 MSB bits have an effect;
437         */
438        value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT);
439        if (value)
440                priv->ahbmst2pci_map = value->i;
441        else
442                priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */     
443
444        priv->genirq = genirq_init(16);
445        if ( priv->genirq == NULL ) {
446                free(priv);
447                dev->priv = NULL;
448                return DRVMGR_FAIL;
449        }
450
451        status = gr_rasta_io_hw_init(priv);
452        if ( status != 0 ) {
453                genirq_destroy(priv->genirq);
454                free(priv);
455                dev->priv = NULL;
456                printf(" Failed to initialize GR-RASTA-IO HW: %d\n", status);
457                return DRVMGR_FAIL;
458        }
459
460        /* Init amba bus */
461        priv->config.abus = &priv->abus;
462        priv->config.ops = &ambapp_rasta_io_ops;
463        priv->config.maps_up = &priv->bus_maps_up[0];
464        priv->config.maps_down = &priv->bus_maps_down[0];
465        if ( priv->dev->minor_drv < gr_rasta_io_resources_cnt ) {
466                priv->config.resources = gr_rasta_io_resources[priv->dev->minor_drv];
467        } else {
468                priv->config.resources = NULL;
469        }
470
471        /* Create and register AMBA PnP bus. */
472        return ambapp_bus_register(dev, &priv->config);
473}
474
475int gr_rasta_io_init2(struct drvmgr_dev *dev)
476{
477        struct gr_rasta_io_priv *priv = dev->priv;
478
479        /* Clear any old interrupt requests */
480        drvmgr_interrupt_clear(dev, 0);
481
482        /* Enable System IRQ so that GR-RASTA-IO PCI target interrupt goes
483         * through.
484         *
485         * It is important to enable it in stage init2. If interrupts were
486         * enabled in init1 this might hang the system when more than one
487         * PCI board is connected, this is because PCI interrupts might
488         * be shared and PCI board 2 have not initialized and
489         * might therefore drive interrupt already when entering init1().
490         */
491        drvmgr_interrupt_register(
492                dev,
493                0,
494                "gr_rasta_io",
495                gr_rasta_io_isr,
496                (void *)priv);
497
498        return gr_rasta_io_hw_init2(priv);
499}
500
501int ambapp_rasta_io_int_register(
502        struct drvmgr_dev *dev,
503        int irq,
504        const char *info,
505        drvmgr_isr handler,
506        void *arg)
507{
508        struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
509        rtems_interrupt_level level;
510        int status;
511
512        rtems_interrupt_disable(level);
513
514        status = genirq_register(priv->genirq, irq, handler, arg);
515        if ( status == 0 ) {
516                /* Clear IRQ for first registered handler */
517                priv->irq->iclear = (1<<irq);
518        } else if ( status == 1 )
519                status = 0;
520
521        if (status != 0) {
522                rtems_interrupt_enable(level);
523                return DRVMGR_FAIL;
524        }
525
526        status = genirq_enable(priv->genirq, irq, handler, arg);
527        if ( status == 0 ) {
528                /* Enable IRQ for first enabled handler only */
529                priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
530        } else if ( status == 1 )
531                status = 0;
532
533        rtems_interrupt_enable(level);
534
535        return status;
536}
537
538int ambapp_rasta_io_int_unregister(
539        struct drvmgr_dev *dev,
540        int irq,
541        drvmgr_isr isr,
542        void *arg)
543{
544        struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
545        rtems_interrupt_level level;
546        int status;
547
548        rtems_interrupt_disable(level);
549
550        status = genirq_disable(priv->genirq, irq, isr, arg);
551        if ( status == 0 ) {
552                /* Disable IRQ only when no enabled handler exists */
553                priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
554        }
555
556        status = genirq_unregister(priv->genirq, irq, isr, arg);
557        if ( status != 0 )
558                status = DRVMGR_FAIL;
559
560        rtems_interrupt_enable(level);
561
562        return status;
563}
564
565int ambapp_rasta_io_int_unmask(
566        struct drvmgr_dev *dev,
567        int irq)
568{
569        struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
570        rtems_interrupt_level level;
571
572        DBG("RASTA-IO IRQ %d: unmask\n", irq);
573
574        if ( genirq_check(priv->genirq, irq) )
575                return DRVMGR_EINVAL;
576
577        rtems_interrupt_disable(level);
578
579        /* Enable IRQ for first enabled handler only */
580        priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
581
582        rtems_interrupt_enable(level);
583
584        return DRVMGR_OK;
585}
586
587int ambapp_rasta_io_int_mask(
588        struct drvmgr_dev *dev,
589        int irq)
590{
591        struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
592        rtems_interrupt_level level;
593
594        DBG("RASTA-IO IRQ %d: mask\n", irq);
595
596        if ( genirq_check(priv->genirq, irq) )
597                return DRVMGR_EINVAL;
598
599        rtems_interrupt_disable(level);
600
601        /* Disable/mask IRQ */
602        priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
603
604        rtems_interrupt_enable(level);
605
606        return DRVMGR_OK;
607}
608
609int ambapp_rasta_io_int_clear(
610        struct drvmgr_dev *dev,
611        int irq)
612{
613        struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
614
615        if ( genirq_check(priv->genirq, irq) )
616                return DRVMGR_EINVAL;
617
618        priv->irq->iclear = (1<<irq);
619
620        return DRVMGR_OK;
621}
622
623int ambapp_rasta_io_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
624{
625        struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
626
627        /* Device name prefix pointer, skip /dev */
628        params->dev_prefix = &priv->prefix[5];
629
630        return 0;
631}
632
633void gr_rasta_io_print_dev(struct drvmgr_dev *dev, int options)
634{
635        struct gr_rasta_io_priv *priv = dev->priv;
636        struct pci_dev_info *devinfo = priv->devinfo;
637        uint32_t bar0, bar1, bar0_size, bar1_size;
638
639        /* Print */
640        printf("--- GR-RASTA-IO [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
641                PCI_DEV_EXPAND(priv->pcidev));
642
643        bar0 = devinfo->resources[0].address;
644        bar0_size = devinfo->resources[0].size;
645        bar1 = devinfo->resources[1].address;
646        bar1_size = devinfo->resources[1].size;
647
648        printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
649        printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
650        printf(" IRQ REGS:        0x%x\n", (unsigned int)priv->irq);
651        printf(" IRQ:             %d\n", devinfo->irq);
652        printf(" PCI REVISION:    %d\n", devinfo->rev);
653        printf(" FREQ:            %d Hz\n", priv->version->amba_freq_hz);
654        printf(" IMASK:           0x%08x\n", priv->irq->mask[0]);
655        printf(" IPEND:           0x%08x\n", priv->irq->ipend);
656
657        /* Print amba config */
658        if ( options & RASTA_IO_OPTIONS_AMBA ) {
659                ambapp_print(&priv->abus, 10);
660        }
661
662#if 0
663        /* Print IRQ handlers and their arguments */
664        if ( options & RASTA_IO_OPTIONS_IRQ ) {
665                int i;
666                for(i=0; i<16; i++) {
667                        printf(" IRQ[%02d]:         0x%x, arg: 0x%x\n",
668                                i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg);
669                }
670        }
671#endif
672}
673
674void gr_rasta_io_print(int options)
675{
676        struct pci_drv_info *drv = &gr_rasta_io_info;
677        struct drvmgr_dev *dev;
678
679        dev = drv->general.dev;
680        while(dev) {
681                gr_rasta_io_print_dev(dev, options);
682                dev = dev->next_in_drv;
683        }
684}
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