[e67b2b8d] | 1 | /* GR-RASTA-IO PCI Target driver. |
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| 2 | * |
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| 3 | * COPYRIGHT (c) 2008. |
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| 4 | * Cobham Gaisler AB. |
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| 5 | * |
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| 6 | * Configures the GR-RASTA-IO interface PCI board. |
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| 7 | * This driver provides a AMBA PnP bus by using the general part |
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| 8 | * of the AMBA PnP bus driver (ambapp_bus.c). |
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| 9 | * |
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| 10 | * Driver resources for the AMBA PnP bus provided can be set using |
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| 11 | * gr_rasta_io_set_resources(). |
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| 12 | * |
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| 13 | * The license and distribution terms for this file may be |
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| 14 | * found in found in the file LICENSE in this distribution or at |
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| 15 | * http://www.rtems.com/license/LICENSE. |
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| 16 | */ |
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| 17 | |
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| 18 | #include <stdio.h> |
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| 19 | #include <stdlib.h> |
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| 20 | #include <string.h> |
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| 21 | #include <sys/types.h> |
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| 22 | #include <sys/stat.h> |
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| 23 | |
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| 24 | #include <bsp.h> |
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| 25 | #include <rtems/bspIo.h> |
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| 26 | #include <pci.h> |
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| 27 | |
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| 28 | #include <ambapp.h> |
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| 29 | #include <grlib.h> |
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| 30 | #include <drvmgr/drvmgr.h> |
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| 31 | #include <drvmgr/ambapp_bus.h> |
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| 32 | #include <drvmgr/pci_bus.h> |
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[960aebf] | 33 | #include <drvmgr/bspcommon.h> |
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[5823bae8] | 34 | #include <bsp/genirq.h> |
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[e67b2b8d] | 35 | |
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[5823bae8] | 36 | #include <bsp/gr_rasta_io.h> |
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[e67b2b8d] | 37 | |
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| 38 | /* Determines which PCI address the AHB masters will access, it should be |
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| 39 | * set so that the masters can access the CPU RAM. Default is base of CPU RAM, |
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| 40 | * CPU RAM is mapped 1:1 to PCI space. |
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| 41 | */ |
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| 42 | extern unsigned int _RAM_START; |
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| 43 | #define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000) |
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| 44 | |
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| 45 | /* Offset from 0x80000000 (dual bus version) */ |
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| 46 | #define AHB1_BASE_ADDR 0x80000000 |
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| 47 | #define AHB1_IOAREA_BASE_ADDR 0x80100000 |
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[80b9c8ac] | 48 | #define AHB1_IOAREA_OFS (AHB1_IOAREA_BASE_ADDR - AHB1_BASE_ADDR) |
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| 49 | |
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| 50 | /* Second revision constants (GRPCI2) */ |
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| 51 | #define GRPCI2_BAR0_TO_AHB_MAP 0x04 /* Fixme */ |
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| 52 | #define GRPCI2_BAR1_TO_AHB_MAP 0x08 /* Fixme */ |
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| 53 | #define GRPCI2_PCI_CONFIG 0x20 /* Fixme */ |
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| 54 | |
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[e67b2b8d] | 55 | |
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| 56 | /* #define DEBUG 1 */ |
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| 57 | |
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| 58 | #ifdef DEBUG |
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| 59 | #define DBG(x...) printk(x) |
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| 60 | #else |
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| 61 | #define DBG(x...) |
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| 62 | #endif |
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| 63 | |
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| 64 | /* PCI ID */ |
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| 65 | #define PCIID_VENDOR_GAISLER 0x1AC8 |
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| 66 | |
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| 67 | int gr_rasta_io_init1(struct drvmgr_dev *dev); |
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| 68 | int gr_rasta_io_init2(struct drvmgr_dev *dev); |
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[960aebf] | 69 | void gr_rasta_io_isr (void *arg); |
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[e67b2b8d] | 70 | |
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| 71 | struct grpci_regs { |
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| 72 | volatile unsigned int cfg_stat; |
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| 73 | volatile unsigned int bar0; |
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| 74 | volatile unsigned int page0; |
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| 75 | volatile unsigned int bar1; |
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| 76 | volatile unsigned int page1; |
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| 77 | volatile unsigned int iomap; |
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| 78 | volatile unsigned int stat_cmd; |
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| 79 | }; |
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| 80 | |
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[80b9c8ac] | 81 | struct grpci2_regs { |
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| 82 | volatile unsigned int ctrl; |
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| 83 | volatile unsigned int statcap; |
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| 84 | volatile unsigned int pcimstprefetch; |
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| 85 | volatile unsigned int ahbtopciiomap; |
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| 86 | volatile unsigned int dmactrl; |
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| 87 | volatile unsigned int dmadesc; |
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| 88 | volatile unsigned int dmachanact; |
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| 89 | volatile unsigned int reserved; |
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| 90 | volatile unsigned int pcibartoahb[6]; |
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| 91 | volatile unsigned int reserved2[2]; |
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| 92 | volatile unsigned int ahbtopcimemmap[16]; |
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| 93 | volatile unsigned int trcctrl; |
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| 94 | volatile unsigned int trccntmode; |
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| 95 | volatile unsigned int trcadpat; |
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| 96 | volatile unsigned int trcadmask; |
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| 97 | volatile unsigned int trcctrlsigpat; |
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| 98 | volatile unsigned int trcctrlsigmask; |
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| 99 | volatile unsigned int trcadstate; |
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| 100 | volatile unsigned int trcctrlsigstate; |
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| 101 | }; |
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| 102 | |
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[e67b2b8d] | 103 | struct gr_rasta_io_ver { |
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| 104 | const unsigned int amba_freq_hz; /* The frequency */ |
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| 105 | const unsigned int amba_ioarea; /* The address where the PnP IOAREA starts at */ |
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| 106 | }; |
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| 107 | |
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| 108 | /* Private data structure for driver */ |
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| 109 | struct gr_rasta_io_priv { |
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| 110 | /* Driver management */ |
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| 111 | struct drvmgr_dev *dev; |
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| 112 | char prefix[16]; |
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| 113 | |
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| 114 | /* PCI */ |
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| 115 | pci_dev_t pcidev; |
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| 116 | struct pci_dev_info *devinfo; |
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| 117 | uint32_t ahbmst2pci_map; |
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| 118 | |
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| 119 | /* IRQ */ |
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| 120 | genirq_t genirq; |
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| 121 | |
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| 122 | /* GR-RASTA-IO */ |
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| 123 | struct gr_rasta_io_ver *version; |
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| 124 | struct irqmp_regs *irq; |
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| 125 | struct grpci_regs *grpci; |
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[80b9c8ac] | 126 | struct grpci2_regs *grpci2; |
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[e67b2b8d] | 127 | struct drvmgr_map_entry bus_maps_down[3]; |
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| 128 | struct drvmgr_map_entry bus_maps_up[2]; |
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| 129 | |
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| 130 | /* AMBA Plug&Play information on GR-RASTA-IO */ |
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| 131 | struct ambapp_bus abus; |
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| 132 | struct ambapp_mmap amba_maps[4]; |
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| 133 | struct ambapp_config config; |
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| 134 | }; |
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| 135 | |
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| 136 | struct gr_rasta_io_ver gr_rasta_io_ver0 = { |
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| 137 | .amba_freq_hz = 30000000, |
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| 138 | .amba_ioarea = 0x80100000, |
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| 139 | }; |
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| 140 | |
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| 141 | struct gr_rasta_io_ver gr_rasta_io_ver1 = { |
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| 142 | .amba_freq_hz = 50000000, |
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| 143 | .amba_ioarea = 0x80100000, |
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| 144 | }; |
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| 145 | |
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| 146 | int ambapp_rasta_io_int_register( |
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| 147 | struct drvmgr_dev *dev, |
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| 148 | int irq, |
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| 149 | const char *info, |
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| 150 | drvmgr_isr handler, |
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| 151 | void *arg); |
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| 152 | int ambapp_rasta_io_int_unregister( |
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| 153 | struct drvmgr_dev *dev, |
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| 154 | int irq, |
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| 155 | drvmgr_isr handler, |
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| 156 | void *arg); |
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| 157 | int ambapp_rasta_io_int_unmask( |
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| 158 | struct drvmgr_dev *dev, |
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| 159 | int irq); |
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| 160 | int ambapp_rasta_io_int_mask( |
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| 161 | struct drvmgr_dev *dev, |
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| 162 | int irq); |
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| 163 | int ambapp_rasta_io_int_clear( |
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| 164 | struct drvmgr_dev *dev, |
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| 165 | int irq); |
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| 166 | int ambapp_rasta_io_get_params( |
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| 167 | struct drvmgr_dev *dev, |
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| 168 | struct drvmgr_bus_params *params); |
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| 169 | |
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| 170 | struct ambapp_ops ambapp_rasta_io_ops = { |
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| 171 | .int_register = ambapp_rasta_io_int_register, |
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| 172 | .int_unregister = ambapp_rasta_io_int_unregister, |
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| 173 | .int_unmask = ambapp_rasta_io_int_unmask, |
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| 174 | .int_mask = ambapp_rasta_io_int_mask, |
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| 175 | .int_clear = ambapp_rasta_io_int_clear, |
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| 176 | .get_params = ambapp_rasta_io_get_params |
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| 177 | }; |
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| 178 | |
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| 179 | struct drvmgr_drv_ops gr_rasta_io_ops = |
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| 180 | { |
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| 181 | .init = {gr_rasta_io_init1, gr_rasta_io_init2, NULL, NULL}, |
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| 182 | .remove = NULL, |
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| 183 | .info = NULL |
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| 184 | }; |
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| 185 | |
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| 186 | struct pci_dev_id_match gr_rasta_io_ids[] = |
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| 187 | { |
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| 188 | PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_IO), |
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| 189 | PCIID_DEVVEND(PCIID_VENDOR_GAISLER_OLD, PCIID_DEVICE_GR_RASTA_IO_OLD), |
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| 190 | PCIID_END_TABLE /* Mark end of table */ |
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| 191 | }; |
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| 192 | |
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| 193 | struct pci_drv_info gr_rasta_io_info = |
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| 194 | { |
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| 195 | { |
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| 196 | DRVMGR_OBJ_DRV, /* Driver */ |
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| 197 | NULL, /* Next driver */ |
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| 198 | NULL, /* Device list */ |
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| 199 | DRIVER_PCI_GAISLER_RASTAIO_ID, /* Driver ID */ |
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| 200 | "GR-RASTA-IO_DRV", /* Driver Name */ |
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| 201 | DRVMGR_BUS_TYPE_PCI, /* Bus Type */ |
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| 202 | &gr_rasta_io_ops, |
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| 203 | NULL, /* Funcs */ |
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| 204 | 0, /* No devices yet */ |
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| 205 | 0, |
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| 206 | }, |
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| 207 | &gr_rasta_io_ids[0] |
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| 208 | }; |
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| 209 | |
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| 210 | /* Driver resources configuration for the AMBA bus on the GR-RASTA-IO board. |
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| 211 | * It is declared weak so that the user may override it from the project file, |
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| 212 | * if the default settings are not enough. |
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| 213 | * |
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| 214 | * The configuration consists of an array of configuration pointers, each |
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| 215 | * pointer determine the configuration of one GR-RASTA-IO board. Pointer |
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| 216 | * zero is for board0, pointer 1 for board1 and so on. |
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| 217 | * |
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| 218 | * The array must end with a NULL pointer. |
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| 219 | */ |
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| 220 | struct drvmgr_bus_res *gr_rasta_io_resources[] __attribute__((weak)) = |
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| 221 | { |
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| 222 | NULL |
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| 223 | }; |
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| 224 | |
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| 225 | void gr_rasta_io_register_drv(void) |
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| 226 | { |
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| 227 | DBG("Registering GR-RASTA-IO PCI driver\n"); |
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| 228 | drvmgr_drv_register(&gr_rasta_io_info.general); |
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| 229 | } |
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| 230 | |
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| 231 | void gr_rasta_io_isr (void *arg) |
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| 232 | { |
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| 233 | struct gr_rasta_io_priv *priv = arg; |
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| 234 | unsigned int status, tmp; |
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| 235 | int irq; |
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| 236 | tmp = status = priv->irq->ipend; |
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| 237 | |
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| 238 | /* DBG("GR-RASTA-IO: IRQ 0x%x\n",status); */ |
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| 239 | |
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| 240 | for(irq=0; irq<16; irq++) { |
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| 241 | if ( status & (1<<irq) ) { |
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| 242 | genirq_doirq(priv->genirq, irq); |
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| 243 | priv->irq->iclear = (1<<irq); |
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| 244 | status &= ~(1<<irq); |
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| 245 | if ( status == 0 ) |
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| 246 | break; |
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| 247 | } |
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| 248 | } |
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| 249 | |
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| 250 | /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */ |
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| 251 | if ( tmp ) |
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| 252 | drvmgr_interrupt_clear(priv->dev, 0); |
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| 253 | |
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| 254 | DBG("RASTA-IO-IRQ: 0x%x\n", tmp); |
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| 255 | } |
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| 256 | |
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[80b9c8ac] | 257 | /* PCI Hardware (Revision 0 and 1) initialization */ |
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[960aebf] | 258 | static int gr_rasta_io_hw_init(struct gr_rasta_io_priv *priv) |
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[e67b2b8d] | 259 | { |
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| 260 | unsigned int *page0 = NULL; |
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| 261 | struct ambapp_dev *tmp; |
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| 262 | struct ambapp_ahb_info *ahb; |
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| 263 | struct pci_dev_info *devinfo = priv->devinfo; |
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| 264 | uint32_t bar0, bar0_size; |
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| 265 | |
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| 266 | bar0 = devinfo->resources[0].address; |
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| 267 | bar0_size = devinfo->resources[0].size; |
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| 268 | page0 = (unsigned int *)(bar0 + bar0_size/2); |
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| 269 | |
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| 270 | /* Point PAGE0 to start of Plug and Play information */ |
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[80b9c8ac] | 271 | *page0 = priv->version->amba_ioarea & 0xff000000; |
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[e67b2b8d] | 272 | |
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| 273 | #if 0 |
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| 274 | { |
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| 275 | uint32_t data; |
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| 276 | /* set parity error response */ |
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| 277 | pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data); |
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| 278 | pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY)); |
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| 279 | } |
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| 280 | #endif |
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| 281 | |
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[819de55b] | 282 | /* Setup cache line size. Default cache line size will result in |
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| 283 | * poor performance (256 word fetches), 0xff will set it according |
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| 284 | * to the max size of the PCI FIFO. |
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| 285 | */ |
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| 286 | pci_cfg_w8(priv->pcidev, PCI_CACHE_LINE_SIZE, 0xff); |
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| 287 | |
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[e67b2b8d] | 288 | /* Scan AMBA Plug&Play */ |
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| 289 | |
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| 290 | /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */ |
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| 291 | priv->amba_maps[0].size = bar0_size/2; |
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| 292 | priv->amba_maps[0].local_adr = bar0; |
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[80b9c8ac] | 293 | priv->amba_maps[0].remote_adr = AHB1_BASE_ADDR; |
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[e67b2b8d] | 294 | |
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| 295 | /* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */ |
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| 296 | priv->amba_maps[1].size = devinfo->resources[1].size; |
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| 297 | priv->amba_maps[1].local_adr = devinfo->resources[1].address; |
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| 298 | priv->amba_maps[1].remote_adr = 0x40000000; |
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| 299 | |
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| 300 | /* Addresses not matching with map be untouched */ |
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| 301 | priv->amba_maps[2].size = 0xfffffff0; |
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| 302 | priv->amba_maps[2].local_adr = 0; |
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| 303 | priv->amba_maps[2].remote_adr = 0; |
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| 304 | |
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| 305 | /* Mark end of table */ |
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| 306 | priv->amba_maps[3].size=0; |
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| 307 | priv->amba_maps[3].local_adr = 0; |
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| 308 | priv->amba_maps[3].remote_adr = 0; |
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| 309 | |
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| 310 | /* Start AMBA PnP scan at first AHB bus */ |
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| 311 | ambapp_scan(&priv->abus, |
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[80b9c8ac] | 312 | bar0 + (priv->version->amba_ioarea & ~0xff000000), |
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[e67b2b8d] | 313 | NULL, &priv->amba_maps[0]); |
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| 314 | |
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| 315 | /* Initialize Frequency of AMBA bus */ |
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| 316 | ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz); |
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| 317 | |
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| 318 | /* Point PAGE0 to start of APB area */ |
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[80b9c8ac] | 319 | *page0 = AHB1_BASE_ADDR; |
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[e67b2b8d] | 320 | |
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| 321 | /* Find GRPCI controller */ |
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[960aebf] | 322 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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[e67b2b8d] | 323 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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| 324 | VENDOR_GAISLER, GAISLER_PCIFBRG, |
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| 325 | ambapp_find_by_idx, NULL); |
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| 326 | if ( !tmp ) { |
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| 327 | return -3; |
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| 328 | } |
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| 329 | priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start; |
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| 330 | |
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| 331 | /* Set GRPCI mmap so that AMBA masters can access CPU-RAM over |
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| 332 | * the PCI window. |
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| 333 | */ |
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| 334 | priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) | |
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| 335 | (priv->ahbmst2pci_map & 0xf0000000); |
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| 336 | priv->grpci->page1 = 0x40000000; |
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| 337 | |
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| 338 | /* Find IRQ controller, Clear all current IRQs */ |
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[960aebf] | 339 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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[e67b2b8d] | 340 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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| 341 | VENDOR_GAISLER, GAISLER_IRQMP, |
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| 342 | ambapp_find_by_idx, NULL); |
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| 343 | if ( !tmp ) { |
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| 344 | return -4; |
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| 345 | } |
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| 346 | priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start; |
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| 347 | /* Set up GR-RASTA-IO irq controller */ |
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| 348 | priv->irq->mask[0] = 0; |
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| 349 | priv->irq->iclear = 0xffff; |
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| 350 | priv->irq->ilevel = 0; |
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| 351 | |
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| 352 | /* DOWN streams translation table */ |
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| 353 | priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA"; |
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| 354 | priv->bus_maps_down[0].size = priv->amba_maps[0].size; |
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| 355 | priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr; |
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| 356 | priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr; |
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| 357 | |
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| 358 | priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA"; |
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| 359 | priv->bus_maps_down[1].size = priv->amba_maps[1].size; |
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| 360 | priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr; |
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| 361 | priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr; |
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| 362 | |
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| 363 | /* Mark end of translation table */ |
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| 364 | priv->bus_maps_down[2].size = 0; |
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| 365 | |
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| 366 | /* Find GRPCI controller AHB Slave interface */ |
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[960aebf] | 367 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
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[e67b2b8d] | 368 | (OPTIONS_ALL|OPTIONS_AHB_SLVS), |
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| 369 | VENDOR_GAISLER, GAISLER_PCIFBRG, |
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| 370 | ambapp_find_by_idx, NULL); |
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| 371 | if ( !tmp ) { |
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| 372 | return -5; |
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| 373 | } |
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| 374 | ahb = (struct ambapp_ahb_info *)tmp->devinfo; |
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| 375 | |
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| 376 | /* UP streams translation table */ |
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| 377 | priv->bus_maps_up[0].name = "AMBA GRPCI Window"; |
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| 378 | priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-IO board */ |
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| 379 | priv->bus_maps_up[0].from_adr = (void *)ahb->start[0]; |
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| 380 | priv->bus_maps_up[0].to_adr = (void *) |
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| 381 | (priv->ahbmst2pci_map & 0xf0000000); |
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| 382 | |
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| 383 | /* Mark end of translation table */ |
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| 384 | priv->bus_maps_up[1].size = 0; |
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| 385 | |
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| 386 | /* Successfully registered the RASTA board */ |
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| 387 | return 0; |
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| 388 | } |
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| 389 | |
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[80b9c8ac] | 390 | /* PCI Hardware (Revision 1) initialization */ |
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[960aebf] | 391 | static int gr_rasta_io2_hw_init(struct gr_rasta_io_priv *priv) |
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[80b9c8ac] | 392 | { |
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| 393 | int i; |
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| 394 | uint32_t data; |
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| 395 | unsigned int ctrl; |
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| 396 | uint8_t tmp2; |
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| 397 | struct ambapp_dev *tmp; |
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| 398 | struct ambapp_ahb_info *ahb; |
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| 399 | uint8_t cap_ptr; |
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| 400 | pci_dev_t pcidev = priv->pcidev; |
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| 401 | struct pci_dev_info *devinfo = priv->devinfo; |
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| 402 | |
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| 403 | /* Check capabilities list bit */ |
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| 404 | pci_cfg_r8(pcidev, PCI_STATUS, &tmp2); |
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| 405 | |
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| 406 | if (!((tmp2 >> 4) & 1)) { |
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| 407 | /* Capabilities list not available which it should be in the |
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| 408 | * GRPCI2 |
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| 409 | */ |
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| 410 | return -3; |
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| 411 | } |
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| 412 | |
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| 413 | /* Read capabilities pointer */ |
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| 414 | pci_cfg_r8(pcidev, PCI_CAP_PTR, &cap_ptr); |
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| 415 | |
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| 416 | /* Set AHB address mappings for target PCI bars |
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| 417 | * BAR0: 16MB : Mapped to I/O at 0x80000000 |
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| 418 | * BAR1: 256MB : Mapped to MEM at 0x40000000 |
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| 419 | */ |
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| 420 | pci_cfg_w32(pcidev, cap_ptr+GRPCI2_BAR0_TO_AHB_MAP, AHB1_BASE_ADDR); |
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| 421 | pci_cfg_w32(pcidev, cap_ptr+GRPCI2_BAR1_TO_AHB_MAP, 0x40000000); |
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| 422 | |
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| 423 | /* Set PCI bus to be same endianess as PCI system */ |
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| 424 | pci_cfg_r32(pcidev, cap_ptr+GRPCI2_PCI_CONFIG, &data); |
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| 425 | if (pci_endian == PCI_BIG_ENDIAN) |
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| 426 | data = data & 0xFFFFFFFE; |
---|
| 427 | else |
---|
| 428 | data = data | 0x00000001; |
---|
| 429 | pci_cfg_w32(pcidev, cap_ptr+GRPCI2_PCI_CONFIG, data); |
---|
| 430 | |
---|
| 431 | #if 0 |
---|
| 432 | /* set parity error response */ |
---|
| 433 | pci_cfg_r32(pcidev, PCI_COMMAND, &data); |
---|
| 434 | pci_cfg_w32(pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY)); |
---|
| 435 | #endif |
---|
| 436 | |
---|
| 437 | /* Scan AMBA Plug&Play */ |
---|
| 438 | |
---|
| 439 | /* AMBA MAP bar0 (in PCI) ==> 0x40000000 (remote amba address) */ |
---|
| 440 | priv->amba_maps[0].size = devinfo->resources[0].size; |
---|
| 441 | priv->amba_maps[0].local_adr = devinfo->resources[0].address; |
---|
| 442 | priv->amba_maps[0].remote_adr = AHB1_BASE_ADDR; |
---|
| 443 | |
---|
| 444 | /* AMBA MAP bar0 (in PCI) ==> 0x80000000 (remote amba address) */ |
---|
| 445 | priv->amba_maps[1].size = devinfo->resources[1].size; |
---|
| 446 | priv->amba_maps[1].local_adr = devinfo->resources[1].address; |
---|
| 447 | priv->amba_maps[1].remote_adr = 0x40000000; |
---|
| 448 | |
---|
| 449 | /* Addresses not matching with map be untouched */ |
---|
| 450 | priv->amba_maps[2].size = 0xfffffff0; |
---|
| 451 | priv->amba_maps[2].local_adr = 0; |
---|
| 452 | priv->amba_maps[2].remote_adr = 0; |
---|
| 453 | |
---|
| 454 | /* Mark end of table */ |
---|
| 455 | priv->amba_maps[3].size=0; |
---|
| 456 | |
---|
| 457 | /* Start AMBA PnP scan at first AHB bus */ |
---|
| 458 | ambapp_scan( |
---|
| 459 | &priv->abus, |
---|
| 460 | devinfo->resources[0].address + AHB1_IOAREA_OFS, |
---|
| 461 | NULL, |
---|
| 462 | &priv->amba_maps[0]); |
---|
| 463 | |
---|
| 464 | /* Initialize Frequency of AMBA bus. The AMBA bus runs at same |
---|
| 465 | * frequency as PCI bus |
---|
| 466 | */ |
---|
| 467 | ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz); |
---|
| 468 | |
---|
| 469 | /* Find IRQ controller, Clear all current IRQs */ |
---|
| 470 | tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus, |
---|
| 471 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
---|
| 472 | VENDOR_GAISLER, GAISLER_IRQMP, |
---|
| 473 | ambapp_find_by_idx, NULL); |
---|
| 474 | if ( !tmp ) { |
---|
| 475 | return -4; |
---|
| 476 | } |
---|
| 477 | priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start; |
---|
| 478 | /* Set up GR-RASTA-SPW-ROUTER irq controller */ |
---|
| 479 | priv->irq->mask[0] = 0; |
---|
| 480 | priv->irq->iclear = 0xffff; |
---|
| 481 | priv->irq->ilevel = 0; |
---|
| 482 | |
---|
| 483 | priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA"; |
---|
| 484 | priv->bus_maps_down[0].size = priv->amba_maps[0].size; |
---|
| 485 | priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr; |
---|
| 486 | priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr; |
---|
| 487 | priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA"; |
---|
| 488 | priv->bus_maps_down[1].size = priv->amba_maps[1].size; |
---|
| 489 | priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr; |
---|
| 490 | priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr; |
---|
| 491 | priv->bus_maps_down[2].size = 0; |
---|
| 492 | |
---|
| 493 | /* Find GRPCI2 controller AHB Slave interface */ |
---|
| 494 | tmp = (void *)ambapp_for_each(&priv->abus, |
---|
| 495 | (OPTIONS_ALL|OPTIONS_AHB_SLVS), |
---|
| 496 | VENDOR_GAISLER, GAISLER_GRPCI2, |
---|
| 497 | ambapp_find_by_idx, NULL); |
---|
| 498 | if ( !tmp ) { |
---|
| 499 | return -5; |
---|
| 500 | } |
---|
| 501 | ahb = (struct ambapp_ahb_info *)tmp->devinfo; |
---|
| 502 | priv->bus_maps_up[0].name = "AMBA GRPCI2 Window"; |
---|
| 503 | priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-SPW-ROUTER board */ |
---|
| 504 | priv->bus_maps_up[0].from_adr = (void *)ahb->start[0]; |
---|
| 505 | priv->bus_maps_up[0].to_adr = (void *) |
---|
| 506 | (priv->ahbmst2pci_map & ~(ahb->mask[0]-1)); |
---|
| 507 | priv->bus_maps_up[1].size = 0; |
---|
| 508 | |
---|
| 509 | /* Find GRPCI2 controller APB Slave interface */ |
---|
| 510 | tmp = (void *)ambapp_for_each(&priv->abus, |
---|
| 511 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
---|
| 512 | VENDOR_GAISLER, GAISLER_GRPCI2, |
---|
| 513 | ambapp_find_by_idx, NULL); |
---|
| 514 | if ( !tmp ) { |
---|
| 515 | return -6; |
---|
| 516 | } |
---|
| 517 | priv->grpci2 = (struct grpci2_regs *) |
---|
| 518 | ((struct ambapp_apb_info *)tmp->devinfo)->start; |
---|
| 519 | |
---|
| 520 | /* Set AHB to PCI mapping for all AMBA AHB masters */ |
---|
| 521 | for(i = 0; i < 16; i++) { |
---|
| 522 | priv->grpci2->ahbtopcimemmap[i] = priv->ahbmst2pci_map & |
---|
| 523 | ~(ahb->mask[0]-1); |
---|
| 524 | } |
---|
| 525 | |
---|
| 526 | /* Make sure dirq(0) sampling is enabled */ |
---|
| 527 | ctrl = priv->grpci2->ctrl; |
---|
| 528 | ctrl = (ctrl & 0xFFFFFF0F) | (1 << 4); |
---|
| 529 | priv->grpci2->ctrl = ctrl; |
---|
| 530 | |
---|
| 531 | /* Successfully registered the RASTA-SPW-ROUTER board */ |
---|
| 532 | return 0; |
---|
| 533 | } |
---|
| 534 | |
---|
[960aebf] | 535 | static int gr_rasta_io_hw_init2(struct gr_rasta_io_priv *priv) |
---|
[e67b2b8d] | 536 | { |
---|
| 537 | /* Enable DMA by enabling PCI target as master */ |
---|
| 538 | pci_master_enable(priv->pcidev); |
---|
| 539 | |
---|
| 540 | return DRVMGR_OK; |
---|
| 541 | } |
---|
| 542 | |
---|
| 543 | /* Called when a PCI target is found with the PCI device and vendor ID |
---|
| 544 | * given in gr_rasta_io_ids[]. |
---|
| 545 | */ |
---|
| 546 | int gr_rasta_io_init1(struct drvmgr_dev *dev) |
---|
| 547 | { |
---|
| 548 | struct gr_rasta_io_priv *priv; |
---|
| 549 | struct pci_dev_info *devinfo; |
---|
| 550 | int status; |
---|
| 551 | uint32_t bar0, bar1, bar0_size, bar1_size; |
---|
| 552 | union drvmgr_key_value *value; |
---|
[960aebf] | 553 | int resources_cnt; |
---|
[e67b2b8d] | 554 | |
---|
| 555 | priv = malloc(sizeof(struct gr_rasta_io_priv)); |
---|
| 556 | if ( !priv ) |
---|
| 557 | return DRVMGR_NOMEM; |
---|
| 558 | |
---|
| 559 | memset(priv, 0, sizeof(*priv)); |
---|
| 560 | dev->priv = priv; |
---|
| 561 | priv->dev = dev; |
---|
| 562 | |
---|
| 563 | /* Determine number of configurations */ |
---|
[960aebf] | 564 | resources_cnt = get_resarray_count(gr_rasta_io_resources); |
---|
[e67b2b8d] | 565 | |
---|
| 566 | /* Generate Device prefix */ |
---|
| 567 | |
---|
| 568 | strcpy(priv->prefix, "/dev/rastaio0"); |
---|
| 569 | priv->prefix[12] += dev->minor_drv; |
---|
| 570 | mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO); |
---|
| 571 | priv->prefix[13] = '/'; |
---|
| 572 | priv->prefix[14] = '\0'; |
---|
| 573 | |
---|
| 574 | priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo; |
---|
| 575 | priv->pcidev = devinfo->pcidev; |
---|
| 576 | bar0 = devinfo->resources[0].address; |
---|
| 577 | bar0_size = devinfo->resources[0].size; |
---|
| 578 | bar1 = devinfo->resources[1].address; |
---|
| 579 | bar1_size = devinfo->resources[1].size; |
---|
| 580 | printf("\n\n--- GR-RASTA-IO[%d] ---\n", dev->minor_drv); |
---|
| 581 | printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n", |
---|
| 582 | PCI_DEV_EXPAND(priv->pcidev)); |
---|
| 583 | printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n", |
---|
| 584 | devinfo->id.vendor, devinfo->id.device); |
---|
| 585 | printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1); |
---|
| 586 | printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1); |
---|
| 587 | printf(" IRQ: %d\n\n\n", devinfo->irq); |
---|
| 588 | |
---|
| 589 | /* all neccessary space assigned to GR-RASTA-IO target? */ |
---|
| 590 | if ((bar0_size == 0) || (bar1_size == 0)) |
---|
| 591 | return DRVMGR_ENORES; |
---|
| 592 | |
---|
| 593 | /* Let user override which PCI address the AHB masters of the |
---|
| 594 | * GR-RASTA-IO board access when doing DMA to CPU RAM. The AHB masters |
---|
| 595 | * access the PCI Window of the AMBA bus, the MSB 4-bits of that address |
---|
| 596 | * is translated according this config option before the address |
---|
| 597 | * goes out on the PCI bus. |
---|
| 598 | * Only the 4 MSB bits have an effect; |
---|
| 599 | */ |
---|
| 600 | value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT); |
---|
| 601 | if (value) |
---|
| 602 | priv->ahbmst2pci_map = value->i; |
---|
| 603 | else |
---|
| 604 | priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */ |
---|
| 605 | |
---|
| 606 | priv->genirq = genirq_init(16); |
---|
| 607 | if ( priv->genirq == NULL ) { |
---|
| 608 | free(priv); |
---|
| 609 | dev->priv = NULL; |
---|
| 610 | return DRVMGR_FAIL; |
---|
| 611 | } |
---|
| 612 | |
---|
[80b9c8ac] | 613 | /* Select version of GR-RASTA-IO board */ |
---|
| 614 | switch (devinfo->rev) { |
---|
| 615 | case 0: |
---|
| 616 | priv->version = &gr_rasta_io_ver0; |
---|
| 617 | status = gr_rasta_io_hw_init(priv); |
---|
| 618 | break; |
---|
| 619 | case 1: |
---|
| 620 | priv->version = &gr_rasta_io_ver1; |
---|
| 621 | status = gr_rasta_io_hw_init(priv); |
---|
| 622 | break; |
---|
| 623 | case 2: |
---|
| 624 | priv->version = &gr_rasta_io_ver1; /* same cfg as 1 */ |
---|
| 625 | status = gr_rasta_io2_hw_init(priv); |
---|
| 626 | break; |
---|
| 627 | default: |
---|
| 628 | return -2; |
---|
| 629 | } |
---|
| 630 | |
---|
[e67b2b8d] | 631 | if ( status != 0 ) { |
---|
| 632 | genirq_destroy(priv->genirq); |
---|
| 633 | free(priv); |
---|
| 634 | dev->priv = NULL; |
---|
| 635 | printf(" Failed to initialize GR-RASTA-IO HW: %d\n", status); |
---|
| 636 | return DRVMGR_FAIL; |
---|
| 637 | } |
---|
| 638 | |
---|
| 639 | /* Init amba bus */ |
---|
| 640 | priv->config.abus = &priv->abus; |
---|
| 641 | priv->config.ops = &ambapp_rasta_io_ops; |
---|
| 642 | priv->config.maps_up = &priv->bus_maps_up[0]; |
---|
| 643 | priv->config.maps_down = &priv->bus_maps_down[0]; |
---|
[960aebf] | 644 | if ( priv->dev->minor_drv < resources_cnt ) { |
---|
[e67b2b8d] | 645 | priv->config.resources = gr_rasta_io_resources[priv->dev->minor_drv]; |
---|
| 646 | } else { |
---|
| 647 | priv->config.resources = NULL; |
---|
| 648 | } |
---|
| 649 | |
---|
| 650 | /* Create and register AMBA PnP bus. */ |
---|
| 651 | return ambapp_bus_register(dev, &priv->config); |
---|
| 652 | } |
---|
| 653 | |
---|
| 654 | int gr_rasta_io_init2(struct drvmgr_dev *dev) |
---|
| 655 | { |
---|
| 656 | struct gr_rasta_io_priv *priv = dev->priv; |
---|
| 657 | |
---|
| 658 | /* Clear any old interrupt requests */ |
---|
| 659 | drvmgr_interrupt_clear(dev, 0); |
---|
| 660 | |
---|
| 661 | /* Enable System IRQ so that GR-RASTA-IO PCI target interrupt goes |
---|
| 662 | * through. |
---|
| 663 | * |
---|
| 664 | * It is important to enable it in stage init2. If interrupts were |
---|
| 665 | * enabled in init1 this might hang the system when more than one |
---|
| 666 | * PCI board is connected, this is because PCI interrupts might |
---|
| 667 | * be shared and PCI board 2 have not initialized and |
---|
| 668 | * might therefore drive interrupt already when entering init1(). |
---|
| 669 | */ |
---|
| 670 | drvmgr_interrupt_register( |
---|
| 671 | dev, |
---|
| 672 | 0, |
---|
| 673 | "gr_rasta_io", |
---|
| 674 | gr_rasta_io_isr, |
---|
| 675 | (void *)priv); |
---|
| 676 | |
---|
| 677 | return gr_rasta_io_hw_init2(priv); |
---|
| 678 | } |
---|
| 679 | |
---|
| 680 | int ambapp_rasta_io_int_register( |
---|
| 681 | struct drvmgr_dev *dev, |
---|
| 682 | int irq, |
---|
| 683 | const char *info, |
---|
| 684 | drvmgr_isr handler, |
---|
| 685 | void *arg) |
---|
| 686 | { |
---|
| 687 | struct gr_rasta_io_priv *priv = dev->parent->dev->priv; |
---|
| 688 | rtems_interrupt_level level; |
---|
| 689 | int status; |
---|
| 690 | |
---|
| 691 | rtems_interrupt_disable(level); |
---|
| 692 | |
---|
| 693 | status = genirq_register(priv->genirq, irq, handler, arg); |
---|
| 694 | if ( status == 0 ) { |
---|
| 695 | /* Clear IRQ for first registered handler */ |
---|
| 696 | priv->irq->iclear = (1<<irq); |
---|
| 697 | } else if ( status == 1 ) |
---|
| 698 | status = 0; |
---|
| 699 | |
---|
| 700 | if (status != 0) { |
---|
| 701 | rtems_interrupt_enable(level); |
---|
| 702 | return DRVMGR_FAIL; |
---|
| 703 | } |
---|
| 704 | |
---|
| 705 | status = genirq_enable(priv->genirq, irq, handler, arg); |
---|
| 706 | if ( status == 0 ) { |
---|
| 707 | /* Enable IRQ for first enabled handler only */ |
---|
| 708 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
---|
| 709 | } else if ( status == 1 ) |
---|
| 710 | status = 0; |
---|
| 711 | |
---|
| 712 | rtems_interrupt_enable(level); |
---|
| 713 | |
---|
| 714 | return status; |
---|
| 715 | } |
---|
| 716 | |
---|
| 717 | int ambapp_rasta_io_int_unregister( |
---|
| 718 | struct drvmgr_dev *dev, |
---|
| 719 | int irq, |
---|
| 720 | drvmgr_isr isr, |
---|
| 721 | void *arg) |
---|
| 722 | { |
---|
| 723 | struct gr_rasta_io_priv *priv = dev->parent->dev->priv; |
---|
| 724 | rtems_interrupt_level level; |
---|
| 725 | int status; |
---|
| 726 | |
---|
| 727 | rtems_interrupt_disable(level); |
---|
| 728 | |
---|
| 729 | status = genirq_disable(priv->genirq, irq, isr, arg); |
---|
| 730 | if ( status == 0 ) { |
---|
| 731 | /* Disable IRQ only when no enabled handler exists */ |
---|
| 732 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
---|
| 733 | } |
---|
| 734 | |
---|
| 735 | status = genirq_unregister(priv->genirq, irq, isr, arg); |
---|
| 736 | if ( status != 0 ) |
---|
| 737 | status = DRVMGR_FAIL; |
---|
| 738 | |
---|
| 739 | rtems_interrupt_enable(level); |
---|
| 740 | |
---|
| 741 | return status; |
---|
| 742 | } |
---|
| 743 | |
---|
| 744 | int ambapp_rasta_io_int_unmask( |
---|
| 745 | struct drvmgr_dev *dev, |
---|
| 746 | int irq) |
---|
| 747 | { |
---|
| 748 | struct gr_rasta_io_priv *priv = dev->parent->dev->priv; |
---|
| 749 | rtems_interrupt_level level; |
---|
| 750 | |
---|
| 751 | DBG("RASTA-IO IRQ %d: unmask\n", irq); |
---|
| 752 | |
---|
| 753 | if ( genirq_check(priv->genirq, irq) ) |
---|
| 754 | return DRVMGR_EINVAL; |
---|
| 755 | |
---|
| 756 | rtems_interrupt_disable(level); |
---|
| 757 | |
---|
| 758 | /* Enable IRQ for first enabled handler only */ |
---|
| 759 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
---|
| 760 | |
---|
| 761 | rtems_interrupt_enable(level); |
---|
| 762 | |
---|
| 763 | return DRVMGR_OK; |
---|
| 764 | } |
---|
| 765 | |
---|
| 766 | int ambapp_rasta_io_int_mask( |
---|
| 767 | struct drvmgr_dev *dev, |
---|
| 768 | int irq) |
---|
| 769 | { |
---|
| 770 | struct gr_rasta_io_priv *priv = dev->parent->dev->priv; |
---|
| 771 | rtems_interrupt_level level; |
---|
| 772 | |
---|
| 773 | DBG("RASTA-IO IRQ %d: mask\n", irq); |
---|
| 774 | |
---|
| 775 | if ( genirq_check(priv->genirq, irq) ) |
---|
| 776 | return DRVMGR_EINVAL; |
---|
| 777 | |
---|
| 778 | rtems_interrupt_disable(level); |
---|
| 779 | |
---|
| 780 | /* Disable/mask IRQ */ |
---|
| 781 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
---|
| 782 | |
---|
| 783 | rtems_interrupt_enable(level); |
---|
| 784 | |
---|
| 785 | return DRVMGR_OK; |
---|
| 786 | } |
---|
| 787 | |
---|
| 788 | int ambapp_rasta_io_int_clear( |
---|
| 789 | struct drvmgr_dev *dev, |
---|
| 790 | int irq) |
---|
| 791 | { |
---|
| 792 | struct gr_rasta_io_priv *priv = dev->parent->dev->priv; |
---|
| 793 | |
---|
| 794 | if ( genirq_check(priv->genirq, irq) ) |
---|
| 795 | return DRVMGR_EINVAL; |
---|
| 796 | |
---|
| 797 | priv->irq->iclear = (1<<irq); |
---|
| 798 | |
---|
| 799 | return DRVMGR_OK; |
---|
| 800 | } |
---|
| 801 | |
---|
| 802 | int ambapp_rasta_io_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params) |
---|
| 803 | { |
---|
| 804 | struct gr_rasta_io_priv *priv = dev->parent->dev->priv; |
---|
| 805 | |
---|
| 806 | /* Device name prefix pointer, skip /dev */ |
---|
| 807 | params->dev_prefix = &priv->prefix[5]; |
---|
| 808 | |
---|
| 809 | return 0; |
---|
| 810 | } |
---|
| 811 | |
---|
| 812 | void gr_rasta_io_print_dev(struct drvmgr_dev *dev, int options) |
---|
| 813 | { |
---|
| 814 | struct gr_rasta_io_priv *priv = dev->priv; |
---|
| 815 | struct pci_dev_info *devinfo = priv->devinfo; |
---|
| 816 | uint32_t bar0, bar1, bar0_size, bar1_size; |
---|
| 817 | |
---|
| 818 | /* Print */ |
---|
| 819 | printf("--- GR-RASTA-IO [bus 0x%x, dev 0x%x, fun 0x%x] ---\n", |
---|
| 820 | PCI_DEV_EXPAND(priv->pcidev)); |
---|
| 821 | |
---|
| 822 | bar0 = devinfo->resources[0].address; |
---|
| 823 | bar0_size = devinfo->resources[0].size; |
---|
| 824 | bar1 = devinfo->resources[1].address; |
---|
| 825 | bar1_size = devinfo->resources[1].size; |
---|
| 826 | |
---|
| 827 | printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1); |
---|
| 828 | printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1); |
---|
| 829 | printf(" IRQ REGS: 0x%x\n", (unsigned int)priv->irq); |
---|
| 830 | printf(" IRQ: %d\n", devinfo->irq); |
---|
| 831 | printf(" PCI REVISION: %d\n", devinfo->rev); |
---|
| 832 | printf(" FREQ: %d Hz\n", priv->version->amba_freq_hz); |
---|
| 833 | printf(" IMASK: 0x%08x\n", priv->irq->mask[0]); |
---|
| 834 | printf(" IPEND: 0x%08x\n", priv->irq->ipend); |
---|
| 835 | |
---|
| 836 | /* Print amba config */ |
---|
| 837 | if ( options & RASTA_IO_OPTIONS_AMBA ) { |
---|
| 838 | ambapp_print(&priv->abus, 10); |
---|
| 839 | } |
---|
| 840 | |
---|
| 841 | #if 0 |
---|
| 842 | /* Print IRQ handlers and their arguments */ |
---|
| 843 | if ( options & RASTA_IO_OPTIONS_IRQ ) { |
---|
| 844 | int i; |
---|
| 845 | for(i=0; i<16; i++) { |
---|
| 846 | printf(" IRQ[%02d]: 0x%x, arg: 0x%x\n", |
---|
| 847 | i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg); |
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| 848 | } |
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| 849 | } |
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| 850 | #endif |
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| 851 | } |
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| 852 | |
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| 853 | void gr_rasta_io_print(int options) |
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| 854 | { |
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| 855 | struct pci_drv_info *drv = &gr_rasta_io_info; |
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| 856 | struct drvmgr_dev *dev; |
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| 857 | |
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| 858 | dev = drv->general.dev; |
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| 859 | while(dev) { |
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| 860 | gr_rasta_io_print_dev(dev, options); |
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| 861 | dev = dev->next_in_drv; |
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| 862 | } |
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| 863 | } |
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