1 | /* GR-RASTA-ADCDAC PCI Target driver. |
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2 | * |
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3 | * COPYRIGHT (c) 2008. |
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4 | * Cobham Gaisler AB. |
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5 | * |
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6 | * Configures the GR-RASTA-ADCDAC interface PCI board. |
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7 | * This driver provides a AMBA PnP bus by using the general part |
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8 | * of the AMBA PnP bus driver (ambapp_bus.c). |
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9 | * |
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10 | * Driver resources for the AMBA PnP bus provided can be set using |
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11 | * gr_rasta_adcdac_set_resources(). |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.com/license/LICENSE. |
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16 | */ |
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17 | |
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18 | #include <stdio.h> |
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19 | #include <stdlib.h> |
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20 | #include <string.h> |
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21 | #include <sys/types.h> |
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22 | #include <sys/stat.h> |
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23 | |
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24 | #include <bsp.h> |
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25 | #include <rtems/bspIo.h> |
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26 | #include <pci.h> |
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27 | |
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28 | #include <ambapp.h> |
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29 | #include <grlib.h> |
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30 | #include <drvmgr/drvmgr.h> |
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31 | #include <drvmgr/ambapp_bus.h> |
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32 | #include <drvmgr/pci_bus.h> |
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33 | #include <genirq.h> |
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34 | |
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35 | #include <gr_rasta_adcdac.h> |
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36 | |
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37 | /*#define DEBUG 1*/ |
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38 | |
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39 | #ifdef DEBUG |
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40 | #define DBG(x...) printk(x) |
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41 | #else |
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42 | #define DBG(x...) |
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43 | #endif |
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44 | |
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45 | /* Determines which PCI address the AHB masters will access, it should be |
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46 | * set so that the masters can access the CPU RAM. Default is base of CPU RAM, |
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47 | * CPU RAM is mapped 1:1 to PCI space. |
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48 | */ |
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49 | extern unsigned int _RAM_START; |
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50 | #define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000) |
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51 | |
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52 | /* PCI ID */ |
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53 | #define PCIID_VENDOR_GAISLER 0x1AC8 |
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54 | #define PCIID_DEVICE_GR_RASTA_ADCDAC 0x0014 |
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55 | |
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56 | int gr_rasta_adcdac_init1(struct drvmgr_dev *dev); |
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57 | int gr_rasta_adcdac_init2(struct drvmgr_dev *dev); |
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58 | |
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59 | struct grpci_regs { |
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60 | volatile unsigned int cfg_stat; |
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61 | volatile unsigned int bar0; |
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62 | volatile unsigned int page0; |
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63 | volatile unsigned int bar1; |
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64 | volatile unsigned int page1; |
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65 | volatile unsigned int iomap; |
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66 | volatile unsigned int stat_cmd; |
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67 | }; |
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68 | |
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69 | struct gr_rasta_adcdac_ver { |
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70 | const unsigned int amba_freq_hz; /* The frequency */ |
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71 | const unsigned int amba_ioarea; /* The address where the PnP IOAREA starts at */ |
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72 | }; |
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73 | |
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74 | /* Private data structure for driver */ |
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75 | struct gr_rasta_adcdac_priv { |
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76 | /* Driver management */ |
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77 | struct drvmgr_dev *dev; |
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78 | char prefix[20]; |
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79 | |
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80 | /* PCI */ |
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81 | pci_dev_t pcidev; |
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82 | struct pci_dev_info *devinfo; |
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83 | uint32_t ahbmst2pci_map; |
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84 | |
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85 | /* IRQ */ |
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86 | genirq_t genirq; |
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87 | |
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88 | /* GR-RASTA-ADCDAC */ |
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89 | struct gr_rasta_adcdac_ver *version; |
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90 | struct irqmp_regs *irq; |
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91 | struct grpci_regs *grpci; |
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92 | struct drvmgr_map_entry bus_maps_down[3]; |
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93 | struct drvmgr_map_entry bus_maps_up[2]; |
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94 | |
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95 | /* AMBA Plug&Play information on GR-RASTA-ADCDAC */ |
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96 | struct ambapp_bus abus; |
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97 | struct ambapp_mmap amba_maps[4]; |
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98 | struct ambapp_config config; |
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99 | }; |
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100 | |
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101 | struct gr_rasta_adcdac_ver gr_rasta_adcdac_ver0 = { |
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102 | .amba_freq_hz = 50000000, |
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103 | .amba_ioarea = 0x80100000, |
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104 | }; |
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105 | |
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106 | int ambapp_rasta_adcdac_int_register( |
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107 | struct drvmgr_dev *dev, |
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108 | int irq, |
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109 | const char *info, |
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110 | drvmgr_isr handler, |
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111 | void *arg); |
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112 | int ambapp_rasta_adcdac_int_unregister( |
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113 | struct drvmgr_dev *dev, |
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114 | int irq, |
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115 | drvmgr_isr isr, |
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116 | void *arg); |
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117 | int ambapp_rasta_adcdac_int_unmask( |
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118 | struct drvmgr_dev *dev, |
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119 | int irq); |
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120 | int ambapp_rasta_adcdac_int_mask( |
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121 | struct drvmgr_dev *dev, |
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122 | int irq); |
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123 | int ambapp_rasta_adcdac_int_clear( |
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124 | struct drvmgr_dev *dev, |
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125 | int irq); |
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126 | int ambapp_rasta_adcdac_get_params( |
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127 | struct drvmgr_dev *dev, |
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128 | struct drvmgr_bus_params *params); |
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129 | |
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130 | struct ambapp_ops ambapp_rasta_adcdac_ops = { |
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131 | .int_register = ambapp_rasta_adcdac_int_register, |
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132 | .int_unregister = ambapp_rasta_adcdac_int_unregister, |
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133 | .int_unmask = ambapp_rasta_adcdac_int_unmask, |
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134 | .int_mask = ambapp_rasta_adcdac_int_mask, |
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135 | .int_clear = ambapp_rasta_adcdac_int_clear, |
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136 | .get_params = ambapp_rasta_adcdac_get_params |
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137 | }; |
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138 | |
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139 | struct drvmgr_drv_ops gr_rasta_adcdac_ops = |
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140 | { .init = {gr_rasta_adcdac_init1, gr_rasta_adcdac_init2, NULL, NULL}, |
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141 | .remove = NULL, |
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142 | .info = NULL |
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143 | }; |
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144 | |
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145 | struct pci_dev_id_match gr_rasta_adcdac_ids[] = |
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146 | { |
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147 | PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_ADCDAC), |
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148 | PCIID_END_TABLE /* Mark end of table */ |
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149 | }; |
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150 | |
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151 | struct pci_drv_info gr_rasta_adcdac_info = |
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152 | { |
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153 | { |
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154 | DRVMGR_OBJ_DRV, /* Driver */ |
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155 | NULL, /* Next driver */ |
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156 | NULL, /* Device list */ |
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157 | DRIVER_PCI_GAISLER_RASTAADCDAC_ID,/* Driver ID */ |
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158 | "GR-RASTA-ADCDAC_DRV", /* Driver Name */ |
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159 | DRVMGR_BUS_TYPE_PCI, /* Bus Type */ |
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160 | &gr_rasta_adcdac_ops, |
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161 | NULL, /* Funcs */ |
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162 | 0, /* No devices yet */ |
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163 | 0, |
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164 | }, |
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165 | &gr_rasta_adcdac_ids[0] |
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166 | }; |
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167 | |
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168 | /* Driver resources configuration for the AMBA bus on the GR-RASTA-ADCDAC board. |
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169 | * It is declared weak so that the user may override it from the project file, |
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170 | * if the default settings are not enough. |
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171 | * |
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172 | * The configuration consists of an array of configuration pointers, each |
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173 | * pointer determine the configuration of one GR-RASTA-ADCDAC board. Pointer |
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174 | * zero is for board0, pointer 1 for board1 and so on. |
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175 | * |
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176 | * The array must end with a NULL pointer. |
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177 | */ |
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178 | struct drvmgr_bus_res *gr_rasta_adcdac_resources[] __attribute__((weak)) = |
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179 | { |
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180 | NULL |
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181 | }; |
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182 | int gr_rasta_adcdac_resources_cnt = 0; |
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183 | |
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184 | void gr_rasta_adcdac_register_drv(void) |
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185 | { |
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186 | DBG("Registering GR-RASTA-ADCDAC PCI driver\n"); |
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187 | drvmgr_drv_register(&gr_rasta_adcdac_info.general); |
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188 | } |
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189 | |
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190 | void gr_rasta_adcdac_isr (void *arg) |
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191 | { |
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192 | struct gr_rasta_adcdac_priv *priv = arg; |
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193 | unsigned int status, tmp; |
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194 | int irq; |
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195 | tmp = status = priv->irq->ipend; |
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196 | |
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197 | /* DBG("GR-RASTA-ADCDAC: IRQ 0x%x\n",status); */ |
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198 | |
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199 | for(irq=0; irq<16; irq++) { |
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200 | if ( status & (1<<irq) ) { |
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201 | genirq_doirq(priv->genirq, irq); |
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202 | priv->irq->iclear = (1<<irq); |
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203 | status &= ~(1<<irq); |
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204 | if ( status == 0 ) |
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205 | break; |
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206 | } |
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207 | } |
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208 | |
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209 | /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */ |
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210 | if ( tmp ) |
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211 | drvmgr_interrupt_clear(priv->dev, 0); |
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212 | |
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213 | DBG("RASTA-ADCDAC-IRQ: 0x%x\n", tmp); |
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214 | } |
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215 | |
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216 | int gr_rasta_adcdac_hw_init1(struct gr_rasta_adcdac_priv *priv) |
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217 | { |
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218 | uint32_t data; |
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219 | unsigned int *page0 = NULL; |
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220 | struct ambapp_dev *tmp; |
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221 | int status; |
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222 | struct ambapp_ahb_info *ahb; |
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223 | struct pci_dev_info *devinfo = priv->devinfo; |
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224 | uint32_t bar0, bar0_size; |
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225 | |
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226 | /* Select version of GR-RASTA-ADCDAC board */ |
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227 | switch (devinfo->rev) { |
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228 | case 0: |
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229 | priv->version = &gr_rasta_adcdac_ver0; |
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230 | break; |
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231 | default: |
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232 | return -2; |
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233 | } |
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234 | |
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235 | bar0 = devinfo->resources[0].address; |
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236 | bar0_size = devinfo->resources[0].size; |
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237 | page0 = (unsigned int *)(bar0 + bar0_size/2); |
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238 | |
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239 | /* Point PAGE0 to start of Plug and Play information */ |
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240 | *page0 = priv->version->amba_ioarea & 0xf0000000; |
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241 | |
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242 | /* set parity error response */ |
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243 | pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data); |
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244 | pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY)); |
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245 | |
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246 | /* Setup cache line size. Default cache line size will result in |
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247 | * poor performance (256 word fetches), 0xff will set it according |
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248 | * to the max size of the PCI FIFO. |
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249 | */ |
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250 | pci_cfg_w8(priv->pcidev, PCI_CACHE_LINE_SIZE, 0xff); |
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251 | |
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252 | /* Scan AMBA Plug&Play */ |
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253 | |
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254 | /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */ |
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255 | priv->amba_maps[0].size = bar0_size/2; |
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256 | priv->amba_maps[0].local_adr = bar0; |
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257 | priv->amba_maps[0].remote_adr = 0x80000000; |
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258 | |
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259 | /* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */ |
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260 | priv->amba_maps[1].size = devinfo->resources[1].size; |
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261 | priv->amba_maps[1].local_adr = devinfo->resources[1].address; |
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262 | priv->amba_maps[1].remote_adr = 0x40000000; |
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263 | |
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264 | /* Addresses not matching with map be untouched */ |
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265 | priv->amba_maps[2].size = 0xfffffff0; |
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266 | priv->amba_maps[2].local_adr = 0; |
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267 | priv->amba_maps[2].remote_adr = 0; |
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268 | |
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269 | /* Mark end of table */ |
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270 | priv->amba_maps[3].size=0; |
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271 | priv->amba_maps[3].local_adr = 0; |
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272 | priv->amba_maps[3].remote_adr = 0; |
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273 | |
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274 | /* Start AMBA PnP scan at first AHB bus */ |
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275 | /*ambapp_scan(priv->bar0 + (priv->version->amba_ioarea & ~0xf0000000), |
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276 | NULL, &priv->amba_maps[0], NULL, &priv->abus.root, NULL);*/ |
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277 | ambapp_scan(&priv->abus, |
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278 | bar0 + (priv->version->amba_ioarea & ~0xf0000000), |
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279 | NULL, &priv->amba_maps[0]); |
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280 | |
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281 | /* Initialize Frequency of AMBA bus */ |
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282 | ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz); |
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283 | |
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284 | /* Point PAGE0 to start of APB area */ |
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285 | *page0 = 0x80000000; |
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286 | |
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287 | /* Find GRPCI controller */ |
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288 | tmp = (void *)ambapp_for_each(&priv->abus, |
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289 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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290 | VENDOR_GAISLER, GAISLER_PCIFBRG, |
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291 | ambapp_find_by_idx, NULL); |
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292 | if ( !tmp ) { |
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293 | return -3; |
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294 | } |
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295 | priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start; |
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296 | |
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297 | /* Set GRPCI mmap so that AMBA masters can access CPU-RAM over |
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298 | * the PCI window. |
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299 | */ |
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300 | priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) | |
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301 | (priv->ahbmst2pci_map & 0xf0000000); |
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302 | priv->grpci->page1 = 0x40000000; |
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303 | |
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304 | /* Find IRQ controller */ |
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305 | tmp = (void *)ambapp_for_each(&priv->abus, |
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306 | (OPTIONS_ALL|OPTIONS_APB_SLVS), |
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307 | VENDOR_GAISLER, GAISLER_IRQMP, |
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308 | ambapp_find_by_idx, NULL); |
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309 | if ( !tmp ) { |
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310 | return -4; |
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311 | } |
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312 | priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start; |
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313 | /* Set up GR-RASTA-ADCDAC irq controller */ |
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314 | priv->irq->iclear = 0xffff; |
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315 | priv->irq->ilevel = 0; |
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316 | priv->irq->mask[0] = 0; |
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317 | |
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318 | /* DOWN streams translation table */ |
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319 | priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA"; |
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320 | priv->bus_maps_down[0].size = priv->amba_maps[0].size; |
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321 | priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr; |
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322 | priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr; |
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323 | |
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324 | priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA"; |
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325 | priv->bus_maps_down[1].size = priv->amba_maps[1].size; |
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326 | priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr; |
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327 | priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr; |
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328 | |
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329 | /* Mark end of translation table */ |
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330 | priv->bus_maps_down[2].size = 0; |
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331 | |
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332 | /* Find GRPCI controller AHB Slave interface */ |
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333 | tmp = (void *)ambapp_for_each(&priv->abus, |
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334 | (OPTIONS_ALL|OPTIONS_AHB_SLVS), |
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335 | VENDOR_GAISLER, GAISLER_PCIFBRG, |
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336 | ambapp_find_by_idx, NULL); |
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337 | if ( !tmp ) { |
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338 | return -5; |
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339 | } |
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340 | ahb = (struct ambapp_ahb_info *)tmp->devinfo; |
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341 | |
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342 | /* UP streams translation table */ |
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343 | priv->bus_maps_up[0].name = "AMBA GRPCI Window"; |
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344 | priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-ADCDAC board */ |
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345 | priv->bus_maps_up[0].from_adr = (void *)ahb->start[0]; |
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346 | priv->bus_maps_up[0].to_adr = (void *) |
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347 | (priv->ahbmst2pci_map & 0xf0000000); |
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348 | |
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349 | /* Mark end of translation table */ |
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350 | priv->bus_maps_up[1].size = 0; |
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351 | |
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352 | /* Successfully registered the RASTA board */ |
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353 | return 0; |
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354 | } |
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355 | |
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356 | int gr_rasta_adcdac_hw_init2(struct gr_rasta_adcdac_priv *priv) |
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357 | { |
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358 | /* Enable DMA by enabling PCI target as master */ |
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359 | pci_master_enable(priv->pcidev); |
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360 | |
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361 | return DRVMGR_OK; |
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362 | } |
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363 | |
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364 | /* Called when a PCI target is found with the PCI device and vendor ID |
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365 | * given in gr_rasta_adcdac_ids[]. |
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366 | */ |
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367 | int gr_rasta_adcdac_init1(struct drvmgr_dev *dev) |
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368 | { |
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369 | struct gr_rasta_adcdac_priv *priv; |
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370 | struct pci_dev_info *devinfo; |
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371 | int status; |
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372 | uint32_t bar0, bar1, bar0_size, bar1_size; |
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373 | union drvmgr_key_value *value; |
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374 | |
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375 | priv = malloc(sizeof(struct gr_rasta_adcdac_priv)); |
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376 | if ( !priv ) |
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377 | return DRVMGR_NOMEM; |
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378 | |
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379 | memset(priv, 0, sizeof(*priv)); |
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380 | dev->priv = priv; |
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381 | priv->dev = dev; |
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382 | |
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383 | /* Determine number of configurations */ |
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384 | if ( gr_rasta_adcdac_resources_cnt == 0 ) { |
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385 | while ( gr_rasta_adcdac_resources[gr_rasta_adcdac_resources_cnt] ) |
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386 | gr_rasta_adcdac_resources_cnt++; |
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387 | } |
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388 | |
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389 | /* Generate Device prefix */ |
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390 | |
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391 | strcpy(priv->prefix, "/dev/rastaadcdac0"); |
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392 | priv->prefix[16] += dev->minor_drv; |
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393 | mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO); |
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394 | priv->prefix[17] = '/'; |
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395 | priv->prefix[18] = '\0'; |
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396 | |
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397 | priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo; |
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398 | priv->pcidev = devinfo->pcidev; |
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399 | bar0 = devinfo->resources[0].address; |
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400 | bar0_size = devinfo->resources[0].size; |
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401 | bar1 = devinfo->resources[1].address; |
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402 | bar1_size = devinfo->resources[1].size; |
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403 | printf("\n\n--- GR-RASTA-ADCDAC[%d] ---\n", dev->minor_drv); |
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404 | printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n", |
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405 | PCI_DEV_EXPAND(priv->pcidev)); |
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406 | printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n", |
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407 | devinfo->id.vendor, devinfo->id.device); |
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408 | printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1); |
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409 | printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1); |
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410 | printf(" IRQ: %d\n\n\n", devinfo->irq); |
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411 | |
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412 | /* all neccessary space assigned to GR-RASTA-ADCDAC target? */ |
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413 | if ((bar0_size == 0) || (bar1_size == 0)) |
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414 | return DRVMGR_ENORES; |
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415 | |
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416 | /* Let user override which PCI address the AHB masters of the |
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417 | * RASTA-ADCDAC board access when doing DMA to CPU RAM. The AHB masters |
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418 | * access the PCI Window of the AMBA bus, the MSB 4-bits of that address |
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419 | * is translated according this config option before the address |
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420 | * goes out on the PCI bus. |
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421 | * Only the 4 MSB bits have an effect; |
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422 | */ |
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423 | value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT); |
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424 | if (value) |
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425 | priv->ahbmst2pci_map = value->i; |
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426 | else |
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427 | priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */ |
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428 | |
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429 | priv->genirq = genirq_init(16); |
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430 | if ( priv->genirq == NULL ) { |
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431 | free(priv); |
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432 | dev->priv = NULL; |
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433 | return DRVMGR_FAIL; |
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434 | } |
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435 | |
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436 | if ( (status = gr_rasta_adcdac_hw_init1(priv)) != 0 ) { |
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437 | genirq_destroy(priv->genirq); |
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438 | free(priv); |
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439 | dev->priv = NULL; |
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440 | printf(" Failed to initialize GR-RASTA-ADCDAC HW: %d\n", status); |
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441 | return DRVMGR_FAIL; |
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442 | } |
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443 | |
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444 | /* Init amba bus */ |
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445 | priv->config.abus = &priv->abus; |
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446 | priv->config.ops = &ambapp_rasta_adcdac_ops; |
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447 | priv->config.maps_up = &priv->bus_maps_up[0]; |
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448 | priv->config.maps_down = &priv->bus_maps_down[0]; |
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449 | if ( priv->dev->minor_drv < gr_rasta_adcdac_resources_cnt ) { |
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450 | priv->config.resources = gr_rasta_adcdac_resources[priv->dev->minor_drv]; |
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451 | } else { |
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452 | priv->config.resources = NULL; |
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453 | } |
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454 | |
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455 | /* Create and register AMBA PnP bus. */ |
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456 | return ambapp_bus_register(dev, &priv->config); |
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457 | } |
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458 | |
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459 | int gr_rasta_adcdac_init2(struct drvmgr_dev *dev) |
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460 | { |
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461 | struct gr_rasta_adcdac_priv *priv = dev->priv; |
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462 | |
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463 | /* Clear any old interrupt requests */ |
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464 | drvmgr_interrupt_clear(dev, 0); |
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465 | |
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466 | /* Enable System IRQ so that GR-RASTA-ADCDAC PCI target interrupt |
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467 | * goes through. |
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468 | * |
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469 | * It is important to enable it in stage init2. If interrupts were |
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470 | * enabled in init1 this might hang the system when more than one |
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471 | * PCI board is connected, this is because PCI interrupts might |
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472 | * be shared and PCI board 2 have not initialized and might |
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473 | * therefore drive interrupt already when entering init1(). |
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474 | */ |
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475 | drvmgr_interrupt_register( |
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476 | dev, |
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477 | 0, |
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478 | "gr_rasta_adcdac", |
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479 | gr_rasta_adcdac_isr, |
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480 | (void *)priv); |
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481 | |
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482 | return gr_rasta_adcdac_hw_init2(priv); |
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483 | } |
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484 | |
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485 | int ambapp_rasta_adcdac_int_register( |
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486 | struct drvmgr_dev *dev, |
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487 | int irq, |
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488 | const char *info, |
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489 | drvmgr_isr handler, |
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490 | void *arg) |
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491 | { |
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492 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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493 | rtems_interrupt_level level; |
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494 | int status; |
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495 | |
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496 | rtems_interrupt_disable(level); |
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497 | |
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498 | status = genirq_register(priv->genirq, irq, handler, arg); |
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499 | if ( status == 0 ) { |
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500 | /* Clear IRQ for first registered handler */ |
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501 | priv->irq->iclear = (1<<irq); |
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502 | } else if ( status == 1 ) |
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503 | status = 0; |
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504 | |
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505 | if (status != 0) { |
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506 | rtems_interrupt_enable(level); |
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507 | return DRVMGR_FAIL; |
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508 | } |
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509 | |
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510 | status = genirq_enable(priv->genirq, irq, handler, arg); |
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511 | if ( status == 0 ) { |
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512 | /* Enable IRQ for first enabled handler only */ |
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513 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
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514 | } else if ( status == 1 ) |
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515 | status = 0; |
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516 | |
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517 | rtems_interrupt_enable(level); |
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518 | |
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519 | return status; |
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520 | } |
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521 | |
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522 | int ambapp_rasta_adcdac_int_unregister( |
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523 | struct drvmgr_dev *dev, |
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524 | int irq, |
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525 | drvmgr_isr isr, |
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526 | void *arg) |
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527 | { |
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528 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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529 | rtems_interrupt_level level; |
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530 | int status; |
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531 | |
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532 | rtems_interrupt_disable(level); |
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533 | |
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534 | status = genirq_disable(priv->genirq, irq, isr, arg); |
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535 | if ( status == 0 ) { |
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536 | /* Disable IRQ only when no enabled handler exists */ |
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537 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
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538 | } |
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539 | |
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540 | status = genirq_unregister(priv->genirq, irq, isr, arg); |
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541 | if ( status != 0 ) |
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542 | status = DRVMGR_FAIL; |
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543 | |
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544 | rtems_interrupt_enable(level); |
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545 | |
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546 | return status; |
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547 | } |
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548 | |
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549 | int ambapp_rasta_adcdac_int_unmask( |
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550 | struct drvmgr_dev *dev, |
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551 | int irq) |
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552 | { |
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553 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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554 | rtems_interrupt_level level; |
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555 | |
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556 | DBG("RASTA-ADCDAC IRQ %d: unmask\n", irq); |
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557 | |
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558 | if ( genirq_check(priv->genirq, irq) ) |
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559 | return DRVMGR_EINVAL; |
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560 | |
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561 | rtems_interrupt_disable(level); |
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562 | |
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563 | /* Enable IRQ for first enabled handler only */ |
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564 | priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */ |
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565 | |
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566 | rtems_interrupt_enable(level); |
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567 | |
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568 | return DRVMGR_OK; |
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569 | } |
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570 | |
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571 | int ambapp_rasta_adcdac_int_mask( |
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572 | struct drvmgr_dev *dev, |
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573 | int irq) |
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574 | { |
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575 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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576 | rtems_interrupt_level level; |
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577 | |
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578 | DBG("RASTA-ADCDAC IRQ %d: mask\n", irq); |
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579 | |
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580 | if ( genirq_check(priv->genirq, irq) ) |
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581 | return DRVMGR_EINVAL; |
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582 | |
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583 | rtems_interrupt_disable(level); |
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584 | |
---|
585 | /* Disable/mask IRQ */ |
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586 | priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */ |
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587 | |
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588 | rtems_interrupt_enable(level); |
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589 | |
---|
590 | return DRVMGR_OK; |
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591 | } |
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592 | |
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593 | int ambapp_rasta_adcdac_int_clear( |
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594 | struct drvmgr_dev *dev, |
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595 | int irq) |
---|
596 | { |
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597 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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598 | |
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599 | if ( genirq_check(priv->genirq, irq) ) |
---|
600 | return DRVMGR_FAIL; |
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601 | |
---|
602 | priv->irq->iclear = (1<<irq); |
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603 | |
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604 | return DRVMGR_OK; |
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605 | } |
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606 | |
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607 | int ambapp_rasta_adcdac_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params) |
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608 | { |
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609 | struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv; |
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610 | |
---|
611 | /* Device name prefix pointer, skip /dev */ |
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612 | params->dev_prefix = &priv->prefix[5]; |
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613 | |
---|
614 | return 0; |
---|
615 | } |
---|
616 | |
---|
617 | void gr_rasta_adcdac_print_dev(struct drvmgr_dev *dev, int options) |
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618 | { |
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619 | struct gr_rasta_adcdac_priv *priv = dev->priv; |
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620 | struct pci_dev_info *devinfo = priv->devinfo; |
---|
621 | uint32_t bar0, bar1, bar0_size, bar1_size; |
---|
622 | |
---|
623 | /* Print */ |
---|
624 | printf("--- GR-RASTA-ADCDAC [bus 0x%x, dev 0x%x, fun 0x%x] ---\n", |
---|
625 | PCI_DEV_EXPAND(priv->pcidev)); |
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626 | |
---|
627 | bar0 = devinfo->resources[0].address; |
---|
628 | bar0_size = devinfo->resources[0].size; |
---|
629 | bar1 = devinfo->resources[1].address; |
---|
630 | bar1_size = devinfo->resources[1].size; |
---|
631 | |
---|
632 | printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1); |
---|
633 | printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1); |
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634 | printf(" IRQ REGS: 0x%x\n", (unsigned int)priv->irq); |
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635 | printf(" IRQ: %d\n", devinfo->irq); |
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636 | printf(" PCI REVISION: %d\n", devinfo->rev); |
---|
637 | printf(" FREQ: %d Hz\n", priv->version->amba_freq_hz); |
---|
638 | printf(" IMASK: 0x%08x\n", priv->irq->mask[0]); |
---|
639 | printf(" IPEND: 0x%08x\n", priv->irq->ipend); |
---|
640 | |
---|
641 | /* Print amba config */ |
---|
642 | if ( options & RASTA_ADCDAC_OPTIONS_AMBA ) { |
---|
643 | ambapp_print(&priv->abus, 10); |
---|
644 | } |
---|
645 | #if 0 |
---|
646 | /* Print IRQ handlers and their arguments */ |
---|
647 | if ( options & RASTA_ADCDAC_OPTIONS_IRQ ) { |
---|
648 | int i; |
---|
649 | for(i=0; i<16; i++) { |
---|
650 | printf(" IRQ[%02d]: 0x%x, arg: 0x%x\n", |
---|
651 | i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg); |
---|
652 | } |
---|
653 | } |
---|
654 | #endif |
---|
655 | } |
---|
656 | |
---|
657 | void gr_rasta_adcdac_print(int options) |
---|
658 | { |
---|
659 | struct pci_drv_info *drv = &gr_rasta_adcdac_info; |
---|
660 | struct drvmgr_dev *dev; |
---|
661 | |
---|
662 | dev = drv->general.dev; |
---|
663 | while(dev) { |
---|
664 | gr_rasta_adcdac_print_dev(dev, options); |
---|
665 | dev = dev->next_in_drv; |
---|
666 | } |
---|
667 | } |
---|