source: rtems/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c @ 819de55b

4.115
Last change on this file since 819de55b was 819de55b, checked in by Daniel Hellstrom <daniel@…>, on 03/18/13 at 07:29:39

PCI-RASTA: set GRPCI1 target cache-line-size to avoid poor performance

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1/*  GR-RASTA-ADCDAC PCI Target driver.
2 *
3 *  COPYRIGHT (c) 2008.
4 *  Cobham Gaisler AB.
5 *
6 *  Configures the GR-RASTA-ADCDAC interface PCI board.
7 *  This driver provides a AMBA PnP bus by using the general part
8 *  of the AMBA PnP bus driver (ambapp_bus.c).
9 *
10 *  Driver resources for the AMBA PnP bus provided can be set using
11 *  gr_rasta_adcdac_set_resources().
12 *
13 *  The license and distribution terms for this file may be
14 *  found in found in the file LICENSE in this distribution or at
15 *  http://www.rtems.com/license/LICENSE.
16 */
17
18#include <stdio.h>
19#include <stdlib.h>
20#include <string.h>
21#include <sys/types.h>
22#include <sys/stat.h>
23
24#include <bsp.h>
25#include <rtems/bspIo.h>
26#include <pci.h>
27
28#include <ambapp.h>
29#include <grlib.h>
30#include <drvmgr/drvmgr.h>
31#include <drvmgr/ambapp_bus.h>
32#include <drvmgr/pci_bus.h>
33#include <genirq.h>
34
35#include <gr_rasta_adcdac.h>
36
37/*#define DEBUG 1*/
38
39#ifdef DEBUG
40#define DBG(x...) printk(x)
41#else
42#define DBG(x...)
43#endif
44
45/* Determines which PCI address the AHB masters will access, it should be
46 * set so that the masters can access the CPU RAM. Default is base of CPU RAM,
47 * CPU RAM is mapped 1:1 to PCI space.
48 */
49extern unsigned int _RAM_START;
50#define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000)
51
52/* PCI ID */
53#define PCIID_VENDOR_GAISLER            0x1AC8
54#define PCIID_DEVICE_GR_RASTA_ADCDAC    0x0014
55
56int gr_rasta_adcdac_init1(struct drvmgr_dev *dev);
57int gr_rasta_adcdac_init2(struct drvmgr_dev *dev);
58
59struct grpci_regs {
60        volatile unsigned int cfg_stat;
61        volatile unsigned int bar0;
62        volatile unsigned int page0;
63        volatile unsigned int bar1;
64        volatile unsigned int page1;
65        volatile unsigned int iomap;
66        volatile unsigned int stat_cmd;
67};
68
69struct gr_rasta_adcdac_ver {
70        const unsigned int      amba_freq_hz;   /* The frequency */
71        const unsigned int      amba_ioarea;    /* The address where the PnP IOAREA starts at */
72};
73
74/* Private data structure for driver */
75struct gr_rasta_adcdac_priv {
76        /* Driver management */
77        struct drvmgr_dev       *dev;
78        char                            prefix[20];
79
80        /* PCI */
81        pci_dev_t                       pcidev;
82        struct pci_dev_info             *devinfo;
83        uint32_t                        ahbmst2pci_map;
84
85        /* IRQ */
86        genirq_t                        genirq;
87
88        /* GR-RASTA-ADCDAC */
89        struct gr_rasta_adcdac_ver      *version;
90        struct irqmp_regs               *irq;
91        struct grpci_regs               *grpci;
92        struct drvmgr_map_entry         bus_maps_down[3];
93        struct drvmgr_map_entry         bus_maps_up[2];
94
95        /* AMBA Plug&Play information on GR-RASTA-ADCDAC */
96        struct ambapp_bus               abus;
97        struct ambapp_mmap              amba_maps[4];
98        struct ambapp_config            config;
99};
100
101struct gr_rasta_adcdac_ver gr_rasta_adcdac_ver0 = {
102        .amba_freq_hz           = 50000000,
103        .amba_ioarea            = 0x80100000,
104};
105
106int ambapp_rasta_adcdac_int_register(
107        struct drvmgr_dev *dev,
108        int irq,
109        const char *info,
110        drvmgr_isr handler,
111        void *arg);
112int ambapp_rasta_adcdac_int_unregister(
113        struct drvmgr_dev *dev,
114        int irq,
115        drvmgr_isr isr,
116        void *arg);
117int ambapp_rasta_adcdac_int_unmask(
118        struct drvmgr_dev *dev,
119        int irq);
120int ambapp_rasta_adcdac_int_mask(
121        struct drvmgr_dev *dev,
122        int irq);
123int ambapp_rasta_adcdac_int_clear(
124        struct drvmgr_dev *dev,
125        int irq);
126int ambapp_rasta_adcdac_get_params(
127        struct drvmgr_dev *dev,
128        struct drvmgr_bus_params *params);
129
130struct ambapp_ops ambapp_rasta_adcdac_ops = {
131        .int_register = ambapp_rasta_adcdac_int_register,
132        .int_unregister = ambapp_rasta_adcdac_int_unregister,
133        .int_unmask = ambapp_rasta_adcdac_int_unmask,
134        .int_mask = ambapp_rasta_adcdac_int_mask,
135        .int_clear = ambapp_rasta_adcdac_int_clear,
136        .get_params = ambapp_rasta_adcdac_get_params
137};
138
139struct drvmgr_drv_ops gr_rasta_adcdac_ops =
140{       .init = {gr_rasta_adcdac_init1, gr_rasta_adcdac_init2, NULL, NULL},
141        .remove = NULL,
142        .info = NULL
143};
144
145struct pci_dev_id_match gr_rasta_adcdac_ids[] =
146{
147        PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_ADCDAC),
148        PCIID_END_TABLE /* Mark end of table */
149};
150
151struct pci_drv_info gr_rasta_adcdac_info =
152{
153        {
154                DRVMGR_OBJ_DRV,                 /* Driver */
155                NULL,                           /* Next driver */
156                NULL,                           /* Device list */
157                DRIVER_PCI_GAISLER_RASTAADCDAC_ID,/* Driver ID */
158                "GR-RASTA-ADCDAC_DRV",          /* Driver Name */
159                DRVMGR_BUS_TYPE_PCI,            /* Bus Type */
160                &gr_rasta_adcdac_ops,
161                NULL,                           /* Funcs */
162                0,                              /* No devices yet */
163                0,
164        },
165        &gr_rasta_adcdac_ids[0]
166};
167
168/* Driver resources configuration for the AMBA bus on the GR-RASTA-ADCDAC board.
169 * It is declared weak so that the user may override it from the project file,
170 * if the default settings are not enough.
171 *
172 * The configuration consists of an array of configuration pointers, each
173 * pointer determine the configuration of one GR-RASTA-ADCDAC board. Pointer
174 * zero is for board0, pointer 1 for board1 and so on.
175 *
176 * The array must end with a NULL pointer.
177 */
178struct drvmgr_bus_res *gr_rasta_adcdac_resources[] __attribute__((weak)) =
179{
180        NULL
181};
182int gr_rasta_adcdac_resources_cnt = 0;
183
184void gr_rasta_adcdac_register_drv(void)
185{
186        DBG("Registering GR-RASTA-ADCDAC PCI driver\n");
187        drvmgr_drv_register(&gr_rasta_adcdac_info.general);
188}
189
190void gr_rasta_adcdac_isr (void *arg)
191{
192        struct gr_rasta_adcdac_priv *priv = arg;
193        unsigned int status, tmp;
194        int irq;
195        tmp = status = priv->irq->ipend;
196
197        /* DBG("GR-RASTA-ADCDAC: IRQ 0x%x\n",status); */
198
199        for(irq=0; irq<16; irq++) {
200                if ( status & (1<<irq) ) {
201                        genirq_doirq(priv->genirq, irq);
202                        priv->irq->iclear = (1<<irq);
203                        status &= ~(1<<irq);
204                        if ( status == 0 )
205                                break;
206                }
207        }
208
209        /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */
210        if ( tmp )
211                drvmgr_interrupt_clear(priv->dev, 0);
212
213        DBG("RASTA-ADCDAC-IRQ: 0x%x\n", tmp);
214}
215
216int gr_rasta_adcdac_hw_init1(struct gr_rasta_adcdac_priv *priv)
217{
218        uint32_t data;
219        unsigned int *page0 = NULL;
220        struct ambapp_dev *tmp;
221        int status;
222        struct ambapp_ahb_info *ahb;
223        struct pci_dev_info *devinfo = priv->devinfo;
224        uint32_t bar0, bar0_size;
225
226        /* Select version of GR-RASTA-ADCDAC board */
227        switch (devinfo->rev) {
228                case 0:
229                        priv->version = &gr_rasta_adcdac_ver0;
230                        break;
231                default:
232                        return -2;
233        }
234
235        bar0 = devinfo->resources[0].address;
236        bar0_size = devinfo->resources[0].size;
237        page0 = (unsigned int *)(bar0 + bar0_size/2);
238
239        /* Point PAGE0 to start of Plug and Play information */
240        *page0 = priv->version->amba_ioarea & 0xf0000000;
241
242        /* set parity error response */
243        pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data);
244        pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
245
246        /* Setup cache line size. Default cache line size will result in
247         * poor performance (256 word fetches), 0xff will set it according
248         * to the max size of the PCI FIFO.
249         */
250        pci_cfg_w8(priv->pcidev, PCI_CACHE_LINE_SIZE, 0xff);
251
252        /* Scan AMBA Plug&Play */
253
254        /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */
255        priv->amba_maps[0].size = bar0_size/2;
256        priv->amba_maps[0].local_adr = bar0;
257        priv->amba_maps[0].remote_adr = 0x80000000;
258
259        /* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */
260        priv->amba_maps[1].size = devinfo->resources[1].size;
261        priv->amba_maps[1].local_adr = devinfo->resources[1].address;
262        priv->amba_maps[1].remote_adr = 0x40000000;
263
264        /* Addresses not matching with map be untouched */
265        priv->amba_maps[2].size = 0xfffffff0;
266        priv->amba_maps[2].local_adr = 0;
267        priv->amba_maps[2].remote_adr = 0;
268
269        /* Mark end of table */
270        priv->amba_maps[3].size=0;
271        priv->amba_maps[3].local_adr = 0;
272        priv->amba_maps[3].remote_adr = 0;
273
274        /* Start AMBA PnP scan at first AHB bus */
275        /*ambapp_scan(priv->bar0 + (priv->version->amba_ioarea & ~0xf0000000),
276                NULL, &priv->amba_maps[0], NULL, &priv->abus.root, NULL);*/
277        ambapp_scan(&priv->abus,
278                bar0 + (priv->version->amba_ioarea & ~0xf0000000),
279                NULL, &priv->amba_maps[0]);
280
281        /* Initialize Frequency of AMBA bus */
282        ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz);
283
284        /* Point PAGE0 to start of APB area */
285        *page0 = 0x80000000;   
286
287        /* Find GRPCI controller */
288        tmp = (void *)ambapp_for_each(&priv->abus,
289                                        (OPTIONS_ALL|OPTIONS_APB_SLVS),
290                                        VENDOR_GAISLER, GAISLER_PCIFBRG,
291                                        ambapp_find_by_idx, NULL);
292        if ( !tmp ) {
293                return -3;
294        }
295        priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start;
296
297        /* Set GRPCI mmap so that AMBA masters can access CPU-RAM over
298         * the PCI window.
299         */
300        priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) |
301                                (priv->ahbmst2pci_map & 0xf0000000);
302        priv->grpci->page1 = 0x40000000;
303
304        /* Find IRQ controller */
305        tmp = (void *)ambapp_for_each(&priv->abus,
306                                        (OPTIONS_ALL|OPTIONS_APB_SLVS),
307                                        VENDOR_GAISLER, GAISLER_IRQMP,
308                                        ambapp_find_by_idx, NULL);
309        if ( !tmp ) {
310                return -4;
311        }
312        priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
313        /* Set up GR-RASTA-ADCDAC irq controller */
314        priv->irq->iclear = 0xffff;
315        priv->irq->ilevel = 0;
316        priv->irq->mask[0] = 0;
317
318        /* DOWN streams translation table */
319        priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
320        priv->bus_maps_down[0].size = priv->amba_maps[0].size;
321        priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
322        priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
323
324        priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA";
325        priv->bus_maps_down[1].size = priv->amba_maps[1].size;
326        priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr;
327        priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr;
328
329        /* Mark end of translation table */
330        priv->bus_maps_down[2].size = 0;
331
332        /* Find GRPCI controller AHB Slave interface */
333        tmp = (void *)ambapp_for_each(&priv->abus,
334                                        (OPTIONS_ALL|OPTIONS_AHB_SLVS),
335                                        VENDOR_GAISLER, GAISLER_PCIFBRG,
336                                        ambapp_find_by_idx, NULL);
337        if ( !tmp ) {
338                return -5;
339        }
340        ahb = (struct ambapp_ahb_info *)tmp->devinfo;
341
342        /* UP streams translation table */
343        priv->bus_maps_up[0].name = "AMBA GRPCI Window";
344        priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-ADCDAC board */
345        priv->bus_maps_up[0].from_adr = (void *)ahb->start[0];
346        priv->bus_maps_up[0].to_adr = (void *)
347                                        (priv->ahbmst2pci_map & 0xf0000000);
348
349        /* Mark end of translation table */
350        priv->bus_maps_up[1].size = 0;
351
352        /* Successfully registered the RASTA board */
353        return 0;
354}
355
356int gr_rasta_adcdac_hw_init2(struct gr_rasta_adcdac_priv *priv)
357{
358        /* Enable DMA by enabling PCI target as master */
359        pci_master_enable(priv->pcidev);
360
361        return DRVMGR_OK;
362}
363
364/* Called when a PCI target is found with the PCI device and vendor ID
365 * given in gr_rasta_adcdac_ids[].
366 */
367int gr_rasta_adcdac_init1(struct drvmgr_dev *dev)
368{
369        struct gr_rasta_adcdac_priv *priv;
370        struct pci_dev_info *devinfo;
371        int status;
372        uint32_t bar0, bar1, bar0_size, bar1_size;
373        union drvmgr_key_value *value;
374
375        priv = malloc(sizeof(struct gr_rasta_adcdac_priv));
376        if ( !priv )
377                return DRVMGR_NOMEM;
378
379        memset(priv, 0, sizeof(*priv));
380        dev->priv = priv;
381        priv->dev = dev;
382
383        /* Determine number of configurations */
384        if ( gr_rasta_adcdac_resources_cnt == 0 ) {
385                while ( gr_rasta_adcdac_resources[gr_rasta_adcdac_resources_cnt] )
386                        gr_rasta_adcdac_resources_cnt++;
387        }
388
389        /* Generate Device prefix */
390
391        strcpy(priv->prefix, "/dev/rastaadcdac0");
392        priv->prefix[16] += dev->minor_drv;
393        mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
394        priv->prefix[17] = '/';
395        priv->prefix[18] = '\0';
396
397        priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
398        priv->pcidev = devinfo->pcidev;
399        bar0 = devinfo->resources[0].address;
400        bar0_size = devinfo->resources[0].size;
401        bar1 = devinfo->resources[1].address;
402        bar1_size = devinfo->resources[1].size;
403        printf("\n\n--- GR-RASTA-ADCDAC[%d] ---\n", dev->minor_drv);
404        printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
405                PCI_DEV_EXPAND(priv->pcidev));
406        printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n",
407                devinfo->id.vendor, devinfo->id.device);
408        printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
409        printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
410        printf(" IRQ: %d\n\n\n", devinfo->irq);
411
412        /* all neccessary space assigned to GR-RASTA-ADCDAC target? */
413        if ((bar0_size == 0) || (bar1_size == 0))
414                return DRVMGR_ENORES;
415
416        /* Let user override which PCI address the AHB masters of the
417         * RASTA-ADCDAC board access when doing DMA to CPU RAM. The AHB masters
418         * access the PCI Window of the AMBA bus, the MSB 4-bits of that address
419         * is translated according this config option before the address
420         * goes out on the PCI bus.
421         * Only the 4 MSB bits have an effect;
422         */
423        value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT);
424        if (value)
425                priv->ahbmst2pci_map = value->i;
426        else
427                priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */
428
429        priv->genirq = genirq_init(16);
430        if ( priv->genirq == NULL ) {
431                free(priv);
432                dev->priv = NULL;
433                return DRVMGR_FAIL;
434        }
435
436        if ( (status = gr_rasta_adcdac_hw_init1(priv)) != 0 ) {
437                genirq_destroy(priv->genirq);
438                free(priv);
439                dev->priv = NULL;
440                printf(" Failed to initialize GR-RASTA-ADCDAC HW: %d\n", status);
441                return DRVMGR_FAIL;
442        }
443
444        /* Init amba bus */
445        priv->config.abus = &priv->abus;
446        priv->config.ops = &ambapp_rasta_adcdac_ops;
447        priv->config.maps_up = &priv->bus_maps_up[0];
448        priv->config.maps_down = &priv->bus_maps_down[0];
449        if ( priv->dev->minor_drv < gr_rasta_adcdac_resources_cnt ) {
450                priv->config.resources = gr_rasta_adcdac_resources[priv->dev->minor_drv];
451        } else {
452                priv->config.resources = NULL;
453        }
454
455        /* Create and register AMBA PnP bus. */
456        return ambapp_bus_register(dev, &priv->config);
457}
458
459int gr_rasta_adcdac_init2(struct drvmgr_dev *dev)
460{
461        struct gr_rasta_adcdac_priv *priv = dev->priv;
462
463        /* Clear any old interrupt requests */
464        drvmgr_interrupt_clear(dev, 0);
465
466        /* Enable System IRQ so that GR-RASTA-ADCDAC PCI target interrupt
467         * goes through.
468         *
469         * It is important to enable it in stage init2. If interrupts were
470         * enabled in init1 this might hang the system when more than one
471         * PCI board is connected, this is because PCI interrupts might
472         * be shared and PCI board 2 have not initialized and might
473         * therefore drive interrupt already when entering init1().
474         */
475        drvmgr_interrupt_register(
476                dev,
477                0,
478                "gr_rasta_adcdac",
479                gr_rasta_adcdac_isr,
480                (void *)priv);
481
482        return gr_rasta_adcdac_hw_init2(priv);
483}
484
485int ambapp_rasta_adcdac_int_register(
486        struct drvmgr_dev *dev,
487        int irq,
488        const char *info,
489        drvmgr_isr handler,
490        void *arg)
491{
492        struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
493        rtems_interrupt_level level;
494        int status;
495
496        rtems_interrupt_disable(level);
497
498        status = genirq_register(priv->genirq, irq, handler, arg);
499        if ( status == 0 ) {
500                /* Clear IRQ for first registered handler */
501                priv->irq->iclear = (1<<irq);
502        } else if ( status == 1 )
503                status = 0;
504
505        if (status != 0) {
506                rtems_interrupt_enable(level);
507                return DRVMGR_FAIL;
508        }
509
510        status = genirq_enable(priv->genirq, irq, handler, arg);
511        if ( status == 0 ) {
512                /* Enable IRQ for first enabled handler only */
513                priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
514        } else if ( status == 1 )
515                status = 0;
516
517        rtems_interrupt_enable(level);
518
519        return status;
520}
521
522int ambapp_rasta_adcdac_int_unregister(
523        struct drvmgr_dev *dev,
524        int irq,
525        drvmgr_isr isr,
526        void *arg)
527{
528        struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
529        rtems_interrupt_level level;
530        int status;
531
532        rtems_interrupt_disable(level);
533
534        status = genirq_disable(priv->genirq, irq, isr, arg);
535        if ( status == 0 ) {
536                /* Disable IRQ only when no enabled handler exists */
537                priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
538        }
539
540        status = genirq_unregister(priv->genirq, irq, isr, arg);
541        if ( status != 0 )
542                status = DRVMGR_FAIL;
543
544        rtems_interrupt_enable(level);
545
546        return status;
547}
548
549int ambapp_rasta_adcdac_int_unmask(
550        struct drvmgr_dev *dev,
551        int irq)
552{
553        struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
554        rtems_interrupt_level level;
555
556        DBG("RASTA-ADCDAC IRQ %d: unmask\n", irq);
557
558        if ( genirq_check(priv->genirq, irq) )
559                return DRVMGR_EINVAL;
560
561        rtems_interrupt_disable(level);
562
563        /* Enable IRQ for first enabled handler only */
564        priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
565
566        rtems_interrupt_enable(level);
567
568        return DRVMGR_OK;
569}
570
571int ambapp_rasta_adcdac_int_mask(
572        struct drvmgr_dev *dev,
573        int irq)
574{
575        struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
576        rtems_interrupt_level level;
577
578        DBG("RASTA-ADCDAC IRQ %d: mask\n", irq);
579
580        if ( genirq_check(priv->genirq, irq) )
581                return DRVMGR_EINVAL;
582
583        rtems_interrupt_disable(level);
584
585        /* Disable/mask IRQ */
586        priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
587
588        rtems_interrupt_enable(level);
589
590        return DRVMGR_OK;
591}
592
593int ambapp_rasta_adcdac_int_clear(
594        struct drvmgr_dev *dev,
595        int irq)
596{
597        struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
598
599        if ( genirq_check(priv->genirq, irq) )
600                return DRVMGR_FAIL;
601
602        priv->irq->iclear = (1<<irq);
603
604        return DRVMGR_OK;
605}
606
607int ambapp_rasta_adcdac_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
608{
609        struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
610
611        /* Device name prefix pointer, skip /dev */
612        params->dev_prefix = &priv->prefix[5];
613
614        return 0;
615}
616
617void gr_rasta_adcdac_print_dev(struct drvmgr_dev *dev, int options)
618{
619        struct gr_rasta_adcdac_priv *priv = dev->priv;
620        struct pci_dev_info *devinfo = priv->devinfo;
621        uint32_t bar0, bar1, bar0_size, bar1_size;
622
623        /* Print */
624        printf("--- GR-RASTA-ADCDAC [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
625                PCI_DEV_EXPAND(priv->pcidev));
626
627        bar0 = devinfo->resources[0].address;
628        bar0_size = devinfo->resources[0].size;
629        bar1 = devinfo->resources[1].address;
630        bar1_size = devinfo->resources[1].size;
631
632        printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
633        printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
634        printf(" IRQ REGS:        0x%x\n", (unsigned int)priv->irq);
635        printf(" IRQ:             %d\n", devinfo->irq);
636        printf(" PCI REVISION:    %d\n", devinfo->rev);
637        printf(" FREQ:            %d Hz\n", priv->version->amba_freq_hz);
638        printf(" IMASK:           0x%08x\n", priv->irq->mask[0]);
639        printf(" IPEND:           0x%08x\n", priv->irq->ipend);
640
641        /* Print amba config */
642        if ( options & RASTA_ADCDAC_OPTIONS_AMBA ) {
643                ambapp_print(&priv->abus, 10);
644        }
645#if 0
646        /* Print IRQ handlers and their arguments */
647        if ( options & RASTA_ADCDAC_OPTIONS_IRQ ) {
648                int i;
649                for(i=0; i<16; i++) {
650                        printf(" IRQ[%02d]:         0x%x, arg: 0x%x\n",
651                                i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg);
652                }
653        }
654#endif
655}
656
657void gr_rasta_adcdac_print(int options)
658{
659        struct pci_drv_info *drv = &gr_rasta_adcdac_info;
660        struct drvmgr_dev *dev;
661
662        dev = drv->general.dev;
663        while(dev) {
664                gr_rasta_adcdac_print_dev(dev, options);
665                dev = dev->next_in_drv;
666        }
667}
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