source: rtems/c/src/lib/libbsp/sparc/shared/irq_asm.S @ 8639685

5
Last change on this file since 8639685 was 8639685, checked in by Jacob Hansen <jacob.hansen@…>, on 10/28/16 at 14:05:56

sparc: Adjust assembly to improve compability with LLVM

  • All references of %0 changed to %g0
  • 'call label,0' changed to 'call label'. According to the sparc specification call does not take any registers
  • '.seg "text"' changed to '.section ".text"'
  • the synonym stub is replaced with stb
  • the synonym stuh is replaced with sth
  • Property mode set to 100644
File size: 29.7 KB
Line 
1/*  cpu_asm.s
2 *
3 *  This file contains the basic algorithms for all assembly code used
4 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
5 *  in assembly language.
6 *
7 *  COPYRIGHT (c) 1989-2011.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  Copyright (c) 2014, 2016 embedded brains GmbH
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.org/license/LICENSE.
15 *
16 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
17 *  Research Corporation (OAR) under contract to the European Space
18 *  Agency (ESA).
19 *
20 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
21 *  European Space Agency.
22 */
23
24#include <rtems/asm.h>
25#include <rtems/score/percpu.h>
26#include <bspopts.h>
27
28#if SPARC_HAS_FPU == 1 && defined(SPARC_USE_SAFE_FP_SUPPORT)
29  #define FP_FRAME_OFFSET_FO_F1 (SPARC_MINIMUM_STACK_FRAME_SIZE + 0)
30  #define FP_FRAME_OFFSET_F2_F3 (FP_FRAME_OFFSET_FO_F1 + 8)
31  #define FP_FRAME_OFFSET_F4_F5 (FP_FRAME_OFFSET_F2_F3 + 8)
32  #define FP_FRAME_OFFSET_F6_F7 (FP_FRAME_OFFSET_F4_F5 + 8)
33  #define FP_FRAME_OFFSET_F8_F9 (FP_FRAME_OFFSET_F6_F7 + 8)
34  #define FP_FRAME_OFFSET_F1O_F11 (FP_FRAME_OFFSET_F8_F9 + 8)
35  #define FP_FRAME_OFFSET_F12_F13 (FP_FRAME_OFFSET_F1O_F11 + 8)
36  #define FP_FRAME_OFFSET_F14_F15 (FP_FRAME_OFFSET_F12_F13 + 8)
37  #define FP_FRAME_OFFSET_F16_F17 (FP_FRAME_OFFSET_F14_F15 + 8)
38  #define FP_FRAME_OFFSET_F18_F19 (FP_FRAME_OFFSET_F16_F17 + 8)
39  #define FP_FRAME_OFFSET_F2O_F21 (FP_FRAME_OFFSET_F18_F19 + 8)
40  #define FP_FRAME_OFFSET_F22_F23 (FP_FRAME_OFFSET_F2O_F21 + 8)
41  #define FP_FRAME_OFFSET_F24_F25 (FP_FRAME_OFFSET_F22_F23 + 8)
42  #define FP_FRAME_OFFSET_F26_F27 (FP_FRAME_OFFSET_F24_F25 + 8)
43  #define FP_FRAME_OFFSET_F28_F29 (FP_FRAME_OFFSET_F26_F27 + 8)
44  #define FP_FRAME_OFFSET_F3O_F31 (FP_FRAME_OFFSET_F28_F29 + 8)
45  #define FP_FRAME_OFFSET_FSR (FP_FRAME_OFFSET_F3O_F31 + 8)
46  #define FP_FRAME_SIZE (FP_FRAME_OFFSET_FSR + 8)
47#endif
48
49/*
50 *  void _CPU_Context_switch(
51 *    Context_Control  *run,
52 *    Context_Control  *heir
53 *  )
54 *
55 *  This routine performs a normal non-FP context switch.
56 */
57
58        .align 4
59        PUBLIC(_CPU_Context_switch)
60SYM(_CPU_Context_switch):
61        st      %g5, [%o0 + G5_OFFSET]       ! save the global registers
62        st      %g7, [%o0 + G7_OFFSET]
63
64        std     %l0, [%o0 + L0_OFFSET]       ! save the local registers
65        std     %l2, [%o0 + L2_OFFSET]
66        std     %l4, [%o0 + L4_OFFSET]
67        std     %l6, [%o0 + L6_OFFSET]
68
69        std     %i0, [%o0 + I0_OFFSET]       ! save the input registers
70        std     %i2, [%o0 + I2_OFFSET]
71        std     %i4, [%o0 + I4_OFFSET]
72        std     %i6, [%o0 + I6_FP_OFFSET]
73
74        std     %o6, [%o0 + O6_SP_OFFSET]    ! save the output registers
75
76        ! load the ISR stack nesting prevention flag
77        ld      [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o4
78        ! save it a bit later so we do not waste a couple of cycles
79
80        rd      %psr, %o2
81        st      %o2, [%o0 + PSR_OFFSET]      ! save status register
82
83        ! Now actually save ISR stack nesting prevention flag
84        st       %o4, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET]
85
86        /*
87         *  This is entered from _CPU_Context_restore with:
88         *    o1 = context to restore
89         *    o2 = psr
90         */
91
92        PUBLIC(_CPU_Context_restore_heir)
93SYM(_CPU_Context_restore_heir):
94        /*
95         *  Flush all windows with valid contents except the current one.
96         *  In examining the set register windows, one may logically divide
97         *  the windows into sets (some of which may be empty) based on their
98         *  current status:
99         *
100         *    + current (i.e. in use),
101         *    + used (i.e. a restore would not trap)
102         *    + invalid (i.e. 1 in corresponding bit in WIM)
103         *    + unused
104         *
105         *  Either the used or unused set of windows may be empty.
106         *
107         *  NOTE: We assume only one bit is set in the WIM at a time.
108         *
109         *  Given a CWP of 5 and a WIM of 0x1, the registers are divided
110         *  into sets as follows:
111         *
112         *    + 0   - invalid
113         *    + 1-4 - unused
114         *    + 5   - current
115         *    + 6-7 - used
116         *
117         *  In this case, we only would save the used windows -- 6 and 7.
118         *
119         *   Traps are disabled for the same logical period as in a
120         *     flush all windows trap handler.
121         *
122         *    Register Usage while saving the windows:
123         *      g1 = current PSR
124         *      g2 = current wim
125         *      g3 = CWP
126         *      g4 = wim scratch
127         *      g5 = scratch
128         */
129
130        and     %o2, SPARC_PSR_CWP_MASK, %g3  ! g3 = CWP
131        andn    %o2, SPARC_PSR_ET_MASK, %g1   ! g1 = psr with traps disabled
132        mov     %g1, %psr                     ! **** DISABLE TRAPS ****
133        mov     %wim, %g2                     ! g2 = wim
134        mov     1, %g4
135        sll     %g4, %g3, %g4                 ! g4 = WIM mask for CW invalid
136
137save_frame_loop:
138        sll     %g4, 1, %g5                   ! rotate the "wim" left 1
139        srl     %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4
140        or      %g4, %g5, %g4                 ! g4 = wim if we do one restore
141
142        /*
143         *  If a restore would not underflow, then continue.
144         */
145
146        andcc   %g4, %g2, %g0                 ! Any windows to flush?
147        bnz     done_flushing                 ! No, then continue
148        nop
149
150        restore                               ! back one window
151
152        /*
153         *  Now save the window just as if we overflowed to it.
154         */
155
156        std     %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
157        std     %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
158        std     %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
159        std     %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
160
161        std     %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
162        std     %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
163        std     %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
164        std     %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
165
166        ba      save_frame_loop
167        nop
168
169done_flushing:
170
171        ! Wait three instructions after the write to PSR before using
172        ! non-global registers or instructions affecting the CWP
173        mov     %g1, %psr                     ! restore cwp
174        add     %g3, 1, %g2                   ! calculate desired WIM
175        and     %g2, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g2
176        mov     1, %g4
177        sll     %g4, %g2, %g4                 ! g4 = new WIM
178        mov     %g4, %wim
179
180#if defined(RTEMS_SMP)
181        /*
182         * The executing thread no longer executes on this processor.  Switch
183         * the stack to the temporary interrupt stack of this processor.  Mark
184         * the context of the executing thread as not executing.
185         */
186        add     %g6, PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE, %sp
187        st      %g0, [%o0 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET]
188
189        ! Try to update the is executing indicator of the heir context
190        mov     1, %g1
191
192.Ltry_update_is_executing:
193
194        swap    [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1
195        cmp     %g1, 0
196        bne     .Lcheck_is_executing
197
198        ! The next load is in a delay slot, which is all right
199#endif
200
201        ld      [%o1 + PSR_OFFSET], %g1       ! g1 = heir psr with traps enabled
202        andn    %g1, SPARC_PSR_CWP_MASK, %g1  ! g1 = heir psr w/o cwp
203        or      %g1, %g3, %g1                 ! g1 = heir psr with cwp
204        mov     %g1, %psr                     ! restore status register and
205                                              ! **** ENABLE TRAPS ****
206
207        ld      [%o1 + G5_OFFSET], %g5        ! restore the global registers
208        ld      [%o1 + G7_OFFSET], %g7
209
210        ! Load thread specific ISR dispatch prevention flag
211        ld      [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2
212        ! Store it to memory later to use the cycles
213
214        ldd     [%o1 + L0_OFFSET], %l0        ! restore the local registers
215        ldd     [%o1 + L2_OFFSET], %l2
216        ldd     [%o1 + L4_OFFSET], %l4
217        ldd     [%o1 + L6_OFFSET], %l6
218
219        ! Now restore thread specific ISR dispatch prevention flag
220        st      %o2, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
221
222        ldd     [%o1 + I0_OFFSET], %i0        ! restore the input registers
223        ldd     [%o1 + I2_OFFSET], %i2
224        ldd     [%o1 + I4_OFFSET], %i4
225        ldd     [%o1 + I6_FP_OFFSET], %i6
226
227        ldd     [%o1 + O6_SP_OFFSET], %o6     ! restore the output registers
228
229        jmp     %o7 + 8                       ! return
230        nop                                   ! delay slot
231
232#if defined(RTEMS_SMP)
233.Lcheck_is_executing:
234
235        ! Check the is executing indicator of the heir context
236        ld      [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1
237        cmp     %g1, 0
238        beq     .Ltry_update_is_executing
239         mov    1, %g1
240
241        ! We may have a new heir
242
243        ! Read the executing and heir
244        ld      [%g6 + PER_CPU_OFFSET_EXECUTING], %g2
245        ld      [%g6 + PER_CPU_OFFSET_HEIR], %g4
246
247        ! Update the executing only if necessary to avoid cache line
248        ! monopolization.
249        cmp     %g2, %g4
250        beq     .Ltry_update_is_executing
251         mov    1, %g1
252
253        ! Calculate the heir context pointer
254        sub     %o1, %g2, %g2
255        add     %g2, %g4, %o1
256
257        ! Update the executing
258        st      %g4, [%g6 + PER_CPU_OFFSET_EXECUTING]
259
260        ba      .Ltry_update_is_executing
261         mov    1, %g1
262#endif
263
264/*
265 *  void _CPU_Context_restore(
266 *    Context_Control *new_context
267 *  )
268 *
269 *  This routine is generally used only to perform restart self.
270 *
271 *  NOTE: It is unnecessary to reload some registers.
272 */
273        .align 4
274        PUBLIC(_CPU_Context_restore)
275SYM(_CPU_Context_restore):
276        save    %sp, -SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
277        rd      %psr, %o2
278#if defined(RTEMS_SMP)
279        ! On SPARC the restore path needs also a valid executing context on SMP
280        ! to update the is executing indicator.
281        mov     %i0, %o0
282#endif
283        ba      SYM(_CPU_Context_restore_heir)
284        mov     %i0, %o1                      ! in the delay slot
285
286/*
287 *  void _ISR_Handler()
288 *
289 *  This routine provides the RTEMS interrupt management.
290 *
291 *  We enter this handler from the 4 instructions in the trap table with
292 *  the following registers assumed to be set as shown:
293 *
294 *    l0 = PSR
295 *    l1 = PC
296 *    l2 = nPC
297 *    l3 = trap type
298 *
299 *  NOTE: By an executive defined convention, trap type is between 0 and 255 if
300 *        it is an asynchonous trap and 256 and 511 if it is synchronous.
301 */
302
303        .align 4
304        PUBLIC(_ISR_Handler)
305SYM(_ISR_Handler):
306        /*
307         *  Fix the return address for synchronous traps.
308         */
309
310        andcc   %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
311                                      ! Is this a synchronous trap?
312        be,a    win_ovflow            ! No, then skip the adjustment
313        nop                           ! DELAY
314        mov     %l1, %l6              ! save trapped pc for debug info
315        mov     %l2, %l1              ! do not return to the instruction
316        add     %l2, 4, %l2           ! indicated
317
318win_ovflow:
319        /*
320         *  Save the globals this block uses.
321         *
322         *  These registers are not restored from the locals.  Their contents
323         *  are saved directly from the locals into the ISF below.
324         */
325
326        mov     %g4, %l4                 ! save the globals this block uses
327        mov     %g5, %l5
328
329        /*
330         *  When at a "window overflow" trap, (wim == (1 << cwp)).
331         *  If we get here like that, then process a window overflow.
332         */
333
334        rd      %wim, %g4
335        srl     %g4, %l0, %g5            ! g5 = win >> cwp ; shift count and CWP
336                                         !   are LS 5 bits ; how convenient :)
337        cmp     %g5, 1                   ! Is this an invalid window?
338        bne     dont_do_the_window       ! No, then skip all this stuff
339        ! we are using the delay slot
340
341        /*
342         *  The following is same as a 1 position right rotate of WIM
343         */
344
345        srl     %g4, 1, %g5              ! g5 = WIM >> 1
346        sll     %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4
347                                         ! g4 = WIM << (Number Windows - 1)
348        or      %g4, %g5, %g4            ! g4 = (WIM >> 1) |
349                                         !      (WIM << (Number Windows - 1))
350
351        /*
352         *  At this point:
353         *
354         *    g4 = the new WIM
355         *    g5 is free
356         */
357
358        /*
359         *  Since we are tinkering with the register windows, we need to
360         *  make sure that all the required information is in global registers.
361         */
362
363        save                          ! Save into the window
364        wr      %g4, 0, %wim          ! WIM = new WIM
365        nop                           ! delay slots
366        nop
367        nop
368
369        /*
370         *  Now save the window just as if we overflowed to it.
371         */
372
373        std     %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
374        std     %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
375        std     %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
376        std     %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
377
378        std     %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
379        std     %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
380        std     %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
381        std     %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
382
383        restore
384        nop
385
386dont_do_the_window:
387        /*
388         *  Global registers %g4 and %g5 are saved directly from %l4 and
389         *  %l5 directly into the ISF below.
390         */
391
392        /*
393         *  Save the state of the interrupted task -- especially the global
394         *  registers -- in the Interrupt Stack Frame.  Note that the ISF
395         *  includes a regular minimum stack frame which will be used if
396         *  needed by register window overflow and underflow handlers.
397         *
398         *  REGISTERS SAME AS AT _ISR_Handler
399         */
400
401        sub     %fp, CPU_INTERRUPT_FRAME_SIZE, %sp
402                                               ! make space for ISF
403
404        std     %l0, [%sp + ISF_PSR_OFFSET]    ! save psr, PC
405        st      %l2, [%sp + ISF_NPC_OFFSET]    ! save nPC
406        st      %g1, [%sp + ISF_G1_OFFSET]     ! save g1
407        std     %g2, [%sp + ISF_G2_OFFSET]     ! save g2, g3
408        std     %l4, [%sp + ISF_G4_OFFSET]     ! save g4, g5 -- see above
409        st      %g7, [%sp + ISF_G7_OFFSET]     ! save g7
410
411        std     %i0, [%sp + ISF_I0_OFFSET]     ! save i0, i1
412        std     %i2, [%sp + ISF_I2_OFFSET]     ! save i2, i3
413        std     %i4, [%sp + ISF_I4_OFFSET]     ! save i4, i5
414        std     %i6, [%sp + ISF_I6_FP_OFFSET]  ! save i6/fp, i7
415
416        rd      %y, %g1
417        st      %g1, [%sp + ISF_Y_OFFSET]      ! save y
418        st      %l6, [%sp + ISF_TPC_OFFSET]    ! save real trapped pc
419
420        mov     %sp, %o1                       ! 2nd arg to ISR Handler
421
422        /*
423         *  Increment ISR nest level and Thread dispatch disable level.
424         *
425         *  Register usage for this section:
426         *
427         *    l6 = _Thread_Dispatch_disable_level value
428         *    l7 = _ISR_Nest_level value
429         *
430         *  NOTE: It is assumed that l6 - l7 will be preserved until the ISR
431         *        nest and thread dispatch disable levels are unnested.
432         */
433
434        ld       [%g6 + PER_CPU_ISR_NEST_LEVEL], %l7
435        ld       [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
436
437        add      %l7, 1, %l7
438        st       %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
439
440        add      %l6, 1, %l6
441        st       %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
442
443#if SPARC_HAS_FPU == 1
444        /*
445         * We cannot use an intermediate value for operations with the PSR[EF]
446         * bit since they use a 13-bit sign extension and PSR[EF] is bit 12.
447         */
448        sethi    %hi(SPARC_PSR_EF_MASK), %l5
449#endif
450
451        /*
452         *  If ISR nest level was zero (now 1), then switch stack.
453         */
454
455        mov      %sp, %fp
456        subcc    %l7, 1, %l7             ! outermost interrupt handler?
457        bnz      dont_switch_stacks      ! No, then do not switch stacks
458
459#if defined(RTEMS_PROFILING)
460         sethi   %hi(_SPARC_Counter), %o5
461        ld       [%o5 + %lo(_SPARC_Counter)], %l4
462        call     %l4
463         nop
464        mov      %o0, %o5
465#else
466         nop
467#endif
468
469        ld       [%g6 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
470
471#if SPARC_HAS_FPU == 1
472        /*
473         * Test if the interrupted thread uses the floating point unit
474         * (PSR[EF] == 1).  In case it uses the floating point unit, then store
475         * the floating point status register.  This has the side-effect that
476         * all pending floating point operations complete before the store
477         * completes.  The PSR[EF] bit is restored after the call to the
478         * interrupt handler.  Thus post-switch actions (e.g. signal handlers)
479         * and context switch extensions may still corrupt the floating point
480         * context.
481         */
482        andcc    %l0, %l5, %g0
483        bne,a    dont_switch_stacks
484         st      %fsr, [%g6 + SPARC_PER_CPU_FSR_OFFSET]
485#endif
486
487dont_switch_stacks:
488        /*
489         *  Make sure we have a place on the stack for the window overflow
490         *  trap handler to write into.  At this point it is safe to
491         *  enable traps again.
492         */
493
494        sub      %sp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
495
496        /*
497         *  Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
498         *  set the PIL in the %psr to mask off interrupts with lower priority.
499         *  The original %psr in %l0 is not modified since it will be restored
500         *  when the interrupt handler returns.
501         */
502
503        mov      %l0, %g5
504        and      %l3, 0x0ff, %g4
505        subcc    %g4, 0x11, %g0
506        bl       dont_fix_pil
507        subcc    %g4, 0x1f, %g0
508        bg       dont_fix_pil
509        sll      %g4, 8, %g4
510        and      %g4, SPARC_PSR_PIL_MASK, %g4
511        andn     %l0, SPARC_PSR_PIL_MASK, %g5
512        ba       pil_fixed
513        or       %g4, %g5, %g5
514dont_fix_pil:
515        or       %g5, SPARC_PSR_PIL_MASK, %g5
516pil_fixed:
517
518#if SPARC_HAS_FPU == 1
519        /*
520         * Clear the PSR[EF] bit of the interrupted context to ensure that
521         * interrupt service routines cannot corrupt the floating point context.
522         */
523        andn     %g5, %l5, %g5
524#endif
525
526        wr       %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
527
528        /*
529         *  Vector to user's handler.
530         *
531         *  NOTE: TBR may no longer have vector number in it since
532         *        we just enabled traps.  It is definitely in l3.
533         */
534
535        sethi    %hi(SYM(_ISR_Vector_table)), %g4
536        or       %g4, %lo(SYM(_ISR_Vector_table)), %g4
537        and      %l3, 0xFF, %g5         ! remove synchronous trap indicator
538        sll      %g5, 2, %g5            ! g5 = offset into table
539        ld       [%g4 + %g5], %g4       ! g4 = _ISR_Vector_table[ vector ]
540
541
542                                        ! o1 = 2nd arg = address of the ISF
543                                        !   WAS LOADED WHEN ISF WAS SAVED!!!
544        mov      %l3, %o0               ! o0 = 1st arg = vector number
545        call     %g4
546#if defined(RTEMS_PROFILING)
547         mov     %o5, %l3               ! save interrupt entry instant
548#else
549         nop                            ! delay slot
550#endif
551
552#if SPARC_HAS_FPU == 1
553        mov      %l0, %g1               ! PSR[EF] value of interrupted context
554        ta       SPARC_SWTRAP_IRQDIS_FP ! **** DISABLE INTERRUPTS ****
555#else
556        ta       SPARC_SWTRAP_IRQDIS    ! **** DISABLE INTERRUPTS ****
557#endif
558
559#if defined(RTEMS_PROFILING)
560        cmp      %l7, 0
561        bne      profiling_not_outer_most_exit
562         nop
563        call     %l4                    ! Call _SPARC_Counter.counter_read
564         mov     %g1, %l4               ! Save previous interrupt status
565        mov      %o0, %o2               ! o2 = 3rd arg = interrupt exit instant
566        mov      %l3, %o1               ! o1 = 2nd arg = interrupt entry instant
567        call     SYM(_Profiling_Outer_most_interrupt_entry_and_exit)
568         mov     %g6, %o0               ! o0 = 1st arg = per-CPU control
569profiling_not_outer_most_exit:
570#endif
571
572        /*
573         *  Decrement ISR nest level and Thread dispatch disable level.
574         *
575         *  Register usage for this section:
576         *
577         *    o2 = g6->dispatch_necessary value
578         *    o3 = g6->isr_dispatch_disable value
579         *    l6 = g6->thread_dispatch_disable_level value
580         *    l7 = g6->isr_nest_level value
581         */
582
583        ldub     [%g6 + PER_CPU_DISPATCH_NEEDED], %o2
584        ld       [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o3
585        st       %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
586        sub      %l6, 1, %l6
587        st       %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
588
589        /*
590         * Thread dispatching is necessary and allowed if and only if
591         *   g6->dispatch_necessary == 1 and
592         *   g6->isr_dispatch_disable == 0 and
593         *   g6->thread_dispatch_disable_level == 0.
594         *
595         * Otherwise, continue with the simple return.
596         */
597        xor      %o2, 1, %o2
598        or       %o2, %l6, %o2
599        orcc     %o2, %o3, %o2
600        bnz      simple_return
601
602        /*
603         * Switch back on the interrupted tasks stack and add enough room to
604         * invoke the dispatcher.  Doing this in the delay slot causes no harm,
605         * since the stack pointer (%sp) is not used in the simple return path.
606         */
607         sub     %fp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
608
609isr_dispatch:
610
611        /* Set ISR dispatch disable and thread dispatch disable level to one */
612        mov      1, %l6
613        st       %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
614        st       %l6, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
615
616        /* Call _Thread_Do_dispatch(), this function will enable interrupts */
617
618        mov      0, %o1                 ! ISR level for _Thread_Do_dispatch()
619
620#if SPARC_HAS_FPU == 1 && defined(SPARC_USE_SAFE_FP_SUPPORT)
621        /* Test if we interrupted a floating point thread (PSR[EF] == 1) */
622        andcc   %l0, %l5, %g0
623        be      non_fp_thread_dispatch
624         nop
625
626        /*
627         * Yes, this is a floating point thread, then save the floating point
628         * context to a new stack frame.  Then do the thread dispatch.
629         * Post-switch actions (e.g. signal handlers) and context switch
630         * extensions may safely use the floating point unit.
631         */
632        sub     %sp, FP_FRAME_SIZE, %sp
633        std     %f0, [%sp + FP_FRAME_OFFSET_FO_F1]
634        std     %f2, [%sp + FP_FRAME_OFFSET_F2_F3]
635        std     %f4, [%sp + FP_FRAME_OFFSET_F4_F5]
636        std     %f6, [%sp + FP_FRAME_OFFSET_F6_F7]
637        std     %f8, [%sp + FP_FRAME_OFFSET_F8_F9]
638        std     %f10, [%sp + FP_FRAME_OFFSET_F1O_F11]
639        std     %f12, [%sp + FP_FRAME_OFFSET_F12_F13]
640        std     %f14, [%sp + FP_FRAME_OFFSET_F14_F15]
641        std     %f16, [%sp + FP_FRAME_OFFSET_F16_F17]
642        std     %f18, [%sp + FP_FRAME_OFFSET_F18_F19]
643        std     %f20, [%sp + FP_FRAME_OFFSET_F2O_F21]
644        std     %f22, [%sp + FP_FRAME_OFFSET_F22_F23]
645        std     %f24, [%sp + FP_FRAME_OFFSET_F24_F25]
646        std     %f26, [%sp + FP_FRAME_OFFSET_F26_F27]
647        std     %f28, [%sp + FP_FRAME_OFFSET_F28_F29]
648        std     %f30, [%sp + FP_FRAME_OFFSET_F3O_F31]
649        st      %fsr, [%sp + FP_FRAME_OFFSET_FSR]
650        call    SYM(_Thread_Do_dispatch)
651         mov    %g6, %o0
652
653        /*
654         * Restore the floating point context from stack frame and release the
655         * stack frame.
656         */
657        ldd     [%sp + FP_FRAME_OFFSET_FO_F1], %f0
658        ldd     [%sp + FP_FRAME_OFFSET_F2_F3], %f2
659        ldd     [%sp + FP_FRAME_OFFSET_F4_F5], %f4
660        ldd     [%sp + FP_FRAME_OFFSET_F6_F7], %f6
661        ldd     [%sp + FP_FRAME_OFFSET_F8_F9], %f8
662        ldd     [%sp + FP_FRAME_OFFSET_F1O_F11], %f10
663        ldd     [%sp + FP_FRAME_OFFSET_F12_F13], %f12
664        ldd     [%sp + FP_FRAME_OFFSET_F14_F15], %f14
665        ldd     [%sp + FP_FRAME_OFFSET_F16_F17], %f16
666        ldd     [%sp + FP_FRAME_OFFSET_F18_F19], %f18
667        ldd     [%sp + FP_FRAME_OFFSET_F2O_F21], %f20
668        ldd     [%sp + FP_FRAME_OFFSET_F22_F23], %f22
669        ldd     [%sp + FP_FRAME_OFFSET_F24_F25], %f24
670        ldd     [%sp + FP_FRAME_OFFSET_F26_F27], %f26
671        ldd     [%sp + FP_FRAME_OFFSET_F28_F29], %f28
672        ldd     [%sp + FP_FRAME_OFFSET_F3O_F31], %f30
673        ld      [%sp + FP_FRAME_OFFSET_FSR], %fsr
674        ba      thread_dispatch_done
675         add    %sp, FP_FRAME_SIZE, %sp
676
677non_fp_thread_dispatch:
678#endif
679
680        call    SYM(_Thread_Do_dispatch)
681         mov    %g6, %o0
682
683#if SPARC_HAS_FPU == 1 && defined(SPARC_USE_SAFE_FP_SUPPORT)
684thread_dispatch_done:
685#endif
686
687        ta       SPARC_SWTRAP_IRQDIS ! **** DISABLE INTERRUPTS ****
688
689        /*
690         *  While we had ISR dispatching disabled in this thread,
691         *  did we miss anything?  If so, then we need to do another
692         *  _Thread_Do_dispatch() before leaving this ISR dispatch context.
693         */
694        ldub    [%g6 + PER_CPU_DISPATCH_NEEDED], %l7
695
696        orcc    %l7, %g0, %g0        ! Is a thread dispatch necessary?
697        bne     isr_dispatch         ! Yes, then invoke the dispatcher again.
698         mov    0, %o1               ! ISR level for _Thread_Do_dispatch()
699
700        /*
701         * No, then set the ISR dispatch disable flag to zero and continue with
702         * the simple return.
703         */
704        st       %g0, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
705
706        /*
707         *  The CWP in place at this point may be different from
708         *  that which was in effect at the beginning of the ISR if we
709         *  have been context switched between the beginning of this invocation
710         *  of _ISR_Handler and this point.  Thus the CWP and WIM should
711         *  not be changed back to their values at ISR entry time.  Any
712         *  changes to the PSR must preserve the CWP.
713         */
714
715simple_return:
716        ld      [%fp + ISF_Y_OFFSET], %l5      ! restore y
717        wr      %l5, 0, %y
718
719        ldd     [%fp + ISF_PSR_OFFSET], %l0    ! restore psr, PC
720        ld      [%fp + ISF_NPC_OFFSET], %l2    ! restore nPC
721        rd      %psr, %l3
722        and     %l3, SPARC_PSR_CWP_MASK, %l3   ! want "current" CWP
723        andn    %l0, SPARC_PSR_CWP_MASK, %l0   ! want rest from task
724        or      %l3, %l0, %l0                  ! install it later...
725        andn    %l0, SPARC_PSR_ET_MASK, %l0
726
727        /*
728         *  Restore tasks global and out registers
729         */
730
731        mov    %fp, %g1
732
733                                              ! g1 is restored later
734        ldd     [%fp + ISF_G2_OFFSET], %g2    ! restore g2, g3
735        ldd     [%fp + ISF_G4_OFFSET], %g4    ! restore g4, g5
736        ld      [%fp + ISF_G7_OFFSET], %g7    ! restore g7
737
738        ldd     [%fp + ISF_I0_OFFSET], %i0    ! restore i0, i1
739        ldd     [%fp + ISF_I2_OFFSET], %i2    ! restore i2, i3
740        ldd     [%fp + ISF_I4_OFFSET], %i4    ! restore i4, i5
741        ldd     [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7
742
743        /*
744         *  Registers:
745         *
746         *   ALL global registers EXCEPT G1 and the input registers have
747         *   already been restored and thuse off limits.
748         *
749         *   The following is the contents of the local registers:
750         *
751         *     l0 = original psr
752         *     l1 = return address (i.e. PC)
753         *     l2 = nPC
754         *     l3 = CWP
755         */
756
757        /*
758         *  if (CWP + 1) is an invalid window then we need to reload it.
759         *
760         *  WARNING: Traps should now be disabled
761         */
762
763        mov     %l0, %psr                  !  **** DISABLE TRAPS ****
764        nop
765        nop
766        nop
767        rd      %wim, %l4
768        add     %l0, 1, %l6                ! l6 = cwp + 1
769        and     %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it
770        srl     %l4, %l6, %l5              ! l5 = win >> cwp + 1 ; shift count
771                                           !  and CWP are conveniently LS 5 bits
772        cmp     %l5, 1                     ! Is tasks window invalid?
773        bne     good_task_window
774
775        /*
776         *  The following code is the same as a 1 position left rotate of WIM.
777         */
778
779        sll     %l4, 1, %l5                ! l5 = WIM << 1
780        srl     %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4
781                                           ! l4 = WIM >> (Number Windows - 1)
782        or      %l4, %l5, %l4              ! l4 = (WIM << 1) |
783                                           !      (WIM >> (Number Windows - 1))
784
785        /*
786         *  Now restore the window just as if we underflowed to it.
787         */
788
789        wr      %l4, 0, %wim               ! WIM = new WIM
790        nop                                ! must delay after writing WIM
791        nop
792        nop
793        restore                            ! now into the tasks window
794
795        ldd     [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0
796        ldd     [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2
797        ldd     [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4
798        ldd     [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6
799        ldd     [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0
800        ldd     [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2
801        ldd     [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4
802        ldd     [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
803                                           ! reload of sp clobbers ISF
804        save                               ! Back to ISR dispatch window
805
806good_task_window:
807
808        mov     %l0, %psr                  !  **** DISABLE TRAPS ****
809        nop; nop; nop
810                                           !  and restore condition codes.
811        ld      [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
812        jmp     %l1                        ! transfer control and
813        rett    %l2                        ! go back to tasks window
814
815/* end of file */
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