source: rtems/c/src/lib/libbsp/sparc/shared/irq_asm.S @ 7c0bd74

4.11
Last change on this file since 7c0bd74 was 7c0bd74, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 22, 2014 at 8:15:39 AM

sparc: Add _CPU_Get_current_per_CPU_control()

Use register g6 for the per-CPU control of the current processor. The
register g6 is reserved for the operating system by the SPARC ABI. On
Linux register g6 is used for a similar purpose with the same method
since 1996.

The register g6 must be initialized during system startup and then must
remain unchanged.

Since the per-CPU control is used in all critical sections of the
operating system, this is a performance optimization for the operating
system core procedures. An additional benefit is that the low-level
context switch and interrupt processing code is now identical on non-SMP
and SMP configurations.

  • Property mode set to 100644
File size: 23.4 KB
Line 
1/*  cpu_asm.s
2 *
3 *  This file contains the basic algorithms for all assembly code used
4 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
5 *  in assembly language.
6 *
7 *  COPYRIGHT (c) 1989-2011.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.org/license/LICENSE.
13 *
14 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
15 *  Research Corporation (OAR) under contract to the European Space
16 *  Agency (ESA).
17 *
18 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
19 *  European Space Agency.
20 */
21
22#include <rtems/asm.h>
23#include <rtems/score/percpu.h>
24#include <bspopts.h>
25
26/*
27 *  void _CPU_Context_switch(
28 *    Context_Control  *run,
29 *    Context_Control  *heir
30 *  )
31 *
32 *  This routine performs a normal non-FP context switch.
33 */
34
35        .align 4
36        PUBLIC(_CPU_Context_switch)
37SYM(_CPU_Context_switch):
38        st      %g5, [%o0 + G5_OFFSET]       ! save the global registers
39        st      %g7, [%o0 + G7_OFFSET]
40
41        std     %l0, [%o0 + L0_OFFSET]       ! save the local registers
42        std     %l2, [%o0 + L2_OFFSET]
43        std     %l4, [%o0 + L4_OFFSET]
44        std     %l6, [%o0 + L6_OFFSET]
45
46        std     %i0, [%o0 + I0_OFFSET]       ! save the input registers
47        std     %i2, [%o0 + I2_OFFSET]
48        std     %i4, [%o0 + I4_OFFSET]
49        std     %i6, [%o0 + I6_FP_OFFSET]
50
51        std     %o6, [%o0 + O6_SP_OFFSET]    ! save the output registers
52
53        ! load the ISR stack nesting prevention flag
54        ld      [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE], %o4
55        ! save it a bit later so we do not waste a couple of cycles
56
57        rd      %psr, %o2
58        st      %o2, [%o0 + PSR_OFFSET]      ! save status register
59
60        ! Now actually save ISR stack nesting prevention flag
61        st       %o4, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET]
62
63        /*
64         *  This is entered from _CPU_Context_restore with:
65         *    o1 = context to restore
66         *    o2 = psr
67         */
68
69        PUBLIC(_CPU_Context_restore_heir)
70SYM(_CPU_Context_restore_heir):
71        /*
72         *  Flush all windows with valid contents except the current one.
73         *  In examining the set register windows, one may logically divide
74         *  the windows into sets (some of which may be empty) based on their
75         *  current status:
76         *
77         *    + current (i.e. in use),
78         *    + used (i.e. a restore would not trap)
79         *    + invalid (i.e. 1 in corresponding bit in WIM)
80         *    + unused
81         *
82         *  Either the used or unused set of windows may be empty.
83         *
84         *  NOTE: We assume only one bit is set in the WIM at a time.
85         *
86         *  Given a CWP of 5 and a WIM of 0x1, the registers are divided
87         *  into sets as follows:
88         *
89         *    + 0   - invalid
90         *    + 1-4 - unused
91         *    + 5   - current
92         *    + 6-7 - used
93         *
94         *  In this case, we only would save the used windows -- 6 and 7.
95         *
96         *   Traps are disabled for the same logical period as in a
97         *     flush all windows trap handler.
98         *
99         *    Register Usage while saving the windows:
100         *      g1 = current PSR
101         *      g2 = current wim
102         *      g3 = CWP
103         *      g4 = wim scratch
104         *      g5 = scratch
105         */
106
107        ld      [%o1 + PSR_OFFSET], %g1       ! g1 = saved psr
108
109        and     %o2, SPARC_PSR_CWP_MASK, %g3  ! g3 = CWP
110                                              ! g1 = psr w/o cwp
111        andn    %g1, SPARC_PSR_ET_MASK | SPARC_PSR_CWP_MASK, %g1
112        or      %g1, %g3, %g1                 ! g1 = heirs psr
113        mov     %g1, %psr                     ! restore status register and
114                                              ! **** DISABLE TRAPS ****
115        mov     %wim, %g2                     ! g2 = wim
116        mov     1, %g4
117        sll     %g4, %g3, %g4                 ! g4 = WIM mask for CW invalid
118
119save_frame_loop:
120        sll     %g4, 1, %g5                   ! rotate the "wim" left 1
121        srl     %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4
122        or      %g4, %g5, %g4                 ! g4 = wim if we do one restore
123
124        /*
125         *  If a restore would not underflow, then continue.
126         */
127
128        andcc   %g4, %g2, %g0                 ! Any windows to flush?
129        bnz     done_flushing                 ! No, then continue
130        nop
131
132        restore                               ! back one window
133
134        /*
135         *  Now save the window just as if we overflowed to it.
136         */
137
138        std     %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
139        std     %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
140        std     %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
141        std     %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
142
143        std     %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
144        std     %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
145        std     %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
146        std     %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
147
148        ba      save_frame_loop
149        nop
150
151done_flushing:
152
153        add     %g3, 1, %g3                   ! calculate desired WIM
154        and     %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3
155        mov     1, %g4
156        sll     %g4, %g3, %g4                 ! g4 = new WIM
157        mov     %g4, %wim
158
159        or      %g1, SPARC_PSR_ET_MASK, %g1
160        mov     %g1, %psr                     ! **** ENABLE TRAPS ****
161                                              !   and restore CWP
162        nop
163        nop
164        nop
165
166        ld      [%o1 + G5_OFFSET], %g5        ! restore the global registers
167        ld      [%o1 + G7_OFFSET], %g7
168
169        ! Load thread specific ISR dispatch prevention flag
170        ld      [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2
171        ! Store it to memory later to use the cycles
172
173        ldd     [%o1 + L0_OFFSET], %l0        ! restore the local registers
174        ldd     [%o1 + L2_OFFSET], %l2
175        ldd     [%o1 + L4_OFFSET], %l4
176        ldd     [%o1 + L6_OFFSET], %l6
177
178        ! Now restore thread specific ISR dispatch prevention flag
179        st      %o2, [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
180
181        ldd     [%o1 + I0_OFFSET], %i0        ! restore the input registers
182        ldd     [%o1 + I2_OFFSET], %i2
183        ldd     [%o1 + I4_OFFSET], %i4
184        ldd     [%o1 + I6_FP_OFFSET], %i6
185
186        ldd     [%o1 + O6_SP_OFFSET], %o6     ! restore the output registers
187
188        jmp     %o7 + 8                       ! return
189        nop                                   ! delay slot
190
191/*
192 *  void _CPU_Context_restore(
193 *    Context_Control *new_context
194 *  )
195 *
196 *  This routine is generally used only to perform restart self.
197 *
198 *  NOTE: It is unnecessary to reload some registers.
199 */
200        .align 4
201        PUBLIC(_CPU_Context_restore)
202SYM(_CPU_Context_restore):
203        save    %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
204        rd      %psr, %o2
205        ba      SYM(_CPU_Context_restore_heir)
206        mov     %i0, %o1                      ! in the delay slot
207
208/*
209 *  void _ISR_Handler()
210 *
211 *  This routine provides the RTEMS interrupt management.
212 *
213 *  We enter this handler from the 4 instructions in the trap table with
214 *  the following registers assumed to be set as shown:
215 *
216 *    l0 = PSR
217 *    l1 = PC
218 *    l2 = nPC
219 *    l3 = trap type
220 *
221 *  NOTE: By an executive defined convention, trap type is between 0 and 255 if
222 *        it is an asynchonous trap and 256 and 511 if it is synchronous.
223 */
224
225        .align 4
226        PUBLIC(_ISR_Handler)
227SYM(_ISR_Handler):
228        /*
229         *  Fix the return address for synchronous traps.
230         */
231
232        andcc   %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
233                                      ! Is this a synchronous trap?
234        be,a    win_ovflow            ! No, then skip the adjustment
235        nop                           ! DELAY
236        mov     %l1, %l6              ! save trapped pc for debug info
237        mov     %l2, %l1              ! do not return to the instruction
238        add     %l2, 4, %l2           ! indicated
239
240win_ovflow:
241        /*
242         *  Save the globals this block uses.
243         *
244         *  These registers are not restored from the locals.  Their contents
245         *  are saved directly from the locals into the ISF below.
246         */
247
248        mov     %g4, %l4                 ! save the globals this block uses
249        mov     %g5, %l5
250
251        /*
252         *  When at a "window overflow" trap, (wim == (1 << cwp)).
253         *  If we get here like that, then process a window overflow.
254         */
255
256        rd      %wim, %g4
257        srl     %g4, %l0, %g5            ! g5 = win >> cwp ; shift count and CWP
258                                         !   are LS 5 bits ; how convenient :)
259        cmp     %g5, 1                   ! Is this an invalid window?
260        bne     dont_do_the_window       ! No, then skip all this stuff
261        ! we are using the delay slot
262
263        /*
264         *  The following is same as a 1 position right rotate of WIM
265         */
266
267        srl     %g4, 1, %g5              ! g5 = WIM >> 1
268        sll     %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4
269                                         ! g4 = WIM << (Number Windows - 1)
270        or      %g4, %g5, %g4            ! g4 = (WIM >> 1) |
271                                         !      (WIM << (Number Windows - 1))
272
273        /*
274         *  At this point:
275         *
276         *    g4 = the new WIM
277         *    g5 is free
278         */
279
280        /*
281         *  Since we are tinkering with the register windows, we need to
282         *  make sure that all the required information is in global registers.
283         */
284
285        save                          ! Save into the window
286        wr      %g4, 0, %wim          ! WIM = new WIM
287        nop                           ! delay slots
288        nop
289        nop
290
291        /*
292         *  Now save the window just as if we overflowed to it.
293         */
294
295        std     %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
296        std     %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
297        std     %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
298        std     %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
299
300        std     %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
301        std     %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
302        std     %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
303        std     %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
304
305        restore
306        nop
307
308dont_do_the_window:
309        /*
310         *  Global registers %g4 and %g5 are saved directly from %l4 and
311         *  %l5 directly into the ISF below.
312         */
313
314save_isf:
315
316        /*
317         *  Save the state of the interrupted task -- especially the global
318         *  registers -- in the Interrupt Stack Frame.  Note that the ISF
319         *  includes a regular minimum stack frame which will be used if
320         *  needed by register window overflow and underflow handlers.
321         *
322         *  REGISTERS SAME AS AT _ISR_Handler
323         */
324
325        sub     %fp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
326                                               ! make space for ISF
327
328        std     %l0, [%sp + ISF_PSR_OFFSET]    ! save psr, PC
329        st      %l2, [%sp + ISF_NPC_OFFSET]    ! save nPC
330        st      %g1, [%sp + ISF_G1_OFFSET]     ! save g1
331        std     %g2, [%sp + ISF_G2_OFFSET]     ! save g2, g3
332        std     %l4, [%sp + ISF_G4_OFFSET]     ! save g4, g5 -- see above
333        st      %g7, [%sp + ISF_G7_OFFSET]     ! save g7
334
335        std     %i0, [%sp + ISF_I0_OFFSET]     ! save i0, i1
336        std     %i2, [%sp + ISF_I2_OFFSET]     ! save i2, i3
337        std     %i4, [%sp + ISF_I4_OFFSET]     ! save i4, i5
338        std     %i6, [%sp + ISF_I6_FP_OFFSET]  ! save i6/fp, i7
339
340        rd      %y, %g1
341        st      %g1, [%sp + ISF_Y_OFFSET]      ! save y
342        st      %l6, [%sp + ISF_TPC_OFFSET]    ! save real trapped pc
343
344        mov     %sp, %o1                       ! 2nd arg to ISR Handler
345
346        /*
347         *  Increment ISR nest level and Thread dispatch disable level.
348         *
349         *  Register usage for this section:
350         *
351         *    l6 = _Thread_Dispatch_disable_level value
352         *    l7 = _ISR_Nest_level value
353         *
354         *  NOTE: It is assumed that l6 - l7 will be preserved until the ISR
355         *        nest and thread dispatch disable levels are unnested.
356         */
357
358        ld       [%g6 + PER_CPU_ISR_NEST_LEVEL], %l7
359        ld       [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
360
361        add      %l7, 1, %l7
362        st       %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
363
364        add      %l6, 1, %l6
365        st       %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
366
367        /*
368         *  If ISR nest level was zero (now 1), then switch stack.
369         */
370
371        mov      %sp, %fp
372        subcc    %l7, 1, %l7             ! outermost interrupt handler?
373        bnz      dont_switch_stacks      ! No, then do not switch stacks
374
375#if defined( RTEMS_PROFILING )
376         sethi   %hi(SYM(_SPARC_Counter)), %o5
377        ld       [%o5 + %lo(SYM(_SPARC_Counter))], %l4
378        ld       [%l4], %o5
379#else
380         nop
381#endif
382
383        ld       [%g6 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
384
385dont_switch_stacks:
386        /*
387         *  Make sure we have a place on the stack for the window overflow
388         *  trap handler to write into.  At this point it is safe to
389         *  enable traps again.
390         */
391
392        sub      %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
393
394        /*
395         *  Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
396         *  set the PIL in the %psr to mask off interrupts with lower priority.
397         *  The original %psr in %l0 is not modified since it will be restored
398         *  when the interrupt handler returns.
399         */
400
401        mov      %l0, %g5
402        and      %l3, 0x0ff, %g4
403        subcc    %g4, 0x11, %g0
404        bl       dont_fix_pil
405        subcc    %g4, 0x1f, %g0
406        bg       dont_fix_pil
407        sll      %g4, 8, %g4
408        and      %g4, SPARC_PSR_PIL_MASK, %g4
409        andn     %l0, SPARC_PSR_PIL_MASK, %g5
410        ba       pil_fixed
411        or       %g4, %g5, %g5
412dont_fix_pil:
413        or       %g5, SPARC_PSR_PIL_MASK, %g5
414pil_fixed:
415        wr       %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
416dont_fix_pil2:
417
418        /*
419         *  Vector to user's handler.
420         *
421         *  NOTE: TBR may no longer have vector number in it since
422         *        we just enabled traps.  It is definitely in l3.
423         */
424
425        sethi    %hi(SYM(_ISR_Vector_table)), %g4
426        ld       [%g4+%lo(SYM(_ISR_Vector_table))], %g4
427        and      %l3, 0xFF, %g5         ! remove synchronous trap indicator
428        sll      %g5, 2, %g5            ! g5 = offset into table
429        ld       [%g4 + %g5], %g4       ! g4 = _ISR_Vector_table[ vector ]
430
431
432                                        ! o1 = 2nd arg = address of the ISF
433                                        !   WAS LOADED WHEN ISF WAS SAVED!!!
434        mov      %l3, %o0               ! o0 = 1st arg = vector number
435        call     %g4, 0
436#if defined( RTEMS_PROFILING )
437         mov     %o5, %l3               ! save interrupt entry instant
438        cmp      %l7, 0
439        bne      profiling_not_outer_most_exit
440         nop
441        call     SYM(sparc_disable_interrupts), 0
442         nop
443        ld       [%l4], %o2             ! o2 = 3rd arg = interrupt exit instant
444        mov      %l3, %o1               ! o1 = 2nd arg = interrupt entry instant
445        call     SYM(_Profiling_Outer_most_interrupt_entry_and_exit), 0
446         mov     %g6, %o0               ! o0 = 1st arg = per-CPU control
447profiling_not_outer_most_exit:
448#else
449         nop                            ! delay slot
450#endif
451
452        /*
453         *  Redisable traps so we can finish up the interrupt processing.
454         *  This is a VERY conservative place to do this.
455         *
456         *  NOTE: %l0 has the PSR which was in place when we took the trap.
457         */
458
459        mov      %l0, %psr             ! **** DISABLE TRAPS ****
460        nop; nop; nop
461
462        /*
463         *  Decrement ISR nest level and Thread dispatch disable level.
464         *
465         *  Register usage for this section:
466         *
467         *    l6 = _Thread_Dispatch_disable_level value
468         *    l7 = _ISR_Nest_level value
469         */
470
471        st       %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
472
473        sub      %l6, 1, %l6
474        st       %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
475
476        /*
477         *  If dispatching is disabled (includes nested interrupt case),
478         *  then do a "simple" exit.
479         */
480
481        orcc     %l6, %g0, %g0   ! Is dispatching disabled?
482        bnz      simple_return   ! Yes, then do a "simple" exit
483        nop
484
485        ! Are we dispatching from a previous ISR in the interrupted thread?
486        ld       [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE], %l7
487        orcc     %l7, %g0, %g0   ! Is this thread already doing an ISR?
488        bnz      simple_return   ! Yes, then do a "simple" exit
489        nop
490
491
492        /*
493         *  If a context switch is necessary, then do fudge stack to
494         *  return to the interrupt dispatcher.
495         */
496
497        ldub     [%g6 + PER_CPU_DISPATCH_NEEDED], %l6
498
499        orcc     %l6, %g0, %g0   ! Is thread switch necessary?
500        bz       simple_return   ! no, then do a simple return
501        nop
502
503        /*
504         *  Invoke interrupt dispatcher.
505         */
506
507        ! Set ISR dispatch nesting prevention flag
508        mov      1,%l6
509        st       %l6, [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
510
511        /*
512         *  The following subtract should get us back on the interrupted
513         *  tasks stack and add enough room to invoke the dispatcher.
514         *  When we enable traps, we are mostly back in the context
515         *  of the task and subsequent interrupts can operate normally.
516         */
517
518        sub      %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
519
520        or      %l0, SPARC_PSR_ET_MASK, %l7    ! l7 = PSR with ET=1
521        mov     %l7, %psr                      !  **** ENABLE TRAPS ****
522        nop
523        nop
524        nop
525isr_dispatch:
526        call    SYM(_Thread_Dispatch), 0
527        nop
528
529        /*
530         *  We invoked _Thread_Dispatch in a state similar to the interrupted
531         *  task.  In order to safely be able to tinker with the register
532         *  windows and get the task back to its pre-interrupt state,
533         *  we need to disable interrupts disabled so we can safely tinker
534         *  with the register windowing.  In particular, the CWP in the PSR
535         *  is fragile during this period. (See PR578.)
536         */
537        mov     2,%g1                           ! syscall (disable interrupts)
538        ta      0                               ! syscall (disable interrupts)
539
540        /*
541         *  While we had ISR dispatching disabled in this thread,
542         *  did we miss anything.  If so, then we need to do another
543         *  _Thread_Dispatch before leaving this ISR Dispatch context.
544         */
545
546        ldub     [%g6 + PER_CPU_DISPATCH_NEEDED], %l7
547
548        orcc     %l7, %g0, %g0    ! Is thread switch necesary?
549        bz       allow_nest_again ! No, then clear out and return
550        nop
551
552        ! Yes, then invoke the dispatcher
553dispatchAgain:
554        mov     3,%g1                           ! syscall (enable interrupts)
555        ta      0                               ! syscall (enable interrupts)
556        ba      isr_dispatch
557        nop
558
559allow_nest_again:
560
561        ! Zero out ISR stack nesting prevention flag
562        st       %g0, [%g6 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
563
564        /*
565         *  The CWP in place at this point may be different from
566         *  that which was in effect at the beginning of the ISR if we
567         *  have been context switched between the beginning of this invocation
568         *  of _ISR_Handler and this point.  Thus the CWP and WIM should
569         *  not be changed back to their values at ISR entry time.  Any
570         *  changes to the PSR must preserve the CWP.
571         */
572
573simple_return:
574        ld      [%fp + ISF_Y_OFFSET], %l5      ! restore y
575        wr      %l5, 0, %y
576
577        ldd     [%fp + ISF_PSR_OFFSET], %l0    ! restore psr, PC
578        ld      [%fp + ISF_NPC_OFFSET], %l2    ! restore nPC
579        rd      %psr, %l3
580        and     %l3, SPARC_PSR_CWP_MASK, %l3   ! want "current" CWP
581        andn    %l0, SPARC_PSR_CWP_MASK, %l0   ! want rest from task
582        or      %l3, %l0, %l0                  ! install it later...
583        andn    %l0, SPARC_PSR_ET_MASK, %l0
584
585        /*
586         *  Restore tasks global and out registers
587         */
588
589        mov    %fp, %g1
590
591                                              ! g1 is restored later
592        ldd     [%fp + ISF_G2_OFFSET], %g2    ! restore g2, g3
593        ldd     [%fp + ISF_G4_OFFSET], %g4    ! restore g4, g5
594        ld      [%fp + ISF_G7_OFFSET], %g7    ! restore g7
595
596        ldd     [%fp + ISF_I0_OFFSET], %i0    ! restore i0, i1
597        ldd     [%fp + ISF_I2_OFFSET], %i2    ! restore i2, i3
598        ldd     [%fp + ISF_I4_OFFSET], %i4    ! restore i4, i5
599        ldd     [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7
600
601        /*
602         *  Registers:
603         *
604         *   ALL global registers EXCEPT G1 and the input registers have
605         *   already been restored and thuse off limits.
606         *
607         *   The following is the contents of the local registers:
608         *
609         *     l0 = original psr
610         *     l1 = return address (i.e. PC)
611         *     l2 = nPC
612         *     l3 = CWP
613         */
614
615        /*
616         *  if (CWP + 1) is an invalid window then we need to reload it.
617         *
618         *  WARNING: Traps should now be disabled
619         */
620
621        mov     %l0, %psr                  !  **** DISABLE TRAPS ****
622        nop
623        nop
624        nop
625        rd      %wim, %l4
626        add     %l0, 1, %l6                ! l6 = cwp + 1
627        and     %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it
628        srl     %l4, %l6, %l5              ! l5 = win >> cwp + 1 ; shift count
629                                           !  and CWP are conveniently LS 5 bits
630        cmp     %l5, 1                     ! Is tasks window invalid?
631        bne     good_task_window
632
633        /*
634         *  The following code is the same as a 1 position left rotate of WIM.
635         */
636
637        sll     %l4, 1, %l5                ! l5 = WIM << 1
638        srl     %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4
639                                           ! l4 = WIM >> (Number Windows - 1)
640        or      %l4, %l5, %l4              ! l4 = (WIM << 1) |
641                                           !      (WIM >> (Number Windows - 1))
642
643        /*
644         *  Now restore the window just as if we underflowed to it.
645         */
646
647        wr      %l4, 0, %wim               ! WIM = new WIM
648        nop                                ! must delay after writing WIM
649        nop
650        nop
651        restore                            ! now into the tasks window
652
653        ldd     [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0
654        ldd     [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2
655        ldd     [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4
656        ldd     [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6
657        ldd     [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0
658        ldd     [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2
659        ldd     [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4
660        ldd     [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
661                                           ! reload of sp clobbers ISF
662        save                               ! Back to ISR dispatch window
663
664good_task_window:
665
666        mov     %l0, %psr                  !  **** DISABLE TRAPS ****
667        nop; nop; nop
668                                           !  and restore condition codes.
669        ld      [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
670        jmp     %l1                        ! transfer control and
671        rett    %l2                        ! go back to tasks window
672
673/* end of file */
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