Context Navigation

irq_asm.S @ 5ff6a9ca

4.115

Last change on this file since 5ff6a9ca was 5ff6a9ca, checked in by Sebastian Huber <sebastian.huber@…>, on 02/04/14 at 15:48:13
bsps/sparc: Remove confusing nop
Property mode set to `100644`
File size: 26.2 KB

Line
1	/* cpu_asm.s
2	*
3	* This file contains the basic algorithms for all assembly code used
4	* in an specific CPU port of RTEMS. These algorithms must be implemented
5	* in assembly language.
6	*
7	* COPYRIGHT (c) 1989-2011.
8	* On-Line Applications Research Corporation (OAR).
9	*
10	* The license and distribution terms for this file may be
11	* found in the file LICENSE in this distribution or at
12	* http://www.rtems.com/license/LICENSE.
13	*
14	* Ported to ERC32 implementation of the SPARC by On-Line Applications
15	* Research Corporation (OAR) under contract to the European Space
16	* Agency (ESA).
17	*
18	* ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
19	* European Space Agency.
20	*/
21
22	#include <rtems/asm.h>
23	#include <rtems/score/percpu.h>
24	#include <bspopts.h>
25
26	.macro GET_SELF_CPU_CONTROL REG, TMP
27	sethi %hi(_Per_CPU_Information), \REG
28	add \REG, %lo(_Per_CPU_Information), \REG
29
30	#if defined( RTEMS_SMP )
31	#if BSP_LEON3_SMP
32	/* LEON3 SMP support */
33	rd %asr17, \TMP
34	srl \TMP, 28, \TMP /* CPU number is upper 4 bits so shift */
35	#else
36	mov 0, \TMP
37	#endif
38	sll \TMP, PER_CPU_CONTROL_SIZE_LOG2, \TMP
39	add \REG, \TMP, \REG
40	#endif /* defined( RTEMS_SMP ) */
41	.endm
42
43	/*
44	* void _CPU_Context_switch(
45	* Context_Control *run,
46	* Context_Control *heir
47	* )
48	*
49	* This routine performs a normal non-FP context switch.
50	*/
51
52	.align 4
53	PUBLIC(_CPU_Context_switch)
54	SYM(_CPU_Context_switch):
55	! skip g0
56	st %g1, [%o0 + G1_OFFSET] ! save the global registers
57	std %g2, [%o0 + G2_OFFSET]
58	std %g4, [%o0 + G4_OFFSET]
59	std %g6, [%o0 + G6_OFFSET]
60
61	std %l0, [%o0 + L0_OFFSET] ! save the local registers
62	std %l2, [%o0 + L2_OFFSET]
63	std %l4, [%o0 + L4_OFFSET]
64	std %l6, [%o0 + L6_OFFSET]
65
66	std %i0, [%o0 + I0_OFFSET] ! save the input registers
67	std %i2, [%o0 + I2_OFFSET]
68	std %i4, [%o0 + I4_OFFSET]
69	std %i6, [%o0 + I6_FP_OFFSET]
70
71	std %o0, [%o0 + O0_OFFSET] ! save the output registers
72	std %o2, [%o0 + O2_OFFSET]
73	std %o4, [%o0 + O4_OFFSET]
74	std %o6, [%o0 + O6_SP_OFFSET]
75
76	! o3 = self per-CPU control
77	GET_SELF_CPU_CONTROL %o3, %o4
78
79	! load the ISR stack nesting prevention flag
80	ld [%o3 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE], %o4
81	! save it a bit later so we do not waste a couple of cycles
82
83	rd %psr, %o2
84	st %o2, [%o0 + PSR_OFFSET] ! save status register
85
86	! Now actually save ISR stack nesting prevention flag
87	st %o4, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET]
88
89	/*
90	* This is entered from _CPU_Context_restore with:
91	* o1 = context to restore
92	* o2 = psr
93	* o3 = self per-CPU control
94	*/
95
96	PUBLIC(_CPU_Context_restore_heir)
97	SYM(_CPU_Context_restore_heir):
98	/*
99	* Flush all windows with valid contents except the current one.
100	* In examining the set register windows, one may logically divide
101	* the windows into sets (some of which may be empty) based on their
102	* current status:
103	*
104	* + current (i.e. in use),
105	* + used (i.e. a restore would not trap)
106	* + invalid (i.e. 1 in corresponding bit in WIM)
107	* + unused
108	*
109	* Either the used or unused set of windows may be empty.
110	*
111	* NOTE: We assume only one bit is set in the WIM at a time.
112	*
113	* Given a CWP of 5 and a WIM of 0x1, the registers are divided
114	* into sets as follows:
115	*
116	* + 0 - invalid
117	* + 1-4 - unused
118	* + 5 - current
119	* + 6-7 - used
120	*
121	* In this case, we only would save the used windows -- 6 and 7.
122	*
123	* Traps are disabled for the same logical period as in a
124	* flush all windows trap handler.
125	*
126	* Register Usage while saving the windows:
127	* g1 = current PSR
128	* g2 = current wim
129	* g3 = CWP
130	* g4 = wim scratch
131	* g5 = scratch
132	*/
133
134	ld [%o1 + PSR_OFFSET], %g1 ! g1 = saved psr
135
136	and %o2, SPARC_PSR_CWP_MASK, %g3 ! g3 = CWP
137	! g1 = psr w/o cwp
138	andn %g1, SPARC_PSR_ET_MASK \| SPARC_PSR_CWP_MASK, %g1
139	or %g1, %g3, %g1 ! g1 = heirs psr
140	mov %g1, %psr ! restore status register and
141	! ** DISABLE TRAPS **
142	mov %wim, %g2 ! g2 = wim
143	mov 1, %g4
144	sll %g4, %g3, %g4 ! g4 = WIM mask for CW invalid
145
146	save_frame_loop:
147	sll %g4, 1, %g5 ! rotate the "wim" left 1
148	srl %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4
149	or %g4, %g5, %g4 ! g4 = wim if we do one restore
150
151	/*
152	* If a restore would not underflow, then continue.
153	*/
154
155	andcc %g4, %g2, %g0 ! Any windows to flush?
156	bnz done_flushing ! No, then continue
157	nop
158
159	restore ! back one window
160
161	/*
162	* Now save the window just as if we overflowed to it.
163	*/
164
165	std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
166	std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
167	std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
168	std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
169
170	std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
171	std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
172	std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
173	std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
174
175	ba save_frame_loop
176	nop
177
178	done_flushing:
179
180	add %g3, 1, %g3 ! calculate desired WIM
181	and %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3
182	mov 1, %g4
183	sll %g4, %g3, %g4 ! g4 = new WIM
184	mov %g4, %wim
185
186	or %g1, SPARC_PSR_ET_MASK, %g1
187	mov %g1, %psr ! ** ENABLE TRAPS **
188	! and restore CWP
189	nop
190	nop
191	nop
192
193	! skip g0
194	ld [%o1 + G1_OFFSET], %g1 ! restore the global registers
195	ldd [%o1 + G2_OFFSET], %g2
196	ldd [%o1 + G4_OFFSET], %g4
197	ldd [%o1 + G6_OFFSET], %g6
198
199	! Load thread specific ISR dispatch prevention flag
200	ld [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2
201	! Store it to memory later to use the cycles
202
203	ldd [%o1 + L0_OFFSET], %l0 ! restore the local registers
204	ldd [%o1 + L2_OFFSET], %l2
205	ldd [%o1 + L4_OFFSET], %l4
206	ldd [%o1 + L6_OFFSET], %l6
207
208	! Now restore thread specific ISR dispatch prevention flag
209	st %o2, [%o3 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
210
211	ldd [%o1 + I0_OFFSET], %i0 ! restore the output registers
212	ldd [%o1 + I2_OFFSET], %i2
213	ldd [%o1 + I4_OFFSET], %i4
214	ldd [%o1 + I6_FP_OFFSET], %i6
215
216	ldd [%o1 + O2_OFFSET], %o2 ! restore the output registers
217	ldd [%o1 + O4_OFFSET], %o4
218	ldd [%o1 + O6_SP_OFFSET], %o6
219	! do o0/o1 last to avoid destroying heir context pointer
220	ldd [%o1 + O0_OFFSET], %o0 ! overwrite heir pointer
221
222	jmp %o7 + 8 ! return
223	nop ! delay slot
224
225	/*
226	* void _CPU_Context_restore(
227	* Context_Control *new_context
228	* )
229	*
230	* This routine is generally used only to perform restart self.
231	*
232	* NOTE: It is unnecessary to reload some registers.
233	*/
234	.align 4
235	PUBLIC(_CPU_Context_restore)
236	SYM(_CPU_Context_restore):
237	save %sp, -CPU_MINIMUM_STACK_FRAME_SIZE, %sp
238	rd %psr, %o2
239	GET_SELF_CPU_CONTROL %o3, %o4
240	ba SYM(_CPU_Context_restore_heir)
241	mov %i0, %o1 ! in the delay slot
242	.align 4
243
244	#if defined(RTEMS_SMP)
245	/*
246	* void _CPU_Context_switch_to_first_task_smp(
247	* Context_Control *new_context
248	* )
249	*
250	* This routine is only used to switch to the first task on a
251	* secondary core in an SMP configuration. We do not need to
252	* flush any windows and, in fact, this can be dangerous
253	* as they may or may not be initialized properly. So we just
254	* reinitialize the PSR and WIM.
255	*/
256	PUBLIC(_CPU_Context_switch_to_first_task_smp)
257	SYM(_CPU_Context_switch_to_first_task_smp):
258	mov %psr, %g1 ! Turn of traps when modifying WIM
259	andn %g1, SPARC_PSR_ET_MASK, %g1
260	mov %g1, %psr
261	/* WIM and PSR will be set in done_flushing, it need args:
262	* g1=PSR, g3=CWP, o1=Context
263	*/
264	and %g1, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3
265	nop
266	mov %o0, %o1 ! in the delay slot
267	GET_SELF_CPU_CONTROL %o3, %o4
268	ba,a done_flushing
269	#endif
270
271	/*
272	* void _ISR_Handler()
273	*
274	* This routine provides the RTEMS interrupt management.
275	*
276	* We enter this handler from the 4 instructions in the trap table with
277	* the following registers assumed to be set as shown:
278	*
279	* l0 = PSR
280	* l1 = PC
281	* l2 = nPC
282	* l3 = trap type
283	*
284	* NOTE: By an executive defined convention, trap type is between 0 and 255 if
285	* it is an asynchonous trap and 256 and 511 if it is synchronous.
286	*/
287
288	.align 4
289	PUBLIC(_ISR_Handler)
290	SYM(_ISR_Handler):
291	/*
292	* Fix the return address for synchronous traps.
293	*/
294
295	andcc %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
296	! Is this a synchronous trap?
297	be,a win_ovflow ! No, then skip the adjustment
298	nop ! DELAY
299	mov %l1, %l6 ! save trapped pc for debug info
300	mov %l2, %l1 ! do not return to the instruction
301	add %l2, 4, %l2 ! indicated
302
303	win_ovflow:
304	/*
305	* Save the globals this block uses.
306	*
307	* These registers are not restored from the locals. Their contents
308	* are saved directly from the locals into the ISF below.
309	*/
310
311	mov %g4, %l4 ! save the globals this block uses
312	mov %g5, %l5
313
314	/*
315	* When at a "window overflow" trap, (wim == (1 << cwp)).
316	* If we get here like that, then process a window overflow.
317	*/
318
319	rd %wim, %g4
320	srl %g4, %l0, %g5 ! g5 = win >> cwp ; shift count and CWP
321	! are LS 5 bits ; how convenient :)
322	cmp %g5, 1 ! Is this an invalid window?
323	bne dont_do_the_window ! No, then skip all this stuff
324	! we are using the delay slot
325
326	/*
327	* The following is same as a 1 position right rotate of WIM
328	*/
329
330	srl %g4, 1, %g5 ! g5 = WIM >> 1
331	sll %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4
332	! g4 = WIM << (Number Windows - 1)
333	or %g4, %g5, %g4 ! g4 = (WIM >> 1) \|
334	! (WIM << (Number Windows - 1))
335
336	/*
337	* At this point:
338	*
339	* g4 = the new WIM
340	* g5 is free
341	*/
342
343	/*
344	* Since we are tinkering with the register windows, we need to
345	* make sure that all the required information is in global registers.
346	*/
347
348	save ! Save into the window
349	wr %g4, 0, %wim ! WIM = new WIM
350	nop ! delay slots
351	nop
352	nop
353
354	/*
355	* Now save the window just as if we overflowed to it.
356	*/
357
358	std %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
359	std %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
360	std %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
361	std %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
362
363	std %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
364	std %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
365	std %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
366	std %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
367
368	restore
369	nop
370
371	dont_do_the_window:
372	/*
373	* Global registers %g4 and %g5 are saved directly from %l4 and
374	* %l5 directly into the ISF below.
375	*/
376
377	save_isf:
378
379	/*
380	* Save the state of the interrupted task -- especially the global
381	* registers -- in the Interrupt Stack Frame. Note that the ISF
382	* includes a regular minimum stack frame which will be used if
383	* needed by register window overflow and underflow handlers.
384	*
385	* REGISTERS SAME AS AT _ISR_Handler
386	*/
387
388	sub %fp, CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE, %sp
389	! make space for ISF
390
391	std %l0, [%sp + ISF_PSR_OFFSET] ! save psr, PC
392	st %l2, [%sp + ISF_NPC_OFFSET] ! save nPC
393	st %g1, [%sp + ISF_G1_OFFSET] ! save g1
394	std %g2, [%sp + ISF_G2_OFFSET] ! save g2, g3
395	std %l4, [%sp + ISF_G4_OFFSET] ! save g4, g5 -- see above
396	std %g6, [%sp + ISF_G6_OFFSET] ! save g6, g7
397
398	std %i0, [%sp + ISF_I0_OFFSET] ! save i0, i1
399	std %i2, [%sp + ISF_I2_OFFSET] ! save i2, i3
400	std %i4, [%sp + ISF_I4_OFFSET] ! save i4, i5
401	std %i6, [%sp + ISF_I6_FP_OFFSET] ! save i6/fp, i7
402
403	rd %y, %g1
404	st %g1, [%sp + ISF_Y_OFFSET] ! save y
405	st %l6, [%sp + ISF_TPC_OFFSET] ! save real trapped pc
406
407	mov %sp, %o1 ! 2nd arg to ISR Handler
408
409	/*
410	* Increment ISR nest level and Thread dispatch disable level.
411	*
412	* Register usage for this section:
413	*
414	* l5 = per cpu info pointer
415	* l6 = _Thread_Dispatch_disable_level value
416	* l7 = _ISR_Nest_level value
417	*
418	* NOTE: It is assumed that l5 - l7 will be preserved until the ISR
419	* nest and thread dispatch disable levels are unnested.
420	*/
421
422	GET_SELF_CPU_CONTROL %l5, %l7
423
424	ld [%l5 + PER_CPU_ISR_NEST_LEVEL], %l7
425	ld [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
426
427	add %l7, 1, %l7
428	st %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
429
430	add %l6, 1, %l6
431	st %l6, [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
432
433	/*
434	* If ISR nest level was zero (now 1), then switch stack.
435	*/
436
437	mov %sp, %fp
438	subcc %l7, 1, %l7 ! outermost interrupt handler?
439	bnz dont_switch_stacks ! No, then do not switch stacks
440
441	nop
442	ld [%l5 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
443
444	dont_switch_stacks:
445	/*
446	* Make sure we have a place on the stack for the window overflow
447	* trap handler to write into. At this point it is safe to
448	* enable traps again.
449	*/
450
451	sub %sp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
452
453	/*
454	* Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
455	* set the PIL in the %psr to mask off interrupts with lower priority.
456	* The original %psr in %l0 is not modified since it will be restored
457	* when the interrupt handler returns.
458	*/
459
460	mov %l0, %g5
461	and %l3, 0x0ff, %g4
462
463	/* This is a fix for ERC32 with FPU rev.B or rev.C */
464
465	#if defined(FPU_REVB)
466
467
468	subcc %g4, 0x08, %g0
469	be fpu_revb
470	subcc %g4, 0x11, %g0
471	bl dont_fix_pil
472	subcc %g4, 0x1f, %g0
473	bg dont_fix_pil
474	sll %g4, 8, %g4
475	and %g4, SPARC_PSR_PIL_MASK, %g4
476	andn %l0, SPARC_PSR_PIL_MASK, %g5
477	or %g4, %g5, %g5
478	srl %l0, 12, %g4
479	andcc %g4, 1, %g0
480	be dont_fix_pil
481	nop
482	ba,a enable_irq
483
484
485	fpu_revb:
486	srl %l0, 12, %g4 ! check if EF is set in %psr
487	andcc %g4, 1, %g0
488	be dont_fix_pil ! if FPU disabled than continue as normal
489	and %l3, 0xff, %g4
490	subcc %g4, 0x08, %g0
491	bne enable_irq ! if not a FPU exception then do two fmovs
492	set __sparc_fq, %g4
493	st %fsr, [%g4] ! if FQ is not empty and FQ[1] = fmovs
494	ld [%g4], %g4 ! than this is bug 3.14
495	srl %g4, 13, %g4
496	andcc %g4, 1, %g0
497	be dont_fix_pil
498	set __sparc_fq, %g4
499	std %fq, [%g4]
500	ld [%g4+4], %g4
501	set 0x81a00020, %g5
502	subcc %g4, %g5, %g0
503	bne,a dont_fix_pil2
504	wr %l0, SPARC_PSR_ET_MASK, %psr ! ** ENABLE TRAPS **
505	ba,a simple_return
506
507	enable_irq:
508	or %g5, SPARC_PSR_PIL_MASK, %g4
509	wr %g4, SPARC_PSR_ET_MASK, %psr ! ** ENABLE TRAPS **
510	nop; nop; nop
511	fmovs %f0, %f0
512	ba dont_fix_pil
513	fmovs %f0, %f0
514
515	.data
516	.global __sparc_fq
517	.align 8
518	__sparc_fq:
519	.word 0,0
520
521	.text
522	/* end of ERC32 FPU rev.B/C fix */
523
524	#else
525
526	subcc %g4, 0x11, %g0
527	bl dont_fix_pil
528	subcc %g4, 0x1f, %g0
529	bg dont_fix_pil
530	sll %g4, 8, %g4
531	and %g4, SPARC_PSR_PIL_MASK, %g4
532	andn %l0, SPARC_PSR_PIL_MASK, %g5
533	ba pil_fixed
534	or %g4, %g5, %g5
535	#endif
536
537	dont_fix_pil:
538	or %g5, SPARC_PSR_PIL_MASK, %g5
539	pil_fixed:
540	wr %g5, SPARC_PSR_ET_MASK, %psr ! ** ENABLE TRAPS **
541	dont_fix_pil2:
542
543	/*
544	* Vector to user's handler.
545	*
546	* NOTE: TBR may no longer have vector number in it since
547	* we just enabled traps. It is definitely in l3.
548	*/
549
550	sethi %hi(SYM(_ISR_Vector_table)), %g4
551	ld [%g4+%lo(SYM(_ISR_Vector_table))], %g4
552	and %l3, 0xFF, %g5 ! remove synchronous trap indicator
553	sll %g5, 2, %g5 ! g5 = offset into table
554	ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ]
555
556
557	! o1 = 2nd arg = address of the ISF
558	! WAS LOADED WHEN ISF WAS SAVED!!!
559	mov %l3, %o0 ! o0 = 1st arg = vector number
560	call %g4, 0
561	nop ! delay slot
562
563	/*
564	* Redisable traps so we can finish up the interrupt processing.
565	* This is a VERY conservative place to do this.
566	*
567	* NOTE: %l0 has the PSR which was in place when we took the trap.
568	*/
569
570	mov %l0, %psr ! ** DISABLE TRAPS **
571	nop; nop; nop
572
573	/*
574	* Decrement ISR nest level and Thread dispatch disable level.
575	*
576	* Register usage for this section:
577	*
578	* l5 = per cpu info pointer
579	* l6 = _Thread_Dispatch_disable_level value
580	* l7 = _ISR_Nest_level value
581	*/
582
583	st %l7, [%l5 + PER_CPU_ISR_NEST_LEVEL]
584
585	sub %l6, 1, %l6
586	st %l6, [%l5 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
587
588	/*
589	* If dispatching is disabled (includes nested interrupt case),
590	* then do a "simple" exit.
591	*/
592
593	orcc %l6, %g0, %g0 ! Is dispatching disabled?
594	bnz simple_return ! Yes, then do a "simple" exit
595	nop
596
597	! Are we dispatching from a previous ISR in the interrupted thread?
598	ld [%l5 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE], %l7
599	orcc %l7, %g0, %g0 ! Is this thread already doing an ISR?
600	bnz simple_return ! Yes, then do a "simple" exit
601	nop
602
603
604	/*
605	* If a context switch is necessary, then do fudge stack to
606	* return to the interrupt dispatcher.
607	*/
608
609	ldub [%l5 + PER_CPU_DISPATCH_NEEDED], %l6
610
611	orcc %l6, %g0, %g0 ! Is thread switch necessary?
612	bz simple_return ! no, then do a simple return
613	nop
614
615	/*
616	* Invoke interrupt dispatcher.
617	*/
618
619	! Set ISR dispatch nesting prevention flag
620	mov 1,%l6
621	st %l6, [%l5 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
622
623	/*
624	* The following subtract should get us back on the interrupted
625	* tasks stack and add enough room to invoke the dispatcher.
626	* When we enable traps, we are mostly back in the context
627	* of the task and subsequent interrupts can operate normally.
628	*/
629
630	sub %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
631
632	or %l0, SPARC_PSR_ET_MASK, %l7 ! l7 = PSR with ET=1
633	mov %l7, %psr ! ** ENABLE TRAPS **
634	nop
635	nop
636	nop
637	isr_dispatch:
638	call SYM(_Thread_Dispatch), 0
639	nop
640
641	/*
642	* We invoked _Thread_Dispatch in a state similar to the interrupted
643	* task. In order to safely be able to tinker with the register
644	* windows and get the task back to its pre-interrupt state,
645	* we need to disable interrupts disabled so we can safely tinker
646	* with the register windowing. In particular, the CWP in the PSR
647	* is fragile during this period. (See PR578.)
648	*/
649	mov 2,%g1 ! syscall (disable interrupts)
650	ta 0 ! syscall (disable interrupts)
651
652	/*
653	* While we had ISR dispatching disabled in this thread,
654	* did we miss anything. If so, then we need to do another
655	* _Thread_Dispatch before leaving this ISR Dispatch context.
656	*/
657
658	GET_SELF_CPU_CONTROL %l5, %l7
659
660	ldub [%l5 + PER_CPU_DISPATCH_NEEDED], %l7
661
662	orcc %l7, %g0, %g0 ! Is thread switch necesary?
663	bz allow_nest_again ! No, then clear out and return
664	nop
665
666	! Yes, then invoke the dispatcher
667	dispatchAgain:
668	mov 3,%g1 ! syscall (enable interrupts)
669	ta 0 ! syscall (enable interrupts)
670	ba isr_dispatch
671	nop
672
673	allow_nest_again:
674
675	! Zero out ISR stack nesting prevention flag
676	st %g0, [%l5 + SPARC_PER_CPU_ISR_DISPATCH_DISABLE]
677
678	/*
679	* The CWP in place at this point may be different from
680	* that which was in effect at the beginning of the ISR if we
681	* have been context switched between the beginning of this invocation
682	* of _ISR_Handler and this point. Thus the CWP and WIM should
683	* not be changed back to their values at ISR entry time. Any
684	* changes to the PSR must preserve the CWP.
685	*/
686
687	simple_return:
688	ld [%fp + ISF_Y_OFFSET], %l5 ! restore y
689	wr %l5, 0, %y
690
691	ldd [%fp + ISF_PSR_OFFSET], %l0 ! restore psr, PC
692	ld [%fp + ISF_NPC_OFFSET], %l2 ! restore nPC
693	rd %psr, %l3
694	and %l3, SPARC_PSR_CWP_MASK, %l3 ! want "current" CWP
695	andn %l0, SPARC_PSR_CWP_MASK, %l0 ! want rest from task
696	or %l3, %l0, %l0 ! install it later...
697	andn %l0, SPARC_PSR_ET_MASK, %l0
698
699	/*
700	* Restore tasks global and out registers
701	*/
702
703	mov %fp, %g1
704
705	! g1 is restored later
706	ldd [%fp + ISF_G2_OFFSET], %g2 ! restore g2, g3
707	ldd [%fp + ISF_G4_OFFSET], %g4 ! restore g4, g5
708	ldd [%fp + ISF_G6_OFFSET], %g6 ! restore g6, g7
709
710	ldd [%fp + ISF_I0_OFFSET], %i0 ! restore i0, i1
711	ldd [%fp + ISF_I2_OFFSET], %i2 ! restore i2, i3
712	ldd [%fp + ISF_I4_OFFSET], %i4 ! restore i4, i5
713	ldd [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7
714
715	/*
716	* Registers:
717	*
718	* ALL global registers EXCEPT G1 and the input registers have
719	* already been restored and thuse off limits.
720	*
721	* The following is the contents of the local registers:
722	*
723	* l0 = original psr
724	* l1 = return address (i.e. PC)
725	* l2 = nPC
726	* l3 = CWP
727	*/
728
729	/*
730	* if (CWP + 1) is an invalid window then we need to reload it.
731	*
732	* WARNING: Traps should now be disabled
733	*/
734
735	mov %l0, %psr ! ** DISABLE TRAPS **
736	nop
737	nop
738	nop
739	rd %wim, %l4
740	add %l0, 1, %l6 ! l6 = cwp + 1
741	and %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it
742	srl %l4, %l6, %l5 ! l5 = win >> cwp + 1 ; shift count
743	! and CWP are conveniently LS 5 bits
744	cmp %l5, 1 ! Is tasks window invalid?
745	bne good_task_window
746
747	/*
748	* The following code is the same as a 1 position left rotate of WIM.
749	*/
750
751	sll %l4, 1, %l5 ! l5 = WIM << 1
752	srl %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4
753	! l4 = WIM >> (Number Windows - 1)
754	or %l4, %l5, %l4 ! l4 = (WIM << 1) \|
755	! (WIM >> (Number Windows - 1))
756
757	/*
758	* Now restore the window just as if we underflowed to it.
759	*/
760
761	wr %l4, 0, %wim ! WIM = new WIM
762	nop ! must delay after writing WIM
763	nop
764	nop
765	restore ! now into the tasks window
766
767	ldd [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0
768	ldd [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2
769	ldd [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4
770	ldd [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6
771	ldd [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0
772	ldd [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2
773	ldd [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4
774	ldd [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
775	! reload of sp clobbers ISF
776	save ! Back to ISR dispatch window
777
778	good_task_window:
779
780	mov %l0, %psr ! ** DISABLE TRAPS **
781	nop; nop; nop
782	! and restore condition codes.
783	ld [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
784	jmp %l1 ! transfer control and
785	rett %l2 ! go back to tasks window
786
787	/* end of file */

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Original Format