source: rtems/c/src/lib/libbsp/sparc/shared/irq_asm.S @ 32b4a0c

5
Last change on this file since 32b4a0c was 32b4a0c, checked in by Sebastian Huber <sebastian.huber@…>, on 06/09/17 at 05:25:02

Simplify TLS support in context switch

There is no need to save the thread pointer in _CPU_Context_switch()
since it is a thread invariant. It is initialized once in
_CPU_Context_Initialize().

  • Property mode set to 100644
File size: 29.8 KB
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1/*  cpu_asm.s
2 *
3 *  This file contains the basic algorithms for all assembly code used
4 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
5 *  in assembly language.
6 *
7 *  COPYRIGHT (c) 1989-2011.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  Copyright (c) 2014, 2016 embedded brains GmbH
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.org/license/LICENSE.
15 *
16 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
17 *  Research Corporation (OAR) under contract to the European Space
18 *  Agency (ESA).
19 *
20 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
21 *  European Space Agency.
22 */
23
24#include <rtems/asm.h>
25#include <rtems/score/percpu.h>
26#include <bspopts.h>
27
28#if SPARC_HAS_FPU == 1 && defined(SPARC_USE_SAFE_FP_SUPPORT)
29  #define FP_FRAME_OFFSET_FO_F1 (SPARC_MINIMUM_STACK_FRAME_SIZE + 0)
30  #define FP_FRAME_OFFSET_F2_F3 (FP_FRAME_OFFSET_FO_F1 + 8)
31  #define FP_FRAME_OFFSET_F4_F5 (FP_FRAME_OFFSET_F2_F3 + 8)
32  #define FP_FRAME_OFFSET_F6_F7 (FP_FRAME_OFFSET_F4_F5 + 8)
33  #define FP_FRAME_OFFSET_F8_F9 (FP_FRAME_OFFSET_F6_F7 + 8)
34  #define FP_FRAME_OFFSET_F1O_F11 (FP_FRAME_OFFSET_F8_F9 + 8)
35  #define FP_FRAME_OFFSET_F12_F13 (FP_FRAME_OFFSET_F1O_F11 + 8)
36  #define FP_FRAME_OFFSET_F14_F15 (FP_FRAME_OFFSET_F12_F13 + 8)
37  #define FP_FRAME_OFFSET_F16_F17 (FP_FRAME_OFFSET_F14_F15 + 8)
38  #define FP_FRAME_OFFSET_F18_F19 (FP_FRAME_OFFSET_F16_F17 + 8)
39  #define FP_FRAME_OFFSET_F2O_F21 (FP_FRAME_OFFSET_F18_F19 + 8)
40  #define FP_FRAME_OFFSET_F22_F23 (FP_FRAME_OFFSET_F2O_F21 + 8)
41  #define FP_FRAME_OFFSET_F24_F25 (FP_FRAME_OFFSET_F22_F23 + 8)
42  #define FP_FRAME_OFFSET_F26_F27 (FP_FRAME_OFFSET_F24_F25 + 8)
43  #define FP_FRAME_OFFSET_F28_F29 (FP_FRAME_OFFSET_F26_F27 + 8)
44  #define FP_FRAME_OFFSET_F3O_F31 (FP_FRAME_OFFSET_F28_F29 + 8)
45  #define FP_FRAME_OFFSET_FSR (FP_FRAME_OFFSET_F3O_F31 + 8)
46  #define FP_FRAME_SIZE (FP_FRAME_OFFSET_FSR + 8)
47#endif
48
49/*
50 *  void _CPU_Context_switch(
51 *    Context_Control  *run,
52 *    Context_Control  *heir
53 *  )
54 *
55 *  This routine performs a normal non-FP context switch.
56 */
57
58        .align 4
59        PUBLIC(_CPU_Context_switch)
60SYM(_CPU_Context_switch):
61        st      %g5, [%o0 + G5_OFFSET]       ! save the global registers
62
63        /*
64         * No need to save the thread pointer %g7 since it is a thread
65         * invariant.  It is initialized once in _CPU_Context_Initialize().
66         */
67
68        std     %l0, [%o0 + L0_OFFSET]       ! save the local registers
69        std     %l2, [%o0 + L2_OFFSET]
70        std     %l4, [%o0 + L4_OFFSET]
71        std     %l6, [%o0 + L6_OFFSET]
72
73        std     %i0, [%o0 + I0_OFFSET]       ! save the input registers
74        std     %i2, [%o0 + I2_OFFSET]
75        std     %i4, [%o0 + I4_OFFSET]
76        std     %i6, [%o0 + I6_FP_OFFSET]
77
78        std     %o6, [%o0 + O6_SP_OFFSET]    ! save the output registers
79
80        ! load the ISR stack nesting prevention flag
81        ld      [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o4
82        ! save it a bit later so we do not waste a couple of cycles
83
84        rd      %psr, %o2
85        st      %o2, [%o0 + PSR_OFFSET]      ! save status register
86
87        ! Now actually save ISR stack nesting prevention flag
88        st       %o4, [%o0 + ISR_DISPATCH_DISABLE_STACK_OFFSET]
89
90        /*
91         *  This is entered from _CPU_Context_restore with:
92         *    o1 = context to restore
93         *    o2 = psr
94         */
95
96        PUBLIC(_CPU_Context_restore_heir)
97SYM(_CPU_Context_restore_heir):
98        /*
99         *  Flush all windows with valid contents except the current one.
100         *  In examining the set register windows, one may logically divide
101         *  the windows into sets (some of which may be empty) based on their
102         *  current status:
103         *
104         *    + current (i.e. in use),
105         *    + used (i.e. a restore would not trap)
106         *    + invalid (i.e. 1 in corresponding bit in WIM)
107         *    + unused
108         *
109         *  Either the used or unused set of windows may be empty.
110         *
111         *  NOTE: We assume only one bit is set in the WIM at a time.
112         *
113         *  Given a CWP of 5 and a WIM of 0x1, the registers are divided
114         *  into sets as follows:
115         *
116         *    + 0   - invalid
117         *    + 1-4 - unused
118         *    + 5   - current
119         *    + 6-7 - used
120         *
121         *  In this case, we only would save the used windows -- 6 and 7.
122         *
123         *   Traps are disabled for the same logical period as in a
124         *     flush all windows trap handler.
125         *
126         *    Register Usage while saving the windows:
127         *      g1 = current PSR
128         *      g2 = current wim
129         *      g3 = CWP
130         *      g4 = wim scratch
131         *      g5 = scratch
132         */
133
134        and     %o2, SPARC_PSR_CWP_MASK, %g3  ! g3 = CWP
135        andn    %o2, SPARC_PSR_ET_MASK, %g1   ! g1 = psr with traps disabled
136        mov     %g1, %psr                     ! **** DISABLE TRAPS ****
137        mov     %wim, %g2                     ! g2 = wim
138        mov     1, %g4
139        sll     %g4, %g3, %g4                 ! g4 = WIM mask for CW invalid
140
141save_frame_loop:
142        sll     %g4, 1, %g5                   ! rotate the "wim" left 1
143        srl     %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g4
144        or      %g4, %g5, %g4                 ! g4 = wim if we do one restore
145
146        /*
147         *  If a restore would not underflow, then continue.
148         */
149
150        andcc   %g4, %g2, %g0                 ! Any windows to flush?
151        bnz     done_flushing                 ! No, then continue
152        nop
153
154        restore                               ! back one window
155
156        /*
157         *  Now save the window just as if we overflowed to it.
158         */
159
160        std     %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
161        std     %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
162        std     %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
163        std     %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
164
165        std     %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
166        std     %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
167        std     %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
168        std     %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
169
170        ba      save_frame_loop
171        nop
172
173done_flushing:
174
175        ! Wait three instructions after the write to PSR before using
176        ! non-global registers or instructions affecting the CWP
177        mov     %g1, %psr                     ! restore cwp
178        add     %g3, 1, %g2                   ! calculate desired WIM
179        and     %g2, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g2
180        mov     1, %g4
181        sll     %g4, %g2, %g4                 ! g4 = new WIM
182        mov     %g4, %wim
183
184#if defined(RTEMS_SMP)
185        /*
186         * The executing thread no longer executes on this processor.  Switch
187         * the stack to the temporary interrupt stack of this processor.  Mark
188         * the context of the executing thread as not executing.
189         */
190        add     %g6, PER_CPU_INTERRUPT_FRAME_AREA + CPU_INTERRUPT_FRAME_SIZE, %sp
191        st      %g0, [%o0 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET]
192
193        ! Try to update the is executing indicator of the heir context
194        mov     1, %g1
195
196.Ltry_update_is_executing:
197
198        swap    [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1
199        cmp     %g1, 0
200        bne     .Lcheck_is_executing
201
202        ! The next load is in a delay slot, which is all right
203#endif
204
205        ld      [%o1 + PSR_OFFSET], %g1       ! g1 = heir psr with traps enabled
206        andn    %g1, SPARC_PSR_CWP_MASK, %g1  ! g1 = heir psr w/o cwp
207        or      %g1, %g3, %g1                 ! g1 = heir psr with cwp
208        mov     %g1, %psr                     ! restore status register and
209                                              ! **** ENABLE TRAPS ****
210
211        ld      [%o1 + G5_OFFSET], %g5        ! restore the global registers
212        ld      [%o1 + G7_OFFSET], %g7
213
214        ! Load thread specific ISR dispatch prevention flag
215        ld      [%o1 + ISR_DISPATCH_DISABLE_STACK_OFFSET], %o2
216        ! Store it to memory later to use the cycles
217
218        ldd     [%o1 + L0_OFFSET], %l0        ! restore the local registers
219        ldd     [%o1 + L2_OFFSET], %l2
220        ldd     [%o1 + L4_OFFSET], %l4
221        ldd     [%o1 + L6_OFFSET], %l6
222
223        ! Now restore thread specific ISR dispatch prevention flag
224        st      %o2, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
225
226        ldd     [%o1 + I0_OFFSET], %i0        ! restore the input registers
227        ldd     [%o1 + I2_OFFSET], %i2
228        ldd     [%o1 + I4_OFFSET], %i4
229        ldd     [%o1 + I6_FP_OFFSET], %i6
230
231        ldd     [%o1 + O6_SP_OFFSET], %o6     ! restore the output registers
232
233        jmp     %o7 + 8                       ! return
234        nop                                   ! delay slot
235
236#if defined(RTEMS_SMP)
237.Lcheck_is_executing:
238
239        ! Check the is executing indicator of the heir context
240        ld      [%o1 + SPARC_CONTEXT_CONTROL_IS_EXECUTING_OFFSET], %g1
241        cmp     %g1, 0
242        beq     .Ltry_update_is_executing
243         mov    1, %g1
244
245        ! We may have a new heir
246
247        ! Read the executing and heir
248        ld      [%g6 + PER_CPU_OFFSET_EXECUTING], %g2
249        ld      [%g6 + PER_CPU_OFFSET_HEIR], %g4
250
251        ! Update the executing only if necessary to avoid cache line
252        ! monopolization.
253        cmp     %g2, %g4
254        beq     .Ltry_update_is_executing
255         mov    1, %g1
256
257        ! Calculate the heir context pointer
258        sub     %o1, %g2, %g2
259        add     %g2, %g4, %o1
260
261        ! Update the executing
262        st      %g4, [%g6 + PER_CPU_OFFSET_EXECUTING]
263
264        ba      .Ltry_update_is_executing
265         mov    1, %g1
266#endif
267
268/*
269 *  void _CPU_Context_restore(
270 *    Context_Control *new_context
271 *  )
272 *
273 *  This routine is generally used only to perform restart self.
274 *
275 *  NOTE: It is unnecessary to reload some registers.
276 */
277        .align 4
278        PUBLIC(_CPU_Context_restore)
279SYM(_CPU_Context_restore):
280        save    %sp, -SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
281        rd      %psr, %o2
282#if defined(RTEMS_SMP)
283        ! On SPARC the restore path needs also a valid executing context on SMP
284        ! to update the is executing indicator.
285        mov     %i0, %o0
286#endif
287        ba      SYM(_CPU_Context_restore_heir)
288        mov     %i0, %o1                      ! in the delay slot
289
290/*
291 *  void _ISR_Handler()
292 *
293 *  This routine provides the RTEMS interrupt management.
294 *
295 *  We enter this handler from the 4 instructions in the trap table with
296 *  the following registers assumed to be set as shown:
297 *
298 *    l0 = PSR
299 *    l1 = PC
300 *    l2 = nPC
301 *    l3 = trap type
302 *
303 *  NOTE: By an executive defined convention, trap type is between 0 and 255 if
304 *        it is an asynchonous trap and 256 and 511 if it is synchronous.
305 */
306
307        .align 4
308        PUBLIC(_ISR_Handler)
309SYM(_ISR_Handler):
310        /*
311         *  Fix the return address for synchronous traps.
312         */
313
314        andcc   %l3, SPARC_SYNCHRONOUS_TRAP_BIT_MASK, %g0
315                                      ! Is this a synchronous trap?
316        be,a    win_ovflow            ! No, then skip the adjustment
317        nop                           ! DELAY
318        mov     %l1, %l6              ! save trapped pc for debug info
319        mov     %l2, %l1              ! do not return to the instruction
320        add     %l2, 4, %l2           ! indicated
321
322win_ovflow:
323        /*
324         *  Save the globals this block uses.
325         *
326         *  These registers are not restored from the locals.  Their contents
327         *  are saved directly from the locals into the ISF below.
328         */
329
330        mov     %g4, %l4                 ! save the globals this block uses
331        mov     %g5, %l5
332
333        /*
334         *  When at a "window overflow" trap, (wim == (1 << cwp)).
335         *  If we get here like that, then process a window overflow.
336         */
337
338        rd      %wim, %g4
339        srl     %g4, %l0, %g5            ! g5 = win >> cwp ; shift count and CWP
340                                         !   are LS 5 bits ; how convenient :)
341        cmp     %g5, 1                   ! Is this an invalid window?
342        bne     dont_do_the_window       ! No, then skip all this stuff
343        ! we are using the delay slot
344
345        /*
346         *  The following is same as a 1 position right rotate of WIM
347         */
348
349        srl     %g4, 1, %g5              ! g5 = WIM >> 1
350        sll     %g4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %g4
351                                         ! g4 = WIM << (Number Windows - 1)
352        or      %g4, %g5, %g4            ! g4 = (WIM >> 1) |
353                                         !      (WIM << (Number Windows - 1))
354
355        /*
356         *  At this point:
357         *
358         *    g4 = the new WIM
359         *    g5 is free
360         */
361
362        /*
363         *  Since we are tinkering with the register windows, we need to
364         *  make sure that all the required information is in global registers.
365         */
366
367        save                          ! Save into the window
368        wr      %g4, 0, %wim          ! WIM = new WIM
369        nop                           ! delay slots
370        nop
371        nop
372
373        /*
374         *  Now save the window just as if we overflowed to it.
375         */
376
377        std     %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
378        std     %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
379        std     %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
380        std     %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
381
382        std     %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
383        std     %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
384        std     %i4, [%sp + CPU_STACK_FRAME_I4_OFFSET]
385        std     %i6, [%sp + CPU_STACK_FRAME_I6_FP_OFFSET]
386
387        restore
388        nop
389
390dont_do_the_window:
391        /*
392         *  Global registers %g4 and %g5 are saved directly from %l4 and
393         *  %l5 directly into the ISF below.
394         */
395
396        /*
397         *  Save the state of the interrupted task -- especially the global
398         *  registers -- in the Interrupt Stack Frame.  Note that the ISF
399         *  includes a regular minimum stack frame which will be used if
400         *  needed by register window overflow and underflow handlers.
401         *
402         *  REGISTERS SAME AS AT _ISR_Handler
403         */
404
405        sub     %fp, CPU_INTERRUPT_FRAME_SIZE, %sp
406                                               ! make space for ISF
407
408        std     %l0, [%sp + ISF_PSR_OFFSET]    ! save psr, PC
409        st      %l2, [%sp + ISF_NPC_OFFSET]    ! save nPC
410        st      %g1, [%sp + ISF_G1_OFFSET]     ! save g1
411        std     %g2, [%sp + ISF_G2_OFFSET]     ! save g2, g3
412        std     %l4, [%sp + ISF_G4_OFFSET]     ! save g4, g5 -- see above
413        st      %g7, [%sp + ISF_G7_OFFSET]     ! save g7
414
415        std     %i0, [%sp + ISF_I0_OFFSET]     ! save i0, i1
416        std     %i2, [%sp + ISF_I2_OFFSET]     ! save i2, i3
417        std     %i4, [%sp + ISF_I4_OFFSET]     ! save i4, i5
418        std     %i6, [%sp + ISF_I6_FP_OFFSET]  ! save i6/fp, i7
419
420        rd      %y, %g1
421        st      %g1, [%sp + ISF_Y_OFFSET]      ! save y
422        st      %l6, [%sp + ISF_TPC_OFFSET]    ! save real trapped pc
423
424        mov     %sp, %o1                       ! 2nd arg to ISR Handler
425
426        /*
427         *  Increment ISR nest level and Thread dispatch disable level.
428         *
429         *  Register usage for this section:
430         *
431         *    l6 = _Thread_Dispatch_disable_level value
432         *    l7 = _ISR_Nest_level value
433         *
434         *  NOTE: It is assumed that l6 - l7 will be preserved until the ISR
435         *        nest and thread dispatch disable levels are unnested.
436         */
437
438        ld       [%g6 + PER_CPU_ISR_NEST_LEVEL], %l7
439        ld       [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL], %l6
440
441        add      %l7, 1, %l7
442        st       %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
443
444        add      %l6, 1, %l6
445        st       %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
446
447#if SPARC_HAS_FPU == 1
448        /*
449         * We cannot use an intermediate value for operations with the PSR[EF]
450         * bit since they use a 13-bit sign extension and PSR[EF] is bit 12.
451         */
452        sethi    %hi(SPARC_PSR_EF_MASK), %l5
453#endif
454
455        /*
456         *  If ISR nest level was zero (now 1), then switch stack.
457         */
458
459        mov      %sp, %fp
460        subcc    %l7, 1, %l7             ! outermost interrupt handler?
461        bnz      dont_switch_stacks      ! No, then do not switch stacks
462
463#if defined(RTEMS_PROFILING)
464         sethi   %hi(_SPARC_Counter), %o5
465        ld       [%o5 + %lo(_SPARC_Counter)], %l4
466        call     %l4
467         nop
468        mov      %o0, %o5
469#else
470         nop
471#endif
472
473        ld       [%g6 + PER_CPU_INTERRUPT_STACK_HIGH], %sp
474
475#if SPARC_HAS_FPU == 1
476        /*
477         * Test if the interrupted thread uses the floating point unit
478         * (PSR[EF] == 1).  In case it uses the floating point unit, then store
479         * the floating point status register.  This has the side-effect that
480         * all pending floating point operations complete before the store
481         * completes.  The PSR[EF] bit is restored after the call to the
482         * interrupt handler.  Thus post-switch actions (e.g. signal handlers)
483         * and context switch extensions may still corrupt the floating point
484         * context.
485         */
486        andcc    %l0, %l5, %g0
487        bne,a    dont_switch_stacks
488         st      %fsr, [%g6 + SPARC_PER_CPU_FSR_OFFSET]
489#endif
490
491dont_switch_stacks:
492        /*
493         *  Make sure we have a place on the stack for the window overflow
494         *  trap handler to write into.  At this point it is safe to
495         *  enable traps again.
496         */
497
498        sub      %sp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
499
500        /*
501         *  Check if we have an external interrupt (trap 0x11 - 0x1f). If so,
502         *  set the PIL in the %psr to mask off interrupts with lower priority.
503         *  The original %psr in %l0 is not modified since it will be restored
504         *  when the interrupt handler returns.
505         */
506
507        mov      %l0, %g5
508        and      %l3, 0x0ff, %g4
509        subcc    %g4, 0x11, %g0
510        bl       dont_fix_pil
511        subcc    %g4, 0x1f, %g0
512        bg       dont_fix_pil
513        sll      %g4, 8, %g4
514        and      %g4, SPARC_PSR_PIL_MASK, %g4
515        andn     %l0, SPARC_PSR_PIL_MASK, %g5
516        ba       pil_fixed
517        or       %g4, %g5, %g5
518dont_fix_pil:
519        or       %g5, SPARC_PSR_PIL_MASK, %g5
520pil_fixed:
521
522#if SPARC_HAS_FPU == 1
523        /*
524         * Clear the PSR[EF] bit of the interrupted context to ensure that
525         * interrupt service routines cannot corrupt the floating point context.
526         */
527        andn     %g5, %l5, %g5
528#endif
529
530        wr       %g5, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
531
532        /*
533         *  Vector to user's handler.
534         *
535         *  NOTE: TBR may no longer have vector number in it since
536         *        we just enabled traps.  It is definitely in l3.
537         */
538
539        sethi    %hi(SYM(_ISR_Vector_table)), %g4
540        or       %g4, %lo(SYM(_ISR_Vector_table)), %g4
541        and      %l3, 0xFF, %g5         ! remove synchronous trap indicator
542        sll      %g5, 2, %g5            ! g5 = offset into table
543        ld       [%g4 + %g5], %g4       ! g4 = _ISR_Vector_table[ vector ]
544
545
546                                        ! o1 = 2nd arg = address of the ISF
547                                        !   WAS LOADED WHEN ISF WAS SAVED!!!
548        mov      %l3, %o0               ! o0 = 1st arg = vector number
549        call     %g4
550#if defined(RTEMS_PROFILING)
551         mov     %o5, %l3               ! save interrupt entry instant
552#else
553         nop                            ! delay slot
554#endif
555
556#if SPARC_HAS_FPU == 1
557        mov      %l0, %g1               ! PSR[EF] value of interrupted context
558        ta       SPARC_SWTRAP_IRQDIS_FP ! **** DISABLE INTERRUPTS ****
559#else
560        ta       SPARC_SWTRAP_IRQDIS    ! **** DISABLE INTERRUPTS ****
561#endif
562
563#if defined(RTEMS_PROFILING)
564        cmp      %l7, 0
565        bne      profiling_not_outer_most_exit
566         nop
567        call     %l4                    ! Call _SPARC_Counter.counter_read
568         mov     %g1, %l4               ! Save previous interrupt status
569        mov      %o0, %o2               ! o2 = 3rd arg = interrupt exit instant
570        mov      %l3, %o1               ! o1 = 2nd arg = interrupt entry instant
571        call     SYM(_Profiling_Outer_most_interrupt_entry_and_exit)
572         mov     %g6, %o0               ! o0 = 1st arg = per-CPU control
573profiling_not_outer_most_exit:
574#endif
575
576        /*
577         *  Decrement ISR nest level and Thread dispatch disable level.
578         *
579         *  Register usage for this section:
580         *
581         *    o2 = g6->dispatch_necessary value
582         *    o3 = g6->isr_dispatch_disable value
583         *    l6 = g6->thread_dispatch_disable_level value
584         *    l7 = g6->isr_nest_level value
585         */
586
587        ldub     [%g6 + PER_CPU_DISPATCH_NEEDED], %o2
588        ld       [%g6 + PER_CPU_ISR_DISPATCH_DISABLE], %o3
589        st       %l7, [%g6 + PER_CPU_ISR_NEST_LEVEL]
590        sub      %l6, 1, %l6
591        st       %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
592
593        /*
594         * Thread dispatching is necessary and allowed if and only if
595         *   g6->dispatch_necessary == 1 and
596         *   g6->isr_dispatch_disable == 0 and
597         *   g6->thread_dispatch_disable_level == 0.
598         *
599         * Otherwise, continue with the simple return.
600         */
601        xor      %o2, 1, %o2
602        or       %o2, %l6, %o2
603        orcc     %o2, %o3, %o2
604        bnz      simple_return
605
606        /*
607         * Switch back on the interrupted tasks stack and add enough room to
608         * invoke the dispatcher.  Doing this in the delay slot causes no harm,
609         * since the stack pointer (%sp) is not used in the simple return path.
610         */
611         sub     %fp, SPARC_MINIMUM_STACK_FRAME_SIZE, %sp
612
613isr_dispatch:
614
615        /* Set ISR dispatch disable and thread dispatch disable level to one */
616        mov      1, %l6
617        st       %l6, [%g6 + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL]
618        st       %l6, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
619
620        /* Call _Thread_Do_dispatch(), this function will enable interrupts */
621
622        mov      0, %o1                 ! ISR level for _Thread_Do_dispatch()
623
624#if SPARC_HAS_FPU == 1 && defined(SPARC_USE_SAFE_FP_SUPPORT)
625        /* Test if we interrupted a floating point thread (PSR[EF] == 1) */
626        andcc   %l0, %l5, %g0
627        be      non_fp_thread_dispatch
628         nop
629
630        /*
631         * Yes, this is a floating point thread, then save the floating point
632         * context to a new stack frame.  Then do the thread dispatch.
633         * Post-switch actions (e.g. signal handlers) and context switch
634         * extensions may safely use the floating point unit.
635         */
636        sub     %sp, FP_FRAME_SIZE, %sp
637        std     %f0, [%sp + FP_FRAME_OFFSET_FO_F1]
638        std     %f2, [%sp + FP_FRAME_OFFSET_F2_F3]
639        std     %f4, [%sp + FP_FRAME_OFFSET_F4_F5]
640        std     %f6, [%sp + FP_FRAME_OFFSET_F6_F7]
641        std     %f8, [%sp + FP_FRAME_OFFSET_F8_F9]
642        std     %f10, [%sp + FP_FRAME_OFFSET_F1O_F11]
643        std     %f12, [%sp + FP_FRAME_OFFSET_F12_F13]
644        std     %f14, [%sp + FP_FRAME_OFFSET_F14_F15]
645        std     %f16, [%sp + FP_FRAME_OFFSET_F16_F17]
646        std     %f18, [%sp + FP_FRAME_OFFSET_F18_F19]
647        std     %f20, [%sp + FP_FRAME_OFFSET_F2O_F21]
648        std     %f22, [%sp + FP_FRAME_OFFSET_F22_F23]
649        std     %f24, [%sp + FP_FRAME_OFFSET_F24_F25]
650        std     %f26, [%sp + FP_FRAME_OFFSET_F26_F27]
651        std     %f28, [%sp + FP_FRAME_OFFSET_F28_F29]
652        std     %f30, [%sp + FP_FRAME_OFFSET_F3O_F31]
653        st      %fsr, [%sp + FP_FRAME_OFFSET_FSR]
654        call    SYM(_Thread_Do_dispatch)
655         mov    %g6, %o0
656
657        /*
658         * Restore the floating point context from stack frame and release the
659         * stack frame.
660         */
661        ldd     [%sp + FP_FRAME_OFFSET_FO_F1], %f0
662        ldd     [%sp + FP_FRAME_OFFSET_F2_F3], %f2
663        ldd     [%sp + FP_FRAME_OFFSET_F4_F5], %f4
664        ldd     [%sp + FP_FRAME_OFFSET_F6_F7], %f6
665        ldd     [%sp + FP_FRAME_OFFSET_F8_F9], %f8
666        ldd     [%sp + FP_FRAME_OFFSET_F1O_F11], %f10
667        ldd     [%sp + FP_FRAME_OFFSET_F12_F13], %f12
668        ldd     [%sp + FP_FRAME_OFFSET_F14_F15], %f14
669        ldd     [%sp + FP_FRAME_OFFSET_F16_F17], %f16
670        ldd     [%sp + FP_FRAME_OFFSET_F18_F19], %f18
671        ldd     [%sp + FP_FRAME_OFFSET_F2O_F21], %f20
672        ldd     [%sp + FP_FRAME_OFFSET_F22_F23], %f22
673        ldd     [%sp + FP_FRAME_OFFSET_F24_F25], %f24
674        ldd     [%sp + FP_FRAME_OFFSET_F26_F27], %f26
675        ldd     [%sp + FP_FRAME_OFFSET_F28_F29], %f28
676        ldd     [%sp + FP_FRAME_OFFSET_F3O_F31], %f30
677        ld      [%sp + FP_FRAME_OFFSET_FSR], %fsr
678        ba      thread_dispatch_done
679         add    %sp, FP_FRAME_SIZE, %sp
680
681non_fp_thread_dispatch:
682#endif
683
684        call    SYM(_Thread_Do_dispatch)
685         mov    %g6, %o0
686
687#if SPARC_HAS_FPU == 1 && defined(SPARC_USE_SAFE_FP_SUPPORT)
688thread_dispatch_done:
689#endif
690
691        ta       SPARC_SWTRAP_IRQDIS ! **** DISABLE INTERRUPTS ****
692
693        /*
694         *  While we had ISR dispatching disabled in this thread,
695         *  did we miss anything?  If so, then we need to do another
696         *  _Thread_Do_dispatch() before leaving this ISR dispatch context.
697         */
698        ldub    [%g6 + PER_CPU_DISPATCH_NEEDED], %l7
699
700        orcc    %l7, %g0, %g0        ! Is a thread dispatch necessary?
701        bne     isr_dispatch         ! Yes, then invoke the dispatcher again.
702         mov    0, %o1               ! ISR level for _Thread_Do_dispatch()
703
704        /*
705         * No, then set the ISR dispatch disable flag to zero and continue with
706         * the simple return.
707         */
708        st       %g0, [%g6 + PER_CPU_ISR_DISPATCH_DISABLE]
709
710        /*
711         *  The CWP in place at this point may be different from
712         *  that which was in effect at the beginning of the ISR if we
713         *  have been context switched between the beginning of this invocation
714         *  of _ISR_Handler and this point.  Thus the CWP and WIM should
715         *  not be changed back to their values at ISR entry time.  Any
716         *  changes to the PSR must preserve the CWP.
717         */
718
719simple_return:
720        ld      [%fp + ISF_Y_OFFSET], %l5      ! restore y
721        wr      %l5, 0, %y
722
723        ldd     [%fp + ISF_PSR_OFFSET], %l0    ! restore psr, PC
724        ld      [%fp + ISF_NPC_OFFSET], %l2    ! restore nPC
725        rd      %psr, %l3
726        and     %l3, SPARC_PSR_CWP_MASK, %l3   ! want "current" CWP
727        andn    %l0, SPARC_PSR_CWP_MASK, %l0   ! want rest from task
728        or      %l3, %l0, %l0                  ! install it later...
729        andn    %l0, SPARC_PSR_ET_MASK, %l0
730
731        /*
732         *  Restore tasks global and out registers
733         */
734
735        mov    %fp, %g1
736
737                                              ! g1 is restored later
738        ldd     [%fp + ISF_G2_OFFSET], %g2    ! restore g2, g3
739        ldd     [%fp + ISF_G4_OFFSET], %g4    ! restore g4, g5
740        ld      [%fp + ISF_G7_OFFSET], %g7    ! restore g7
741
742        ldd     [%fp + ISF_I0_OFFSET], %i0    ! restore i0, i1
743        ldd     [%fp + ISF_I2_OFFSET], %i2    ! restore i2, i3
744        ldd     [%fp + ISF_I4_OFFSET], %i4    ! restore i4, i5
745        ldd     [%fp + ISF_I6_FP_OFFSET], %i6 ! restore i6/fp, i7
746
747        /*
748         *  Registers:
749         *
750         *   ALL global registers EXCEPT G1 and the input registers have
751         *   already been restored and thuse off limits.
752         *
753         *   The following is the contents of the local registers:
754         *
755         *     l0 = original psr
756         *     l1 = return address (i.e. PC)
757         *     l2 = nPC
758         *     l3 = CWP
759         */
760
761        /*
762         *  if (CWP + 1) is an invalid window then we need to reload it.
763         *
764         *  WARNING: Traps should now be disabled
765         */
766
767        mov     %l0, %psr                  !  **** DISABLE TRAPS ****
768        nop
769        nop
770        nop
771        rd      %wim, %l4
772        add     %l0, 1, %l6                ! l6 = cwp + 1
773        and     %l6, SPARC_PSR_CWP_MASK, %l6 ! do the modulo on it
774        srl     %l4, %l6, %l5              ! l5 = win >> cwp + 1 ; shift count
775                                           !  and CWP are conveniently LS 5 bits
776        cmp     %l5, 1                     ! Is tasks window invalid?
777        bne     good_task_window
778
779        /*
780         *  The following code is the same as a 1 position left rotate of WIM.
781         */
782
783        sll     %l4, 1, %l5                ! l5 = WIM << 1
784        srl     %l4, SPARC_NUMBER_OF_REGISTER_WINDOWS-1 , %l4
785                                           ! l4 = WIM >> (Number Windows - 1)
786        or      %l4, %l5, %l4              ! l4 = (WIM << 1) |
787                                           !      (WIM >> (Number Windows - 1))
788
789        /*
790         *  Now restore the window just as if we underflowed to it.
791         */
792
793        wr      %l4, 0, %wim               ! WIM = new WIM
794        nop                                ! must delay after writing WIM
795        nop
796        nop
797        restore                            ! now into the tasks window
798
799        ldd     [%g1 + CPU_STACK_FRAME_L0_OFFSET], %l0
800        ldd     [%g1 + CPU_STACK_FRAME_L2_OFFSET], %l2
801        ldd     [%g1 + CPU_STACK_FRAME_L4_OFFSET], %l4
802        ldd     [%g1 + CPU_STACK_FRAME_L6_OFFSET], %l6
803        ldd     [%g1 + CPU_STACK_FRAME_I0_OFFSET], %i0
804        ldd     [%g1 + CPU_STACK_FRAME_I2_OFFSET], %i2
805        ldd     [%g1 + CPU_STACK_FRAME_I4_OFFSET], %i4
806        ldd     [%g1 + CPU_STACK_FRAME_I6_FP_OFFSET], %i6
807                                           ! reload of sp clobbers ISF
808        save                               ! Back to ISR dispatch window
809
810good_task_window:
811
812        mov     %l0, %psr                  !  **** DISABLE TRAPS ****
813        nop; nop; nop
814                                           !  and restore condition codes.
815        ld      [%g1 + ISF_G1_OFFSET], %g1 ! restore g1
816        jmp     %l1                        ! transfer control and
817        rett    %l2                        ! go back to tasks window
818
819/* end of file */
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